/* Blackfin External Bus Interface Unit (EBIU) Asynchronous Memory Controller
(AMC) model.
- Copyright (C) 2010-2014 Free Software Foundation, Inc.
+ Copyright (C) 2010-2020 Free Software Foundation, Inc.
Contributed by Analog Devices, Inc.
This file is part of simulators.
{
bu32 amben_old, amben, addr, i;
- amben_old = MIN ((amc->amgctl >> 1) & 0x7, 4);
- amben = MIN ((amgctl >> 1) & 0x7, 4);
+ amben_old = min ((amc->amgctl >> 1) & 0x7, 4);
+ amben = min ((amgctl >> 1) & 0x7, 4);
HW_TRACE ((me, "reattaching banks: AMGCTL 0x%04x[%u] -> 0x%04x[%u]",
amc->amgctl, amben_old, amgctl, amben));
switch (mmr_off)
{
case mmr_offset(amgctl):
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
+ return 0;
bfin_ebiu_amc_write_amgctl (me, amc, value);
break;
case mmr_offset(bf50x.ambctl0):
break;
case mmr_offset(bf50x.mode):
/* XXX: implement this. */
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
+ return 0;
break;
case mmr_offset(bf50x.fctl):
/* XXX: implement this. */
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
+ return 0;
break;
default:
dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
- break;
+ return 0;
}
return nr_bytes;
switch (mmr_off)
{
case mmr_offset(amgctl):
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
+ return 0;
bfin_ebiu_amc_write_amgctl (me, amc, value);
break;
case mmr_offset(bf53x.ambctl0):
break;
default:
dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
- break;
+ return 0;
}
return nr_bytes;
switch (mmr_off)
{
case mmr_offset(amgctl):
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, true);
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
+ return 0;
bfin_ebiu_amc_write_amgctl (me, amc, value);
break;
case mmr_offset(bf54x.ambctl0):
break;
default:
dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
- break;
+ return 0;
}
return nr_bytes;
bu32 mmr_off;
bu32 value;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, true))
+ return 0;
+
value = dv_load_4 (source);
mmr_off = addr - amc->base;
{
case mmr_offset(amgctl):
case mmr_offset(bf50x.fctl):
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, false);
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, false))
+ return 0;
dv_store_2 (dest, *value16);
break;
case mmr_offset(bf50x.ambctl0):
break;
default:
dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
- break;
+ return 0;
}
return nr_bytes;
switch (mmr_off)
{
case mmr_offset(amgctl):
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, false);
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, false))
+ return 0;
dv_store_2 (dest, *value16);
break;
case mmr_offset(bf53x.ambctl0):
break;
default:
dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
- break;
+ return 0;
}
return nr_bytes;
switch (mmr_off)
{
case mmr_offset(amgctl):
- dv_bfin_mmr_require_16 (me, addr, nr_bytes, false);
+ if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, false))
+ return 0;
dv_store_2 (dest, *value16);
break;
case mmr_offset(bf54x.ambctl0):
break;
default:
dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
- break;
+ return 0;
}
return nr_bytes;
bu32 mmr_off;
void *valuep;
+ /* Invalid access mode is higher priority than missing register. */
+ if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, false))
+ return 0;
+
mmr_off = addr - amc->base;
valuep = (void *)((unsigned long)amc + mmr_base() + mmr_off);