sim: trace: add a basic cpu register class

[deliverable/binutils-gdb.git] / sim / bfin / dv-bfin_jtag.c

diff --git a/sim/bfin/dv-bfin_jtag.c b/sim/bfin/dv-bfin_jtag.c
index 78a3686ef56df5242f180338ab1ca3a822813eaa..0f34c687f77c2cbfe3779896f4ac46e90b21f6fe 100644 (file)
--- a/sim/bfin/dv-bfin_jtag.c
+++ b/sim/bfin/dv-bfin_jtag.c
@@ -1,6 +1,6 @@
 /* Blackfin JTAG model.
 
-   Copyright (C) 2010-2011 Free Software Foundation, Inc.
+   Copyright (C) 2010-2015 Free Software Foundation, Inc.
    Contributed by Analog Devices, Inc.
 
    This file is part of simulators.
@@ -63,7 +63,7 @@ bfin_jtag_io_write_buffer (struct hw *me, const void *source, int space,
   switch (mmr_off)
     {
     case mmr_offset(dbgstat):
-      dv_w1c_4 (valuep, value, ~0xc);
+      dv_w1c_4 (valuep, value, 0xc);
       break;
     case mmr_offset(dspid):
       /* Discard writes to these.  */
@@ -152,7 +152,8 @@ bfin_jtag_finish (struct hw *me)
   jtag->dspid = bfin_model_get_dspid (hw_system (me));
 }
 
-const struct hw_descriptor dv_bfin_jtag_descriptor[] = {
+const struct hw_descriptor dv_bfin_jtag_descriptor[] =
+{
   {"bfin_jtag", bfin_jtag_finish,},
   {NULL, NULL},
 };