ubsan: nds32: left shift cannot be represented in type 'int'

[deliverable/binutils-gdb.git] / sim / bfin / dv-bfin_rtc.c

diff --git a/sim/bfin/dv-bfin_rtc.c b/sim/bfin/dv-bfin_rtc.c
index ff70780d551802cf59c624e979c1c9c388d1ba49..2115acfcf50888345c3eee867e804304fe4458ab 100644 (file)
--- a/sim/bfin/dv-bfin_rtc.c
+++ b/sim/bfin/dv-bfin_rtc.c
@@ -1,6 +1,6 @@
 /* Blackfin Real Time Clock (RTC) model.
 
-   Copyright (C) 2010-2016 Free Software Foundation, Inc.
+   Copyright (C) 2010-2019 Free Software Foundation, Inc.
    Contributed by Analog Devices, Inc.
 
    This file is part of simulators.