sim: bfin: fix ASTAT issues in immediate shifts

[deliverable/binutils-gdb.git] / sim / bfin / dv-bfin_uart2.c

diff --git a/sim/bfin/dv-bfin_uart2.c b/sim/bfin/dv-bfin_uart2.c
index facde1c6cd24a3c6aaf3a650f7089e39b814eadb..4d36eff3d4209bb3f80ddfe62ac3d976f9985b36 100644 (file)
--- a/sim/bfin/dv-bfin_uart2.c
+++ b/sim/bfin/dv-bfin_uart2.c
@@ -1,7 +1,7 @@
 /* Blackfin Universal Asynchronous Receiver/Transmitter (UART) model.
    For "new style" UARTs on BF50x/BF54x parts.
 
-   Copyright (C) 2010-2011 Free Software Foundation, Inc.
+   Copyright (C) 2010-2012 Free Software Foundation, Inc.
    Contributed by Analog Devices, Inc.
 
    This file is part of simulators.
@@ -89,7 +89,7 @@ bfin_uart_io_write_buffer (struct hw *me, const void *source,
   switch (mmr_off)
     {
     case mmr_offset(thr):
-      uart->thr = bfin_uart_write_byte (me, value);
+      uart->thr = bfin_uart_write_byte (me, value, uart->mcr);
       if (uart->ier & ETBEI)
        hw_port_event (me, DV_PORT_TX, 1);
       break;
@@ -142,7 +142,7 @@ bfin_uart_io_read_buffer (struct hw *me, void *dest,
   switch (mmr_off)
     {
     case mmr_offset(rbr):
-      uart->rbr = bfin_uart_get_next_byte (me, uart->rbr, NULL);
+      uart->rbr = bfin_uart_get_next_byte (me, uart->rbr, uart->mcr, NULL);
       dv_store_2 (dest, uart->rbr);
       break;
     case mmr_offset(ier_set):
@@ -151,6 +151,7 @@ bfin_uart_io_read_buffer (struct hw *me, void *dest,
       bfin_uart_reschedule (me);
       break;
     case mmr_offset(lsr):
+      uart->lsr &= ~(DR | THRE | TEMT);
       uart->lsr |= bfin_uart_get_status (me);
     case mmr_offset(thr):
     case mmr_offset(msr):