gdb: add target_ops::supports_displaced_step

[deliverable/binutils-gdb.git] / sim / common / cgen-accfp.c

diff --git a/sim/common/cgen-accfp.c b/sim/common/cgen-accfp.c
index afbca6d582c1b7e3bfc8ce2df628f85da1fadf04..b898de3935e61617ea93d61a93a34088f7d3c081 100644 (file)
--- a/sim/common/cgen-accfp.c
+++ b/sim/common/cgen-accfp.c
@@ -92,6 +92,25 @@ divsf (CGEN_FPU* fpu, SF x, SF y)
   return res;
 }
 
+static SF
+remsf (CGEN_FPU* fpu, SF x, SF y)
+{
+  sim_fpu op1;
+  sim_fpu op2;
+  sim_fpu ans;
+  unsigned32 res;
+  sim_fpu_status status;
+
+  sim_fpu_32to (&op1, x);
+  sim_fpu_32to (&op2, y);
+  status = sim_fpu_rem (&ans, &op1, &op2);
+  if (status != 0)
+    (*fpu->ops->error) (fpu, status);
+  sim_fpu_to32 (&res, &ans);
+
+  return res;
+}
+
 static SF
 negsf (CGEN_FPU* fpu, SF x)
 {
@@ -284,6 +303,18 @@ gesf (CGEN_FPU* fpu, SF x, SF y)
   return sim_fpu_is_ge (&op1, &op2);
 }
 
+static int
+unorderedsf (CGEN_FPU* fpu, SF x, SF y)
+{
+  sim_fpu op1;
+  sim_fpu op2;
+
+  sim_fpu_32to (&op1, x);
+  sim_fpu_32to (&op2, y);
+  return sim_fpu_is_nan (&op1) || sim_fpu_is_nan (&op2);
+}
+
+
 static DF
 fextsfdf (CGEN_FPU* fpu, int how UNUSED, SF x)
 {
@@ -330,6 +361,17 @@ floatsidf (CGEN_FPU* fpu, int how UNUSED, SI x)
   return res;
 }
 
+static DF
+floatdidf (CGEN_FPU* fpu, int how UNUSED, DI x)
+{
+  sim_fpu ans;
+  unsigned64 res;
+
+  sim_fpu_i64to (&ans, x, sim_fpu_round_near);
+  sim_fpu_to64 (&res, &ans);
+  return res;
+}
+
 static SF
 ufloatsisf (CGEN_FPU* fpu, int how UNUSED, USI x)
 {
@@ -363,6 +405,17 @@ fixdfsi (CGEN_FPU* fpu, int how UNUSED, DF x)
   return res;
 }
 
+static DI
+fixdfdi (CGEN_FPU* fpu, int how UNUSED, DF x)
+{
+  sim_fpu op1;
+  unsigned64 res;
+
+  sim_fpu_64to (&op1, x);
+  sim_fpu_to64i (&res, &op1, sim_fpu_round_near);
+  return res;
+}
+
 static USI
 ufixsfsi (CGEN_FPU* fpu, int how UNUSED, SF x)
 {
@@ -452,6 +505,25 @@ divdf (CGEN_FPU* fpu, DF x, DF y)
   return res;
 }
 
+static DF
+remdf (CGEN_FPU* fpu, DF x, DF y)
+{
+  sim_fpu op1;
+  sim_fpu op2;
+  sim_fpu ans;
+  unsigned64 res;
+  sim_fpu_status status;
+
+  sim_fpu_64to (&op1, x);
+  sim_fpu_64to (&op2, y);
+  status = sim_fpu_rem (&ans, &op1, &op2);
+  if (status != 0)
+    (*fpu->ops->error) (fpu, status);
+  sim_fpu_to64(&res, &ans);
+
+  return res;
+}
+
 static DF
 negdf (CGEN_FPU* fpu, DF x)
 {
@@ -643,6 +715,17 @@ gedf (CGEN_FPU* fpu, DF x, DF y)
   sim_fpu_64to (&op2, y);
   return sim_fpu_is_ge (&op1, &op2);
 }
+
+static int
+unordereddf (CGEN_FPU* fpu, DF x, DF y)
+{
+  sim_fpu op1;
+  sim_fpu op2;
+
+  sim_fpu_64to (&op1, x);
+  sim_fpu_64to (&op2, y);
+  return sim_fpu_is_nan (&op1) || sim_fpu_is_nan (&op2);
+}
 \f
 /* Initialize FP_OPS to use accurate library.  */
 
@@ -664,6 +747,7 @@ cgen_init_accurate_fpu (SIM_CPU* cpu, CGEN_FPU* fpu, CGEN_FPU_ERROR_FN* error)
   o->subsf = subsf;
   o->mulsf = mulsf;
   o->divsf = divsf;
+  o->remsf = remsf;
   o->negsf = negsf;
   o->abssf = abssf;
   o->sqrtsf = sqrtsf;
@@ -677,11 +761,13 @@ cgen_init_accurate_fpu (SIM_CPU* cpu, CGEN_FPU* fpu, CGEN_FPU_ERROR_FN* error)
   o->lesf = lesf;
   o->gtsf = gtsf;
   o->gesf = gesf;
+  o->unorderedsf = unorderedsf;
 
   o->adddf = adddf;
   o->subdf = subdf;
   o->muldf = muldf;
   o->divdf = divdf;
+  o->remdf = remdf;
   o->negdf = negdf;
   o->absdf = absdf;
   o->sqrtdf = sqrtdf;
@@ -695,12 +781,15 @@ cgen_init_accurate_fpu (SIM_CPU* cpu, CGEN_FPU* fpu, CGEN_FPU_ERROR_FN* error)
   o->ledf = ledf;
   o->gtdf = gtdf;
   o->gedf = gedf;
+  o->unordereddf = unordereddf;
   o->fextsfdf = fextsfdf;
   o->ftruncdfsf = ftruncdfsf;
   o->floatsisf = floatsisf;
   o->floatsidf = floatsidf;
+  o->floatdidf = floatdidf;
   o->ufloatsisf = ufloatsisf;
   o->fixsfsi = fixsfsi;
   o->fixdfsi = fixdfsi;
+  o->fixdfdi = fixdfdi;
   o->ufixsfsi = ufixsfsi;
 }