x86: drop a few dead macros

[deliverable/binutils-gdb.git] / sim / common / cgen-defs.h

diff --git a/sim/common/cgen-defs.h b/sim/common/cgen-defs.h
index d3c9a8ae57baddea2e8b2bd974756d914d29b191..3ab39c2b6fecd3801b499cce50ff89dcf0564cec 100644 (file)
--- a/sim/common/cgen-defs.h
+++ b/sim/common/cgen-defs.h
@@ -1,22 +1,21 @@
 /* General Cpu tools GENerated simulator support.
-   Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+   Copyright (C) 1996-2019 Free Software Foundation, Inc.
    Contributed by Cygnus Support.
 
 This file is part of GDB, the GNU debugger.
 
 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+the Free Software Foundation; either version 3 of the License, or
+(at your option) any later version.
 
 This program is distributed in the hope that it will be useful,
 but WITHOUT ANY WARRANTY; without even the implied warranty of
 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+You should have received a copy of the GNU General Public License
+along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
 
 #ifndef CGEN_DEFS_H
 #define CGEN_DEFS_H
@@ -92,6 +91,15 @@ typedef SCACHE *SEM_PC;
 #else
 typedef IADDR SEM_PC;
 #endif
+
+/* Kinds of branches.  */
+typedef enum {
+  SEM_BRANCH_UNTAKEN,
+  /* Branch to an uncacheable address (e.g. j reg).  */
+  SEM_BRANCH_UNCACHEABLE,
+  /* Branch to a cacheable (fixed) address.  */
+  SEM_BRANCH_CACHEABLE
+} SEM_BRANCH_TYPE;
 \f
 /* Virtual insn support.  */
 
@@ -106,7 +114,7 @@ typedef enum {
   VIRTUAL_INSN_X_CHAIN= -4, VIRTUAL_INSN_X_CTI_CHAIN = -5
 } CGEN_INSN_VIRTUAL_TYPE;
 
-/* Return non-zero if OPCODE is a virtual insn.  */
+/* Return non-zero if CGEN_INSN* INSN is a virtual insn.  */
 #define CGEN_INSN_VIRTUAL_P(insn) \
   CGEN_INSN_ATTR_VALUE ((insn), CGEN_INSN_VIRTUAL)
 \f
@@ -121,7 +129,7 @@ typedef enum {
 #define CASE(N, X) case_##N##_##X
 #define BREAK(N) goto end_switch_##N
 #define DEFAULT(N) default_##N
-#define ENDSWITCH(N) end_switch_##N:
+#define ENDSWITCH(N) end_switch_##N:;
 #else
 #define SWITCH(N, X) switch (X)
 #define CASE(N, X) case X /* FIXME: old sem-switch had (@arch@_,X) here */
@@ -132,24 +140,10 @@ typedef enum {
 \f
 /* Simulator state.  */
 
-/* Records simulator descriptor so utilities like @cpu@_dump_regs can be
-   called from gdb.  */
-extern SIM_DESC current_state;
-
-/* Simulator state.  */
-
 /* CGEN_STATE contains additional state information not present in
    sim_state_base.  */
 
 typedef struct cgen_state {
-  /* FIXME: Moved to sim_state_base.  */
-  /* argv, env */
-  char **argv;
-#define STATE_ARGV(s) ((s) -> cgen_state.argv)
-  /* FIXME: Move to sim_state_base.  */
-  char **envp;
-#define STATE_ENVP(s) ((s) -> cgen_state.envp)
-
   /* Non-zero if no tracing or profiling is selected.  */
   int run_fast_p;
 #define STATE_RUN_FAST_P(sd) ((sd) -> cgen_state.run_fast_p)
@@ -168,7 +162,7 @@ extern CPU_INSN_NAME_FN cgen_insn_name;
    language [or suggest a better way].  */
 extern int cgen_cpu_max_extra_bytes (void);
 
-/* Called to process an invalid instruction.  */
-extern void sim_engine_invalid_insn (SIM_CPU *, IADDR);
+/* Target supplied routine to process an invalid instruction.  */
+extern SEM_PC sim_engine_invalid_insn (SIM_CPU *, IADDR, SEM_PC);
 
 #endif /* CGEN_DEFS_H */