-/* Simulator header for the cgen engine.
+/* Engine header for Cpu tools GENerated simulators.
Copyright (C) 1998 Free Software Foundation, Inc.
Contributed by Cygnus Support.
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
-/* This file must be included after eng.h and ${cpu}.h have been included. */
-
-#ifndef CGEN_ENGINE_H
-#define CGEN_ENGINE_H
+/* This file must be included after eng.h and before ${cpu}.h. */
/* Semantic functions come in six versions on two axes:
fast/full-featured, and using one of the simple/scache/compilation engines.
/* FIXME: --enable-sim-fast not implemented yet. */
/* FIXME: undecided how to handle WITH_SCACHE_PBB. */
+#ifndef CGEN_ENGINE_H
+#define CGEN_ENGINE_H
+
+/* Instruction field support macros. */
+
+#define EXTRACT_MSB0_INT(val, total, start, length) \
+(((INT) (val) << ((sizeof (INT) * 8) - (total) + (start))) \
+ >> ((sizeof (INT) * 8) - (length)))
+#define EXTRACT_MSB0_UINT(val, total, start, length) \
+(((UINT) (val) << ((sizeof (UINT) * 8) - (total) + (start))) \
+ >> ((sizeof (UINT) * 8) - (length)))
+
+#define EXTRACT_LSB0_INT(val, total, start, length) \
+(((INT) (val) << ((sizeof (INT) * 8) - (start) - (length))) \
+ >> ((sizeof (INT) * 8) - (length)))
+#define EXTRACT_LSB0_UINT(val, total, start, length) \
+(((UINT) (val) << ((sizeof (UINT) * 8) - (start) - (length))) \
+ >> ((sizeof (UINT) * 8) - (length)))
+
+#if CGEN_INSN_LSB0_P
+
+#define EXTRACT_INT(val, total, start, length) \
+ EXTRACT_LSB0_INT ((val), (total), (start), (length))
+#define EXTRACT_UINT(val, total, start, length) \
+ EXTRACT_LSB0_UINT ((val), (total), (start), (length))
+
+#else
+
+#define EXTRACT_INT(val, total, start, length) \
+ EXTRACT_MSB0_INT ((val), (total), (start), (length))
+#define EXTRACT_UINT(val, total, start, length) \
+ EXTRACT_MSB0_UINT ((val), (total), (start), (length))
+
+#endif
+\f
+/* union sem */
+
/* Types of the machine generated extract and semantic fns. */
typedef void (EXTRACT_FN) (SIM_CPU *, PCADDR, insn_t, ARGBUF *);
#if HAVE_PARALLEL_INSNS
else \
SEM_SET_FULL_CODE ((abuf), (idesc)); \
} while (0)
-
+\f
#define IDESC_CTI_P(idesc) \
((CGEN_ATTR_BOOLS (CGEN_INSN_ATTRS ((idesc)->opcode)) \
& (CGEN_ATTR_MASK (CGEN_INSN_COND_CTI) \
/* These are used so that we can compile two copies of the semantic code,
one with full feature support and one without that runs fast(er). */
-/* FIXME: Eventually delete extraction if not using scache. */
-#define EX_FN_NAME(cpu,fn) XCONCAT3 (cpu,_ex_,fn)
#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_sem_,fn)
#define SEMF_FN_NAME(cpu,fn) XCONCAT3 (cpu,_semf_,fn)
/* semantics.c support */
#define SEM_ARGBUF(sem_arg) (& (sem_arg) -> argbuf)
#define SEM_INSN(sem_arg) shouldnt_be_used
-#define SEM_NEXT_VPC(sc, len) ((sc) + 1)
#if WITH_SCACHE_PBB
+/* Return the scache pointer of the current insn. */
+#define SEM_SEM_ARG(vpc, sc) (vpc)
+/* Return the virtual pc of the next insn to execute
+ (assuming this isn't a cti). */
+#define SEM_NEXT_VPC(sem_arg, pc, len) ((sem_arg) + 1)
+
/* Update the instruction counter. */
#define PBB_UPDATE_INSN_COUNT(cpu,sc) \
(CPU_INSN_COUNT (cpu) += SEM_ARGBUF (sc) -> fields.chain.insn_count)
address (e.g. j reg). */
#define SEM_BRANCH_UNCACHEABLE ((SEM_PC *) 1)
-/* ??? Only necessary if SEM_BRANCH_VIA_CACHE will be used,
- but for simplicity it's done this way. */
+/* Initialize next-pbb link for SEM_BRANCH_VIA_CACHE. */
#define SEM_BRANCH_INIT_EXTRACT(abuf) \
do { (abuf)->fields.cti.addr_cache = 0; } while (0)
generated by genmloop.sh. It exists so generated semantic code needn't
care whether it's being put in a switch or in a function. */
#ifdef SEM_IN_SWITCH
-/* Do not append a `;' to invocations of this.
- ??? Unnecessary here, but for consistency with ..._INIT. */
-#define SEM_BRANCH_FINI \
-{ \
+#define SEM_BRANCH_FINI(pcvar) \
+do { \
pbb_br_npc = npc; \
pbb_br_npc_ptr = npc_ptr; \
-}
+} while (0)
#else /* 1 semantic function per instruction */
-/* Do not append a `;' to invocations of this.
- ??? Unnecessary here, but for consistency with ..._INIT. */
-#define SEM_BRANCH_FINI \
-{ \
+#define SEM_BRANCH_FINI(pcvar) \
+do { \
CPU_PBB_BR_NPC (current_cpu) = npc; \
CPU_PBB_BR_NPC_PTR (current_cpu) = npc_ptr; \
-}
+} while (0)
#endif
/* Return address of cached branch address value. */
#else /* ! WITH_SCACHE_PBB */
-#define SEM_BRANCH_INIT
-#define SEM_BRANCH_FINI
+#define SEM_SEM_ARG(vpc, sc) (sc)
+#define SEM_NEXT_VPC(sem_arg, pc, len) ((pc) + (len))
+
+#define SEM_BRANCH_INIT_EXTRACT(abuf) do { } while (0)
+
+#define SEM_BRANCH_INIT \
+ int taken_p = 0;
+#ifndef TARGET_SEM_BRANCH_FINI(pcvar, taken_p)
+#define TARGET_SEM_BRANCH_FINI(pcvar, taken_p)
+#endif
+#define SEM_BRANCH_FINI(pcvar) \
+ do { TARGET_SEM_BRANCH_FINI (pcvar, taken_p); } while (0)
#define SEM_BRANCH_ADDR_CACHE(sem_arg) shouldnt_be_used
#define SEM_BRANCH_VIA_CACHE(cpu, sc, newval, pcvar, cachevar) \
do { \
(pcvar) = (newval); \
+ taken_p = 1; \
} while (0)
#define SEM_BRANCH_VIA_ADDR(cpu, sc, newval, pcvar) \
do { \
(pcvar) = (newval); \
+ taken_p = 1; \
} while (0)
#endif /* ! WITH_SCACHE_PBB */
-/* Return address a branch insn will branch to.
- This is only used during tracing. */
-#define SEM_NEW_PC_ADDR(new_pc) (new_pc)
-
#else /* ! WITH_SCACHE */
#define CIA_ADDR(cia) (cia)
/* semantics.c support */
#define SEM_ARGBUF(sem_arg) (sem_arg)
-#define SEM_INSN(sem_arg) (SEM_ARGBUF (sem_arg) -> insn)
-/* FIXME:wip */
-#define SEM_NEXT_VPC(abuf, len) ((abuf) -> addr + (abuf) -> length)
+#define SEM_INSN(sem_arg) (SEM_ARGBUF (sem_arg) -> base_insn)
-#define SEM_BRANCH_INIT
-#define SEM_BRANCH_FINI
+#define SEM_SEM_ARG(vpc, sc) (sc)
+#define SEM_NEXT_VPC(sem_arg, pc, len) ((pc) + (len))
+
+#define SEM_BRANCH_INIT \
+ int taken_p = 0;
+#ifndef TARGET_SEM_BRANCH_FINI
+#define TARGET_SEM_BRANCH_FINI(pcvar, taken_p)
+#endif
+#define SEM_BRANCH_FINI(pcvar) \
+ do { TARGET_SEM_BRANCH_FINI (pcvar, taken_p); } while (0)
#define SEM_BRANCH_ADDR_CACHE(sem_arg) shouldnt_be_used
#define SEM_BRANCH_VIA_CACHE(cpu, abuf, newval, pcvar, cachevar) \
do { \
(pcvar) = (newval); \
+ taken_p = 1; \
} while (0)
#define SEM_BRANCH_VIA_ADDR(cpu, abuf, newval, pcvar) \
do { \
(pcvar) = (newval); \
+ taken_p = 1; \
} while (0)
-#define SEM_NEW_PC_ADDR(new_pc) (new_pc)
-
#endif /* ! WITH_SCACHE */
+\f
+/* Tracing/profiling. */
+
+/* Return non-zero if a before/after handler is needed.
+ When tracing/profiling a selected range there's no need to slow
+ down simulation of the other insns (except to get more accurate data!).
+
+ ??? May wish to profile all insns if doing insn tracing, or to
+ get more accurate cycle data.
+
+ First test ANY_P so we avoid a potentially expensive HIT_P call
+ [if there are lots of address ranges]. */
+
+#define PC_IN_TRACE_RANGE_P(cpu, pc) \
+ (TRACE_ANY_P (cpu) \
+ && ADDR_RANGE_HIT_P (TRACE_RANGE (CPU_TRACE_DATA (cpu)), (pc)))
+#define PC_IN_PROFILE_RANGE_P(cpu, pc) \
+ (PROFILE_ANY_P (cpu) \
+ && ADDR_RANGE_HIT_P (PROFILE_RANGE (CPU_PROFILE_DATA (cpu)), (pc)))
#endif /* CGEN_ENGINE_H */
projects / deliverable / binutils-gdb.git / blobdiff