# Generate the main loop of the simulator.
-# Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+# Copyright (C) 1996-2020 Free Software Foundation, Inc.
# Contributed by Cygnus Support.
#
# This file is part of the GNU simulators.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
-# You should have received a copy of the GNU General Public License along
-# with this program; if not, write to the Free Software Foundation, Inc.,
-# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
# This file creates two files: eng.hin and mloop.cin.
# eng.hin defines a few macros that specify what kind of engine was selected
#
# -parallel-read: support parallel execution with read-before-exec support.
# -parallel-write: support parallel execution with write-after-exec support.
+# -parallel-generic-write: support parallel execution with generic queued
+# writes.
#
# One of these options is specified in addition to -simple, -scache,
# -pbb. Note that while the code can determine if the cpu supports
# technically unnecessary], having this option cuts down on the clutter
# in the result.
#
+# -parallel-only: semantic code only supports parallel version of insn
+#
+# Semantic code only supports parallel versions of each insn.
+# Things can be sped up by generating both serial and parallel versions
+# and is better suited to mixed parallel architectures like the m32r.
+#
+# -prefix: string to prepend to function names in mloop.c/eng.h.
+#
+# If no prefix is specified, the cpu type is used.
+#
# -switch file: specify file containing semantics implemented as a switch()
#
# -cpu <cpu-family>
#
# Specify the mainloop.in input file.
#
+# -outfile-suffix <output-file-suffix>
+#
+# Specify the suffix to append to output files.
+#
+# -shell <shell>
+#
+# Specify the shell to use to execute <input-file>
+#
# Only one of -scache/-pbb may be selected.
# -simple is the default.
#
#full_switch=
#pbb=
parallel=no
+parallel_only=no
switch=
cpu="unknown"
infile=""
+prefix="unknown"
+outsuffix=""
while test $# -gt 0
do
-scache) scache=yes ;;
-pbb) pbb=yes ;;
-no-parallel) ;;
+ -outfile-suffix) shift ; outsuffix=$1 ;;
-parallel-read) parallel=read ;;
-parallel-write) parallel=write ;;
+ -parallel-generic-write) parallel=genwrite ;;
+ -parallel-only) parallel_only=yes ;;
+ -prefix) shift ; prefix=$1 ;;
-switch) shift ; switch=$1 ;;
-cpu) shift ; cpu=$1 ;;
-infile) shift ; infile=$1 ;;
+ -shell) shift ; SHELL=$1 ;;
*) echo "unknown option: $1" >&2 ; exit 1 ;;
esac
shift
exit 1
fi
+if [ "x$prefix" = xunknown ] ; then
+ prefix=$cpu
+fi
+
lowercase='abcdefghijklmnopqrstuvwxyz'
uppercase='ABCDEFGHIJKLMNOPQRSTUVWXYZ'
CPU=`echo ${cpu} | tr "${lowercase}" "${uppercase}"`
+PREFIX=`echo ${prefix} | tr "${lowercase}" "${uppercase}"`
##########################################################################
-rm -f eng.hin
-exec 1>eng.hin
+rm -f eng${outsuffix}.hin
+exec 1>eng${outsuffix}.hin
echo "/* engine configuration for ${cpu} */"
echo ""
fi
echo ""
-echo "/* WITH_SCACHE_PBB_${CPU}: non-zero if the pbb engine was selected. */"
+echo "/* WITH_SCACHE_PBB_${PREFIX}: non-zero if the pbb engine was selected. */"
if [ x$pbb = xyes ] ; then
- echo "#define WITH_SCACHE_PBB_${CPU} 1"
+ echo "#define WITH_SCACHE_PBB_${PREFIX} 1"
else
- echo "#define WITH_SCACHE_PBB_${CPU} 0"
+ echo "#define WITH_SCACHE_PBB_${PREFIX} 0"
fi
echo ""
echo "/* HAVE_PARALLEL_INSNS: non-zero if cpu can parallelly execute > 1 insn. */"
-if [ x$parallel != xno ] ; then
- echo "#define HAVE_PARALLEL_INSNS 1"
- if [ x$parallel = xread ] ; then
- echo "/* Parallel execution is supported by read-before-exec. */"
- echo "#define WITH_PARALLEL_READ 1"
- echo "#define WITH_PARALLEL_WRITE 0"
- else
- echo "/* Parallel execution is supported by write-after-exec. */"
- echo "#define WITH_PARALLEL_READ 0"
- echo "#define WITH_PARALLEL_WRITE 1"
- fi
-else
- echo "#define HAVE_PARALLEL_INSNS 0"
- echo "#define WITH_PARALLEL_READ 0"
- echo "#define WITH_PARALLEL_WRITE 0"
-fi
+# blah blah blah, other ways to do this, blah blah blah
+case x$parallel in
+xno)
+ echo "#define HAVE_PARALLEL_INSNS 0"
+ echo "#define WITH_PARALLEL_READ 0"
+ echo "#define WITH_PARALLEL_WRITE 0"
+ echo "#define WITH_PARALLEL_GENWRITE 0"
+ ;;
+xread)
+ echo "#define HAVE_PARALLEL_INSNS 1"
+ echo "/* Parallel execution is supported by read-before-exec. */"
+ echo "#define WITH_PARALLEL_READ 1"
+ echo "#define WITH_PARALLEL_WRITE 0"
+ echo "#define WITH_PARALLEL_GENWRITE 0"
+ ;;
+xwrite)
+ echo "#define HAVE_PARALLEL_INSNS 1"
+ echo "/* Parallel execution is supported by write-after-exec. */"
+ echo "#define WITH_PARALLEL_READ 0"
+ echo "#define WITH_PARALLEL_WRITE 1"
+ echo "#define WITH_PARALLEL_GENWRITE 0"
+ ;;
+xgenwrite)
+ echo "#define HAVE_PARALLEL_INSNS 1"
+ echo "/* Parallel execution is supported by generic write-after-exec. */"
+ echo "#define WITH_PARALLEL_READ 0"
+ echo "#define WITH_PARALLEL_WRITE 0"
+ echo "#define WITH_PARALLEL_GENWRITE 1"
+ ;;
+esac
if [ "x$switch" != x ] ; then
echo ""
echo "/* Functions defined in the generated mainloop.c file"
echo " (which doesn't necessarily have that file name). */"
echo ""
-echo "extern ENGINE_FN ${cpu}_engine_run_full;"
-echo "extern ENGINE_FN ${cpu}_engine_run_fast;"
+echo "extern ENGINE_FN ${prefix}_engine_run_full;"
+echo "extern ENGINE_FN ${prefix}_engine_run_fast;"
if [ x$pbb = xyes ] ; then
echo ""
- echo "extern SEM_PC ${cpu}_pbb_begin (SIM_CPU *, int);"
- echo "extern SEM_PC ${cpu}_pbb_chain (SIM_CPU *, SEM_ARG);"
- echo "extern SEM_PC ${cpu}_pbb_cti_chain (SIM_CPU *, SEM_ARG, SEM_BRANCH_TYPE, PCADDR);"
- echo "extern void ${cpu}_pbb_before (SIM_CPU *, SCACHE *);"
- echo "extern void ${cpu}_pbb_after (SIM_CPU *, SCACHE *);"
+ echo "extern SEM_PC ${prefix}_pbb_begin (SIM_CPU *, int);"
+ echo "extern SEM_PC ${prefix}_pbb_chain (SIM_CPU *, SEM_ARG);"
+ echo "extern SEM_PC ${prefix}_pbb_cti_chain (SIM_CPU *, SEM_ARG, SEM_BRANCH_TYPE, PCADDR);"
+ echo "extern void ${prefix}_pbb_before (SIM_CPU *, SCACHE *);"
+ echo "extern void ${prefix}_pbb_after (SIM_CPU *, SCACHE *);"
fi
##########################################################################
-rm -f tmp-mloop.cin mloop.cin
-exec 1>tmp-mloop.cin
+rm -f tmp-mloop-$$.cin mloop${outsuffix}.cin
+exec 1>tmp-mloop-$$.cin
# We use @cpu@ instead of ${cpu} because we still need to run sed to handle
# transformation of @cpu@ for mainloop.in, so there's no need to use ${cpu}
virtual and real. */
static INLINE void
-@cpu@_fill_argbuf (const SIM_CPU *cpu, ARGBUF *abuf, const IDESC *idesc,
+@prefix@_fill_argbuf (const SIM_CPU *cpu, ARGBUF *abuf, const IDESC *idesc,
PCADDR pc, int fast_p)
{
#if WITH_SCACHE
/* Fill in tracing/profiling fields of an ARGBUF. */
static INLINE void
-@cpu@_fill_argbuf_tp (const SIM_CPU *cpu, ARGBUF *abuf,
+@prefix@_fill_argbuf_tp (const SIM_CPU *cpu, ARGBUF *abuf,
int trace_p, int profile_p)
{
ARGBUF_TRACE_P (abuf) = trace_p;
of parallel insns. */
static INLINE void
-@cpu@_emit_before (SIM_CPU *current_cpu, SCACHE *sc, PCADDR pc, int first_p)
+@prefix@_emit_before (SIM_CPU *current_cpu, SCACHE *sc, PCADDR pc, int first_p)
{
ARGBUF *abuf = &sc[0].argbuf;
- const IDESC *id = & CPU_IDESC (current_cpu) [@CPU@_INSN_X_BEFORE];
+ const IDESC *id = & CPU_IDESC (current_cpu) [@PREFIX@_INSN_X_BEFORE];
abuf->fields.before.first_p = first_p;
- @cpu@_fill_argbuf (current_cpu, abuf, id, pc, 0);
+ @prefix@_fill_argbuf (current_cpu, abuf, id, pc, 0);
/* no need to set trace_p,profile_p */
}
parallel insns. */
static INLINE void
-@cpu@_emit_after (SIM_CPU *current_cpu, SCACHE *sc, PCADDR pc)
+@prefix@_emit_after (SIM_CPU *current_cpu, SCACHE *sc, PCADDR pc)
{
ARGBUF *abuf = &sc[0].argbuf;
- const IDESC *id = & CPU_IDESC (current_cpu) [@CPU@_INSN_X_AFTER];
+ const IDESC *id = & CPU_IDESC (current_cpu) [@PREFIX@_INSN_X_AFTER];
- @cpu@_fill_argbuf (current_cpu, abuf, id, pc, 0);
+ @prefix@_fill_argbuf (current_cpu, abuf, id, pc, 0);
/* no need to set trace_p,profile_p */
}
#define FAST_P 0
void
-@cpu@_engine_run_full (SIM_CPU *current_cpu)
+@prefix@_engine_run_full (SIM_CPU *current_cpu)
{
#define FAST_P 0
SIM_DESC current_state = CPU_STATE (current_cpu);
EOF
-if [ x$parallel != xno ] ; then
- cat << EOF
+case x$parallel in
+xread | xwrite)
+ cat << EOF
PAREXEC pbufs[MAX_PARALLEL_INSNS];
PAREXEC *par_exec;
EOF
-fi
+ ;;
+esac
# Any initialization code before looping starts.
# Note that this code may declare some locals.
#include "$switch"
#endif
#else
- @cpu@_sem_init_idesc_table (current_cpu);
+ @prefix@_sem_init_idesc_table (current_cpu);
#endif
CPU_IDESC_SEM_INIT_P (current_cpu) = 1;
}
cat << EOF
static INLINE SCACHE *
-@cpu@_scache_lookup (SIM_CPU *current_cpu, PCADDR vpc, SCACHE *scache,
+@prefix@_scache_lookup (SIM_CPU *current_cpu, PCADDR vpc, SCACHE *scache,
unsigned int hash_mask, int FAST_P)
{
/* First step: look up current insn in hash table. */
#define FAST_P 0
void
-@cpu@_engine_run_full (SIM_CPU *current_cpu)
+@prefix@_engine_run_full (SIM_CPU *current_cpu)
{
SIM_DESC current_state = CPU_STATE (current_cpu);
SCACHE *scache = CPU_SCACHE_CACHE (current_cpu);
if (! CPU_IDESC_SEM_INIT_P (current_cpu))
{
#if ! WITH_SEM_SWITCH_FULL
- @cpu@_sem_init_idesc_table (current_cpu);
+ @prefix@_sem_init_idesc_table (current_cpu);
#endif
CPU_IDESC_SEM_INIT_P (current_cpu) = 1;
}
{
SCACHE *sc;
- sc = @cpu@_scache_lookup (current_cpu, vpc, scache, hash_mask, FAST_P);
+ sc = @prefix@_scache_lookup (current_cpu, vpc, scache, hash_mask, FAST_P);
/* begin full-exec-scache */
EOF
#define FAST_P 1
void
-@cpu@_engine_run_fast (SIM_CPU *current_cpu)
+@prefix@_engine_run_fast (SIM_CPU *current_cpu)
{
SIM_DESC current_state = CPU_STATE (current_cpu);
SCACHE *scache = CPU_SCACHE_CACHE (current_cpu);
#include "$switch"
#endif
#else
- @cpu@_semf_init_idesc_table (current_cpu);
+ @prefix@_semf_init_idesc_table (current_cpu);
#endif
CPU_IDESC_SEM_INIT_P (current_cpu) = 1;
}
{
SCACHE *sc;
- sc = @cpu@_scache_lookup (current_cpu, vpc, scache, hash_mask, FAST_P);
+ sc = @prefix@_scache_lookup (current_cpu, vpc, scache, hash_mask, FAST_P);
/* begin fast-exec-scache */
EOF
cat << EOF
static INLINE SCACHE *
-@cpu@_scache_lookup (SIM_CPU *current_cpu, PCADDR vpc, SCACHE *scache,
- unsigned int hash_mask, int *last_insn_p, int FAST_P)
+@prefix@_scache_lookup (SIM_CPU *current_cpu, PCADDR vpc, SCACHE *scache,
+ unsigned int hash_mask, int FAST_P)
{
/* First step: look up current insn in hash table. */
SCACHE *sc = scache + SCACHE_HASH_PC (vpc, hash_mask);
if (! FAST_P)
PROFILE_COUNT_SCACHE_MISS (current_cpu);
-#define SET_LAST_INSN_P(last_p) do { *last_insn_p = (last_p); } while (0)
+#define SET_LAST_INSN_P(last_p) do { sc->last_insn_p = (last_p); } while (0)
/* begin extract-scache */
EOF
#define FAST_P 0
void
-@cpu@_engine_run_full (SIM_CPU *current_cpu)
+@prefix@_engine_run_full (SIM_CPU *current_cpu)
{
SIM_DESC current_state = CPU_STATE (current_cpu);
SCACHE *scache = CPU_SCACHE_CACHE (current_cpu);
if (! CPU_IDESC_SEM_INIT_P (current_cpu))
{
#if ! WITH_SEM_SWITCH_FULL
- @cpu@_sem_init_idesc_table (current_cpu);
+ @prefix@_sem_init_idesc_table (current_cpu);
#endif
CPU_IDESC_SEM_INIT_P (current_cpu) = 1;
}
#define FAST_P 1
void
-@cpu@_engine_run_fast (SIM_CPU *current_cpu)
+@prefix@_engine_run_fast (SIM_CPU *current_cpu)
{
SIM_DESC current_state = CPU_STATE (current_cpu);
SCACHE *scache = CPU_SCACHE_CACHE (current_cpu);
#include "$switch"
#endif
#else
- @cpu@_semf_init_idesc_table (current_cpu);
+ @prefix@_semf_init_idesc_table (current_cpu);
#endif
CPU_IDESC_SEM_INIT_P (current_cpu) = 1;
}
FAST_P is non-zero if no tracing/profiling/etc. is wanted. */
INLINE SEM_PC
-@cpu@_pbb_begin (SIM_CPU *current_cpu, int FAST_P)
+@prefix@_pbb_begin (SIM_CPU *current_cpu, int FAST_P)
{
SEM_PC new_vpc;
PCADDR pc;
/* Was pbb terminated by a cti? */
if (_cti_sc)
{
- id = & CPU_IDESC (current_cpu) [@CPU@_INSN_X_CTI_CHAIN];
+ id = & CPU_IDESC (current_cpu) [@PREFIX@_INSN_X_CTI_CHAIN];
}
else
{
- id = & CPU_IDESC (current_cpu) [@CPU@_INSN_X_CHAIN];
+ id = & CPU_IDESC (current_cpu) [@PREFIX@_INSN_X_CHAIN];
}
SEM_SET_CODE (&sc->argbuf, id, FAST_P);
sc->argbuf.idesc = id;
/* Chain to the next block from a non-cti terminated previous block. */
INLINE SEM_PC
-@cpu@_pbb_chain (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+@prefix@_pbb_chain (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
BR_TYPE != SEM_BRANCH_UNTAKEN. */
INLINE SEM_PC
-@cpu@_pbb_cti_chain (SIM_CPU *current_cpu, SEM_ARG sem_arg,
+@prefix@_pbb_cti_chain (SIM_CPU *current_cpu, SEM_ARG sem_arg,
SEM_BRANCH_TYPE br_type, PCADDR new_pc)
{
SEM_PC *new_vpc_ptr;
This is called before each insn. */
void
-@cpu@_pbb_before (SIM_CPU *current_cpu, SCACHE *sc)
+@prefix@_pbb_before (SIM_CPU *current_cpu, SCACHE *sc)
{
SEM_ARG sem_arg = sc;
const ARGBUF *abuf = SEM_ARGBUF (sem_arg);
if (ARGBUF_PROFILE_P (prev_abuf))
{
cycles = (*prev_idesc->timing->model_fn) (current_cpu, prev_sem_arg);
- @cpu@_model_insn_after (current_cpu, 0 /*last_p*/, cycles);
+ @prefix@_model_insn_after (current_cpu, 0 /*last_p*/, cycles);
}
}
- TRACE_INSN_FINI (current_cpu, cur_abuf, 0 /*last_p*/);
+ CGEN_TRACE_INSN_FINI (current_cpu, cur_abuf, 0 /*last_p*/);
}
/* FIXME: Later make cover macros: PROFILE_INSN_{INIT,FINI}. */
if (PROFILE_MODEL_P (current_cpu)
&& ARGBUF_PROFILE_P (cur_abuf))
- @cpu@_model_insn_before (current_cpu, first_p);
+ @prefix@_model_insn_before (current_cpu, first_p);
- TRACE_INSN_INIT (current_cpu, cur_abuf, first_p);
- TRACE_INSN (current_cpu, cur_idesc->idata, cur_abuf, pc);
+ CGEN_TRACE_INSN_INIT (current_cpu, cur_abuf, first_p);
+ CGEN_TRACE_INSN (current_cpu, cur_idesc->idata, cur_abuf, pc);
}
/* x-after handler.
insns. */
void
-@cpu@_pbb_after (SIM_CPU *current_cpu, SCACHE *sc)
+@prefix@_pbb_after (SIM_CPU *current_cpu, SCACHE *sc)
{
SEM_ARG sem_arg = sc;
const ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int cycles;
cycles = (*prev_idesc->timing->model_fn) (current_cpu, prev_sem_arg);
- @cpu@_model_insn_after (current_cpu, 1 /*last_p*/, cycles);
+ @prefix@_model_insn_after (current_cpu, 1 /*last_p*/, cycles);
}
- TRACE_INSN_FINI (current_cpu, prev_abuf, 1 /*last_p*/);
+ CGEN_TRACE_INSN_FINI (current_cpu, prev_abuf, 1 /*last_p*/);
}
#define FAST_P 0
void
-@cpu@_engine_run_full (SIM_CPU *current_cpu)
+@prefix@_engine_run_full (SIM_CPU *current_cpu)
{
SIM_DESC current_state = CPU_STATE (current_cpu);
SCACHE *scache = CPU_SCACHE_CACHE (current_cpu);
EOF
-if [ x$parallel != xno ] ; then
- cat << EOF
+case x$parallel in
+xread | xwrite)
+ cat << EOF
PAREXEC pbufs[MAX_PARALLEL_INSNS];
PAREXEC *par_exec = &pbufs[0];
EOF
-fi
+ ;;
+esac
# Any initialization code before looping starts.
# Note that this code may declare some locals.
#include "$switch"
#endif
#else
- @cpu@_sem_init_idesc_table (current_cpu);
+ @prefix@_sem_init_idesc_table (current_cpu);
#endif
/* Initialize the "begin (compile) a pbb" virtual insn. */
vpc = CPU_SCACHE_PBB_BEGIN (current_cpu);
SEM_SET_FULL_CODE (SEM_ARGBUF (vpc),
- & CPU_IDESC (current_cpu) [@CPU@_INSN_X_BEGIN]);
- vpc->argbuf.idesc = & CPU_IDESC (current_cpu) [@CPU@_INSN_X_BEGIN];
+ & CPU_IDESC (current_cpu) [@PREFIX@_INSN_X_BEGIN]);
+ vpc->argbuf.idesc = & CPU_IDESC (current_cpu) [@PREFIX@_INSN_X_BEGIN];
CPU_IDESC_SEM_INIT_P (current_cpu) = 1;
}
pbb we don't want to call pbb_begin each time (which hashes on the pc
and does a table lookup). A way to speed this up is to save vpc
between calls. */
- vpc = @cpu@_pbb_begin (current_cpu, FAST_P);
+ vpc = @prefix@_pbb_begin (current_cpu, FAST_P);
do
{
#define FAST_P 1
void
-@cpu@_engine_run_fast (SIM_CPU *current_cpu)
+@prefix@_engine_run_fast (SIM_CPU *current_cpu)
{
SIM_DESC current_state = CPU_STATE (current_cpu);
SCACHE *scache = CPU_SCACHE_CACHE (current_cpu);
EOF
-if [ x$parallel != xno ] ; then
- cat << EOF
+case x$parallel in
+xread | xwrite)
+ cat << EOF
PAREXEC pbufs[MAX_PARALLEL_INSNS];
PAREXEC *par_exec = &pbufs[0];
EOF
-fi
+ ;;
+esac
# Any initialization code before looping starts.
# Note that this code may declare some locals.
#include "$switch"
#endif
#else
- @cpu@_semf_init_idesc_table (current_cpu);
+ @prefix@_semf_init_idesc_table (current_cpu);
#endif
/* Initialize the "begin (compile) a pbb" virtual insn. */
vpc = CPU_SCACHE_PBB_BEGIN (current_cpu);
SEM_SET_FAST_CODE (SEM_ARGBUF (vpc),
- & CPU_IDESC (current_cpu) [@CPU@_INSN_X_BEGIN]);
- vpc->argbuf.idesc = & CPU_IDESC (current_cpu) [@CPU@_INSN_X_BEGIN];
+ & CPU_IDESC (current_cpu) [@PREFIX@_INSN_X_BEGIN]);
+ vpc->argbuf.idesc = & CPU_IDESC (current_cpu) [@PREFIX@_INSN_X_BEGIN];
CPU_IDESC_SEM_INIT_P (current_cpu) = 1;
}
pbb we don't want to call pbb_begin each time (which hashes on the pc
and does a table lookup). A way to speed this up is to save vpc
between calls. */
- vpc = @cpu@_pbb_begin (current_cpu, FAST_P);
+ vpc = @prefix@_pbb_begin (current_cpu, FAST_P);
do
{
fi # -pbb
-# Process @cpu@,@CPU@ appearing in mainloop.in.
-sed -e "s/@cpu@/$cpu/g" -e "s/@CPU@/$CPU/g" < tmp-mloop.cin > mloop.cin
+# Expand @..@ macros appearing in tmp-mloop-{pid}.cin.
+sed \
+ -e "s/@cpu@/$cpu/g" -e "s/@CPU@/$CPU/g" \
+ -e "s/@prefix@/$prefix/g" -e "s/@PREFIX@/$PREFIX/g" < tmp-mloop-$$.cin > mloop${outsuffix}.cin
rc=$?
-rm -f tmp-mloop.cin
+rm -f tmp-mloop-$$.cin
exit $rc
projects / deliverable / binutils-gdb.git / blobdiff