*/
-#ifndef _SIM_CORE_H_
-#define _SIM_CORE_H_
+#ifndef SIM_CORE_H
+#define SIM_CORE_H
-/* core signals (error conditions) */
+/* core signals (error conditions)
+ Define SIM_CORE_SIGNAL to catch these signals - see sim-core.c for
+ details. */
typedef enum {
sim_core_unmapped_signal,
nr_sim_core_signals,
} sim_core_signals;
-/* define SIM_CORE_SIGNAL to catch these signals - see sim-core.c for
- details */
+/* Type of SIM_CORE_SIGNAL handler. */
+typedef void (SIM_CORE_SIGNAL_FN)
+ (SIM_DESC sd, sim_cpu *cpu, sim_cia cia, unsigned map, int nr_bytes,
+ address_word addr, transfer_type transfer, sim_core_signals sig);
+extern SIM_CORE_SIGNAL_FN sim_core_signal;
/* basic types */
void *free_buffer;
void *buffer;
/* callback map */
+#if (WITH_HW)
+ struct hw *device;
+#else
device *device;
+#endif
/* tracing */
int trace;
/* growth */
sim_core_mapping *first;
};
-typedef enum {
- sim_core_read_map,
- sim_core_write_map,
- sim_core_execute_map,
- nr_sim_core_maps,
-} sim_core_maps;
-
typedef struct _sim_core_common {
- sim_core_map map[nr_sim_core_maps];
+ sim_core_map map[nr_maps];
} sim_core_common;
/* Install the "core" module. */
-EXTERN_SIM_CORE\
-(SIM_RC) sim_core_install (SIM_DESC sd);
+extern SIM_RC sim_core_install (SIM_DESC sd);
-/* Create a memory space within the core.
+/* Create a memory region within the core.
- CPU, when non NULL, specifes the single processor that the memory
- space is to be attached to. (UNIMPLEMENTED).
+ CPU - when non NULL, specifes the single processor that the memory
+ space is to be attached to. (INIMPLEMENTED).
- LEVEL specifies the ordering of the memory region. Lower regions
+ LEVEL - specifies the ordering of the memory region. Lower regions
are searched first. Within a level, memory regions can not
overlap.
- DEVICE, when non NULL, specifies a callback memory space.
- (UNIMPLEMENTED, see the ppc simulator for an example).
+ MAPMASK - Bitmask specifying the memory maps that the region is to
+ be attached to. Typically the enums sim-basics.h:access_* are used.
+
+ ADDRESS_SPACE - For device regions, a MAP:ADDRESS pair is
+ translated into ADDRESS_SPACE:OFFSET before being passed to the
+ client device.
- MODULO, when the simulator has been configured WITH_MODULO support
+ MODULO - when the simulator has been configured WITH_MODULO support
and is greater than zero, specifies that accesses to the region
[ADDR .. ADDR+NR_BYTES) should be mapped onto the sub region [ADDR
.. ADDR+MODULO). The modulo value must be a power of two.
- OPTIONAL_BUFFER, when non NULL, specifies the buffer to use for
+ DEVICE - When non NULL, indicates that this is a callback memory
+ space and specified device's memory callback handler should be
+ called.
+
+ OPTIONAL_BUFFER - when non NULL, specifies the buffer to use for
data read & written to the region. Normally a more efficient
internal structure is used. It is assumed that buffer is allocated
such that the byte alignmed of OPTIONAL_BUFFER matches ADDR vis
- (OPTIONAL_BUFFER % 8) == (ADDR % 8)) */
+ (OPTIONAL_BUFFER % 8) == (ADDR % 8)). It is defined to be a sub-optimal
+ hook that allows clients to do nasty things that the interface doesn't
+ accomodate. */
-EXTERN_SIM_CORE\
-(void) sim_core_attach
+extern void sim_core_attach
(SIM_DESC sd,
sim_cpu *cpu,
int level,
- access_type access,
+ unsigned mapmask,
int address_space,
address_word addr,
address_word nr_bytes,
unsigned modulo,
+#if (WITH_HW)
+ struct hw *client,
+#else
device *client,
+#endif
void *optional_buffer);
-/* Delete a memory space within the core.
+/* Delete a memory section within the core.
*/
-EXTERN_SIM_CORE\
-(void) sim_core_detach
+extern void sim_core_detach
(SIM_DESC sd,
sim_cpu *cpu,
int level,
address map that is to be used in the transfer. */
-EXTERN_SIM_CORE\
-(unsigned) sim_core_read_buffer
+extern unsigned sim_core_read_buffer
(SIM_DESC sd,
sim_cpu *cpu,
- sim_core_maps map,
+ unsigned map,
void *buffer,
address_word addr,
unsigned nr_bytes);
-EXTERN_SIM_CORE\
-(unsigned) sim_core_write_buffer
+extern unsigned sim_core_write_buffer
(SIM_DESC sd,
sim_cpu *cpu,
- sim_core_maps map,
+ unsigned map,
const void *buffer,
address_word addr,
unsigned nr_bytes);
The CPU argument, when non NULL, specifes the single processor that
the xor-endian configuration is to be applied to. */
-EXTERN_SIM_CORE\
-(void) sim_core_set_xor\
+extern void sim_core_set_xor
(SIM_DESC sd,
sim_cpu *cpu,
int is_xor);
If CPU argument, when non NULL, specifies the processor specific
address map that is to be used in the transfer. */
-EXTERN_SIM_CORE\
-(unsigned) sim_core_xor_read_buffer
+extern unsigned sim_core_xor_read_buffer
(SIM_DESC sd,
sim_cpu *cpu,
- sim_core_maps map,
+ unsigned map,
void *buffer,
address_word addr,
unsigned nr_bytes);
-EXTERN_SIM_CORE\
-(unsigned) sim_core_xor_write_buffer
+extern unsigned sim_core_xor_write_buffer
(SIM_DESC sd,
sim_cpu *cpu,
- sim_core_maps map,
+ unsigned map,
const void *buffer,
address_word addr,
unsigned nr_bytes);
order (including xor endian). Should the transfer fail, the
operation shall abort (no return).
- The aligned alternative makes the assumption that that the address
- is N byte aligned (no alignment checks are made).
+ ALIGNED assumes yhat the specified ADDRESS is correctly alligned
+ for an N byte transfer (no alignment checks are made). Passing an
+ incorrectly aligned ADDRESS is erroneous.
+
+ UNALIGNED checks/modifies the ADDRESS according to the requirements
+ of an N byte transfer. Action, as defined by WITH_ALIGNMENT, being
+ taken should the check fail.
- The unaligned alternative checks the address for correct byte
- alignment. Action, as defined by WITH_ALIGNMENT, being taken
- should the check fail.
+ MISSALIGNED transfers the data regardless.
Misaligned xor-endian accesses are broken into a sequence of
transfers each <= WITH_XOR_ENDIAN bytes */
-#define DECLARE_SIM_CORE_WRITE_N(ALIGNMENT,N) \
+#define DECLARE_SIM_CORE_WRITE_N(ALIGNMENT,N,M) \
INLINE_SIM_CORE\
(void) sim_core_write_##ALIGNMENT##_##N \
(sim_cpu *cpu, \
sim_cia cia, \
- sim_core_maps map, \
+ unsigned map, \
address_word addr, \
- unsigned_##N val);
+ unsigned_##M val);
-DECLARE_SIM_CORE_WRITE_N(aligned,1)
-DECLARE_SIM_CORE_WRITE_N(aligned,2)
-DECLARE_SIM_CORE_WRITE_N(aligned,4)
-DECLARE_SIM_CORE_WRITE_N(aligned,8)
-DECLARE_SIM_CORE_WRITE_N(aligned,16)
+DECLARE_SIM_CORE_WRITE_N(aligned,1,1)
+DECLARE_SIM_CORE_WRITE_N(aligned,2,2)
+DECLARE_SIM_CORE_WRITE_N(aligned,4,4)
+DECLARE_SIM_CORE_WRITE_N(aligned,8,8)
+DECLARE_SIM_CORE_WRITE_N(aligned,16,16)
-DECLARE_SIM_CORE_WRITE_N(unaligned,1)
-DECLARE_SIM_CORE_WRITE_N(unaligned,2)
-DECLARE_SIM_CORE_WRITE_N(unaligned,4)
-DECLARE_SIM_CORE_WRITE_N(unaligned,8)
-DECLARE_SIM_CORE_WRITE_N(unaligned,16)
+#define sim_core_write_unaligned_1 sim_core_write_aligned_1
+DECLARE_SIM_CORE_WRITE_N(unaligned,2,2)
+DECLARE_SIM_CORE_WRITE_N(unaligned,4,4)
+DECLARE_SIM_CORE_WRITE_N(unaligned,8,8)
+DECLARE_SIM_CORE_WRITE_N(unaligned,16,16)
+DECLARE_SIM_CORE_WRITE_N(misaligned,3,4)
+DECLARE_SIM_CORE_WRITE_N(misaligned,5,8)
+DECLARE_SIM_CORE_WRITE_N(misaligned,6,8)
+DECLARE_SIM_CORE_WRITE_N(misaligned,7,8)
#define sim_core_write_1 sim_core_write_aligned_1
#define sim_core_write_2 sim_core_write_aligned_2
#undef DECLARE_SIM_CORE_WRITE_N
-#define DECLARE_SIM_CORE_READ_N(ALIGNMENT,N) \
+#define DECLARE_SIM_CORE_READ_N(ALIGNMENT,N,M) \
INLINE_SIM_CORE\
-(unsigned_##N) sim_core_read_##ALIGNMENT##_##N \
+(unsigned_##M) sim_core_read_##ALIGNMENT##_##N \
(sim_cpu *cpu, \
sim_cia cia, \
- sim_core_maps map, \
+ unsigned map, \
address_word addr);
-DECLARE_SIM_CORE_READ_N(aligned,1)
-DECLARE_SIM_CORE_READ_N(aligned,2)
-DECLARE_SIM_CORE_READ_N(aligned,4)
-DECLARE_SIM_CORE_READ_N(aligned,8)
-DECLARE_SIM_CORE_READ_N(aligned,16)
+DECLARE_SIM_CORE_READ_N(aligned,1,1)
+DECLARE_SIM_CORE_READ_N(aligned,2,2)
+DECLARE_SIM_CORE_READ_N(aligned,4,4)
+DECLARE_SIM_CORE_READ_N(aligned,8,8)
+DECLARE_SIM_CORE_READ_N(aligned,16,16)
+
+#define sim_core_read_unaligned_1 sim_core_read_aligned_1
+DECLARE_SIM_CORE_READ_N(unaligned,2,2)
+DECLARE_SIM_CORE_READ_N(unaligned,4,4)
+DECLARE_SIM_CORE_READ_N(unaligned,8,8)
+DECLARE_SIM_CORE_READ_N(unaligned,16,16)
+
+DECLARE_SIM_CORE_READ_N(misaligned,3,4)
+DECLARE_SIM_CORE_READ_N(misaligned,5,8)
+DECLARE_SIM_CORE_READ_N(misaligned,6,8)
+DECLARE_SIM_CORE_READ_N(misaligned,7,8)
-DECLARE_SIM_CORE_READ_N(unaligned,1)
-DECLARE_SIM_CORE_READ_N(unaligned,2)
-DECLARE_SIM_CORE_READ_N(unaligned,4)
-DECLARE_SIM_CORE_READ_N(unaligned,8)
-DECLARE_SIM_CORE_READ_N(unaligned,16)
#define sim_core_read_1 sim_core_read_aligned_1
#define sim_core_read_2 sim_core_read_aligned_2
#undef DECLARE_SIM_CORE_READ_N
+
+#if (WITH_DEVICES)
+/* TODO: create sim/common/device.h */
+/* These are defined with each particular cpu. */
+void device_error (device *me, char* message, ...);
+int device_io_read_buffer(device *me, void *dest, int space, address_word addr, unsigned nr_bytes, SIM_DESC sd, sim_cpu *processor, sim_cia cia);
+int device_io_write_buffer(device *me, const void *source, int space, address_word addr, unsigned nr_bytes, SIM_DESC sd, sim_cpu *processor, sim_cia cia);
+#endif
+
+
#endif
projects / deliverable / binutils-gdb.git / blobdiff