ubsan: nds32: left shift cannot be represented in type 'int'

[deliverable/binutils-gdb.git] / sim / cris / modelv10.c

diff --git a/sim/cris/modelv10.c b/sim/cris/modelv10.c
index 38fd850722441b7baf0bef3047614f5d426fb2f0..8299ac4e69826a101c279c4eae863de76f88ff7d 100644 (file)
--- a/sim/cris/modelv10.c
+++ b/sim/cris/modelv10.c
@@ -2,7 +2,7 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996-2009 Free Software Foundation, Inc.
+Copyright 1996-2019 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
@@ -17,8 +17,7 @@ This file is part of the GNU simulators.
    License for more details.
 
    You should have received a copy of the GNU General Public License along
-   with this program; if not, write to the Free Software Foundation, Inc.,
-   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+   with this program; if not, see <http://www.gnu.org/licenses/>.
 
 */
 
@@ -37,7 +36,7 @@ This file is part of the GNU simulators.
 static int
 model_crisv10_nop (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_empty.f
+#define FLD(f) abuf->fields.sfmt_empty.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1160,7 +1159,7 @@ model_crisv10_move_spr_mv10 (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_crisv10_sbfs (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_empty.f
+#define FLD(f) abuf->fields.sfmt_empty.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -1561,7 +1560,7 @@ model_crisv10_addscwr (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_crisv10_addspcpc (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_empty.f
+#define FLD(f) abuf->fields.sfmt_empty.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -4114,7 +4113,7 @@ crisv10_model_init (SIM_CPU *cpu)
 #define TIMING_DATA(td) 0
 #endif
 
-static const MODEL crisv10_models[] =
+static const SIM_MODEL crisv10_models[] =
 {
   { "crisv10", & crisv10_mach, MODEL_CRISV10, TIMING_DATA (& crisv10_timing[0]), crisv10_model_init },
   { 0 }
@@ -4122,7 +4121,7 @@ static const MODEL crisv10_models[] =
 
 /* The properties of this cpu's implementation.  */
 
-static const MACH_IMP_PROPERTIES crisv10f_imp_properties =
+static const SIM_MACH_IMP_PROPERTIES crisv10f_imp_properties =
 {
   sizeof (SIM_CPU),
 #if WITH_SCACHE
@@ -4164,7 +4163,7 @@ crisv10_init_cpu (SIM_CPU *cpu)
 #endif
 }
 
-const MACH crisv10_mach =
+const SIM_MACH crisv10_mach =
 {
   "crisv10", "cris", MACH_CRISV10,
   32, 32, & crisv10_models[0], & crisv10f_imp_properties,