Document the fact that the assembler's alignment pseudo-ops can be issued without...

[deliverable/binutils-gdb.git] / sim / cris / modelv32.c

diff --git a/sim/cris/modelv32.c b/sim/cris/modelv32.c
index 1f429ac38495c4358875c5f7000c301320d5d219..0b10be52268b1ffc448ae5c9d4e2ec1c40f0fffc 100644 (file)
--- a/sim/cris/modelv32.c
+++ b/sim/cris/modelv32.c
@@ -2,22 +2,22 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996-2005 Free Software Foundation, Inc.
+Copyright 1996-2020 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 3 of the License, or
-(at your option) any later version.
+   This file is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program.  If not, see <http://www.gnu.org/licenses/>.
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, see <http://www.gnu.org/licenses/>.
 
 */
 
@@ -4683,7 +4683,7 @@ model_crisv32_sfe (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_crisv32_rfg (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_empty.f
+#define FLD(f) abuf->fields.sfmt_empty.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -4721,7 +4721,7 @@ model_crisv32_rfn (SIM_CPU *current_cpu, void *sem_arg)
 static int
 model_crisv32_halt (SIM_CPU *current_cpu, void *sem_arg)
 {
-#define FLD(f) abuf->fields.fmt_empty.f
+#define FLD(f) abuf->fields.sfmt_empty.f
   const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
   const IDESC * UNUSED idesc = abuf->idesc;
   int cycles = 0;
@@ -5904,7 +5904,7 @@ crisv32_model_init (SIM_CPU *cpu)
 #define TIMING_DATA(td) 0
 #endif
 
-static const MODEL crisv32_models[] =
+static const SIM_MODEL crisv32_models[] =
 {
   { "crisv32", & crisv32_mach, MODEL_CRISV32, TIMING_DATA (& crisv32_timing[0]), crisv32_model_init },
   { 0 }
@@ -5912,7 +5912,7 @@ static const MODEL crisv32_models[] =
 
 /* The properties of this cpu's implementation.  */
 
-static const MACH_IMP_PROPERTIES crisv32f_imp_properties =
+static const SIM_MACH_IMP_PROPERTIES crisv32f_imp_properties =
 {
   sizeof (SIM_CPU),
 #if WITH_SCACHE
@@ -5954,7 +5954,7 @@ crisv32_init_cpu (SIM_CPU *cpu)
 #endif
 }
 
-const MACH crisv32_mach =
+const SIM_MACH crisv32_mach =
 {
   "crisv32", "crisv32", MACH_CRISV32,
   32, 32, & crisv32_models[0], & crisv32f_imp_properties,