#include <signal.h>
#include "sysdep.h"
#include "bfd.h"
-#include "callback.h"
-#include "remote-sim.h"
+#include "gdb/callback.h"
+#include "gdb/remote-sim.h"
#include "d10v_sim.h"
-
-#define IMEM_SIZE 18 /* D10V instruction memory size is 18 bits */
-#define DMEM_SIZE 16 /* Data memory is 64K (but only 32K internal RAM) */
-#define UMEM_SIZE 17 /* Each unified memory segment is 17 bits */
-#define UMEM_SEGMENTS 128 /* Number of segments in unified memory region */
+#include "gdb/sim-d10v.h"
enum _leftright { LEFT_FIRST, RIGHT_FIRST };
static char *myname;
static SIM_OPEN_KIND sim_kind;
int d10v_debug;
+
+/* Set this to true to get the previous segment layout. */
+
+int old_segment_mapping;
+
host_callback *d10v_callback;
unsigned long ins_type_counters[ (int)INS_MAX ];
static char *add_commas PARAMS ((char *buf, int sizeof_buf, unsigned long value));
extern void sim_set_profile PARAMS ((int n));
extern void sim_set_profile_size PARAMS ((int n));
+static INLINE uint8 *map_memory (unsigned phys_addr);
+
+#ifdef NEED_UI_LOOP_HOOK
+/* How often to run the ui_loop update, when in use */
+#define UI_LOOP_POLL_INTERVAL 0x14000
+
+/* Counter for the ui_loop_hook update */
+static long ui_loop_hook_counter = UI_LOOP_POLL_INTERVAL;
+
+/* Actual hook to call to run through gdb's gui event loop */
+extern int (*ui_loop_hook) PARAMS ((int signo));
+#endif /* NEED_UI_LOOP_HOOK */
#ifndef INLINE
#if defined(__GNUC__) && defined(__OPTIMIZE__)
struct hash_entry
{
struct hash_entry *next;
- long opcode;
- long mask;
+ uint32 opcode;
+ uint32 mask;
int size;
struct simops *ops;
};
{
if (h->next == NULL)
{
- (*d10v_callback->printf_filtered) (d10v_callback, "ERROR looking up hash for %x at PC %x\n",ins, PC);
- exit (1);
+ State.exception = SIGILL;
+ State.pc_changed = 1; /* Don't increment the PC. */
+ return NULL;
}
h = h->next;
}
mask = 0x7FFFFFFF >> (31 - bits);
OP[i] = (ins >> shift) & mask;
}
+ /* FIXME: for tracing, update values that need to be updated each
+ instruction decode cycle */
+ State.trace.psw = PSW;
}
bfd_vma
(*d10v_callback->printf_filtered) (d10v_callback, "do_long 0x%x\n", ins);
#endif
h = lookup_hash (ins, 1);
+ if (h == NULL)
+ return;
get_operands (h->ops, ins);
State.ins_type = INS_LONG;
ins_type_counters[ (int)State.ins_type ]++;
enum _leftright leftright;
{
struct hash_entry *h;
- reg_t orig_pc = PC;
enum _ins_type first, second;
#ifdef DEBUG
ins_type_counters[ (int)INS_RIGHTLEFT ]++;
}
+ /* Issue the first instruction */
h = lookup_hash (ins1, 0);
+ if (h == NULL)
+ return;
get_operands (h->ops, ins1);
State.ins_type = first;
ins_type_counters[ (int)State.ins_type ]++;
(h->ops->func)();
- /* If the PC has changed (ie, a jump), don't do the second instruction */
- if (orig_pc == PC && !State.exception)
+ /* Issue the second instruction (if the PC hasn't changed) */
+ if (!State.pc_changed && !State.exception)
{
+ /* finish any existing instructions */
+ SLOT_FLUSH ();
h = lookup_hash (ins2, 0);
+ if (h == NULL)
+ return;
get_operands (h->ops, ins2);
State.ins_type = second;
ins_type_counters[ (int)State.ins_type ]++;
ins_type_counters[ (int)INS_CYCLES ]++;
(h->ops->func)();
}
- else if (orig_pc != PC && !State.exception)
+ else if (!State.exception)
ins_type_counters[ (int)INS_COND_JUMP ]++;
}
#endif
ins_type_counters[ (int)INS_PARALLEL ]++;
h1 = lookup_hash (ins1, 0);
+ if (h1 == NULL)
+ return;
h2 = lookup_hash (ins2, 0);
+ if (h2 == NULL)
+ return;
if (h1->ops->exec_type == PARONLY)
{
{
int i;
-
- if (State.imem)
+ for (i = 0; i < IMEM_SEGMENTS; i++)
{
- for (i=0;i<UMEM_SEGMENTS;i++)
- {
- if (State.umem[i])
- {
- free (State.umem[i]);
- State.umem[i] = NULL;
- }
- }
- free (State.imem);
- free (State.dmem);
+ if (State.mem.insn[i])
+ free (State.mem.insn[i]);
}
-
- State.imem = (uint8 *)calloc(1,1<<IMEM_SIZE);
- State.dmem = (uint8 *)calloc(1,1<<DMEM_SIZE);
- for (i=1;i<(UMEM_SEGMENTS-1);i++)
- State.umem[i] = NULL;
- State.umem[0] = (uint8 *)calloc(1,1<<UMEM_SIZE);
- State.umem[1] = (uint8 *)calloc(1,1<<UMEM_SIZE);
- State.umem[2] = (uint8 *)calloc(1,1<<UMEM_SIZE);
- State.umem[UMEM_SEGMENTS-1] = (uint8 *)calloc(1,1<<UMEM_SIZE);
- if (!State.imem || !State.dmem || !State.umem[0] || !State.umem[1] || !State.umem[2] || !State.umem[UMEM_SEGMENTS-1] )
+ for (i = 0; i < DMEM_SEGMENTS; i++)
{
- (*d10v_callback->printf_filtered) (d10v_callback, "Memory allocation failed.\n");
- exit(1);
+ if (State.mem.data[i])
+ free (State.mem.data[i]);
}
-
+ for (i = 0; i < UMEM_SEGMENTS; i++)
+ {
+ if (State.mem.unif[i])
+ free (State.mem.unif[i]);
+ }
+ /* Always allocate dmem segment 0. This contains the IMAP and DMAP
+ registers. */
+ State.mem.data[0] = calloc (1, SEGMENT_SIZE);
+}
+
+/* For tracing - leave info on last access around. */
+static char *last_segname = "invalid";
+static char *last_from = "invalid";
+static char *last_to = "invalid";
+
+enum
+ {
+ IMAP0_OFFSET = 0xff00,
+ DMAP0_OFFSET = 0xff08,
+ DMAP2_SHADDOW = 0xff04,
+ DMAP2_OFFSET = 0xff0c
+ };
+
+static void
+set_dmap_register (int reg_nr, unsigned long value)
+{
+ uint8 *raw = map_memory (SIM_D10V_MEMORY_DATA
+ + DMAP0_OFFSET + 2 * reg_nr);
+ WRITE_16 (raw, value);
#ifdef DEBUG
- if ((d10v_debug & DEBUG_MEMSIZE) != 0)
+ if ((d10v_debug & DEBUG_MEMORY))
{
- char buffer[20];
- (*d10v_callback->printf_filtered) (d10v_callback,
- "Allocated %s bytes instruction memory and\n",
- add_commas (buffer, sizeof (buffer), (1UL<<IMEM_SIZE)));
+ (*d10v_callback->printf_filtered)
+ (d10v_callback, "mem: dmap%d=0x%04lx\n", reg_nr, value);
+ }
+#endif
+}
+
+static unsigned long
+dmap_register (void *regcache, int reg_nr)
+{
+ uint8 *raw = map_memory (SIM_D10V_MEMORY_DATA
+ + DMAP0_OFFSET + 2 * reg_nr);
+ return READ_16 (raw);
+}
- (*d10v_callback->printf_filtered) (d10v_callback, " %s bytes data memory.\n",
- add_commas (buffer, sizeof (buffer), (1UL<<IMEM_SIZE)));
+static void
+set_imap_register (int reg_nr, unsigned long value)
+{
+ uint8 *raw = map_memory (SIM_D10V_MEMORY_DATA
+ + IMAP0_OFFSET + 2 * reg_nr);
+ WRITE_16 (raw, value);
+#ifdef DEBUG
+ if ((d10v_debug & DEBUG_MEMORY))
+ {
+ (*d10v_callback->printf_filtered)
+ (d10v_callback, "mem: imap%d=0x%04lx\n", reg_nr, value);
}
#endif
}
-/* Transfer data to/from simulated memory. Since a bug in either the
- simulated program or in gdb or the simulator itself may cause a
- bogus address to be passed in, we need to do some sanity checking
- on addresses to make sure they are within bounds. When an address
- fails the bounds check, treat it as a zero length read/write rather
- than aborting the entire run. */
+static unsigned long
+imap_register (void *regcache, int reg_nr)
+{
+ uint8 *raw = map_memory (SIM_D10V_MEMORY_DATA
+ + IMAP0_OFFSET + 2 * reg_nr);
+ return READ_16 (raw);
+}
-static int
-xfer_mem (SIM_ADDR addr,
- unsigned char *buffer,
- int size,
- int write_p)
+enum
+ {
+ HELD_SPI_IDX = 0,
+ HELD_SPU_IDX = 1
+ };
+
+static unsigned long
+spu_register (void)
{
- unsigned char *memory;
- int segment = ((addr >> 24) & 0xff);
- addr = (addr & 0x00ffffff);
+ if (PSW_SM)
+ return GPR (SP_IDX);
+ else
+ return HELD_SP (HELD_SPU_IDX);
+}
-#ifdef DEBUG
- if ((d10v_debug & DEBUG_INSTRUCTION) != 0)
+static unsigned long
+spi_register (void)
+{
+ if (!PSW_SM)
+ return GPR (SP_IDX);
+ else
+ return HELD_SP (HELD_SPI_IDX);
+}
+
+static void
+set_spi_register (unsigned long value)
+{
+ if (!PSW_SM)
+ SET_GPR (SP_IDX, value);
+ SET_HELD_SP (HELD_SPI_IDX, value);
+}
+
+static void
+set_spu_register (unsigned long value)
+{
+ if (PSW_SM)
+ SET_GPR (SP_IDX, value);
+ SET_HELD_SP (HELD_SPU_IDX, value);
+}
+
+/* Given a virtual address in the DMAP address space, translate it
+ into a physical address. */
+
+unsigned long
+sim_d10v_translate_dmap_addr (unsigned long offset,
+ int nr_bytes,
+ unsigned long *phys,
+ void *regcache,
+ unsigned long (*dmap_register) (void *regcache,
+ int reg_nr))
+{
+ short map;
+ int regno;
+ last_from = "logical-data";
+ if (offset >= DMAP_BLOCK_SIZE * SIM_D10V_NR_DMAP_REGS)
+ {
+ /* Logical address out side of data segments, not supported */
+ return 0;
+ }
+ regno = (offset / DMAP_BLOCK_SIZE);
+ offset = (offset % DMAP_BLOCK_SIZE);
+ if ((offset % DMAP_BLOCK_SIZE) + nr_bytes > DMAP_BLOCK_SIZE)
+ {
+ /* Don't cross a BLOCK boundary */
+ nr_bytes = DMAP_BLOCK_SIZE - (offset % DMAP_BLOCK_SIZE);
+ }
+ map = dmap_register (regcache, regno);
+ if (regno == 3)
+ {
+ /* Always maps to data memory */
+ int iospi = (offset / 0x1000) % 4;
+ int iosp = (map >> (4 * (3 - iospi))) % 0x10;
+ last_to = "io-space";
+ *phys = (SIM_D10V_MEMORY_DATA + (iosp * 0x10000) + 0xc000 + offset);
+ }
+ else
{
- if (write_p)
+ int sp = ((map & 0x3000) >> 12);
+ int segno = (map & 0x3ff);
+ switch (sp)
{
- (*d10v_callback->printf_filtered) (d10v_callback, "sim_write %d bytes to 0x%02x:%06x\n", size, segment, addr);
+ case 0: /* 00: Unified memory */
+ *phys = SIM_D10V_MEMORY_UNIFIED + (segno * DMAP_BLOCK_SIZE) + offset;
+ last_to = "unified";
+ break;
+ case 1: /* 01: Instruction Memory */
+ *phys = SIM_D10V_MEMORY_INSN + (segno * DMAP_BLOCK_SIZE) + offset;
+ last_to = "chip-insn";
+ break;
+ case 2: /* 10: Internal data memory */
+ *phys = SIM_D10V_MEMORY_DATA + (segno << 16) + (regno * DMAP_BLOCK_SIZE) + offset;
+ last_to = "chip-data";
+ break;
+ case 3: /* 11: Reserved */
+ return 0;
}
- else
+ }
+ return nr_bytes;
+}
+
+/* Given a virtual address in the IMAP address space, translate it
+ into a physical address. */
+
+unsigned long
+sim_d10v_translate_imap_addr (unsigned long offset,
+ int nr_bytes,
+ unsigned long *phys,
+ void *regcache,
+ unsigned long (*imap_register) (void *regcache,
+ int reg_nr))
+{
+ short map;
+ int regno;
+ int sp;
+ int segno;
+ last_from = "logical-insn";
+ if (offset >= (IMAP_BLOCK_SIZE * SIM_D10V_NR_IMAP_REGS))
+ {
+ /* Logical address outside of IMAP segments, not supported */
+ return 0;
+ }
+ regno = (offset / IMAP_BLOCK_SIZE);
+ offset = (offset % IMAP_BLOCK_SIZE);
+ if (offset + nr_bytes > IMAP_BLOCK_SIZE)
+ {
+ /* Don't cross a BLOCK boundary */
+ nr_bytes = IMAP_BLOCK_SIZE - offset;
+ }
+ map = imap_register (regcache, regno);
+ sp = (map & 0x3000) >> 12;
+ segno = (map & 0x007f);
+ switch (sp)
+ {
+ case 0: /* 00: unified memory */
+ *phys = SIM_D10V_MEMORY_UNIFIED + (segno << 17) + offset;
+ last_to = "unified";
+ break;
+ case 1: /* 01: instruction memory */
+ *phys = SIM_D10V_MEMORY_INSN + (IMAP_BLOCK_SIZE * regno) + offset;
+ last_to = "chip-insn";
+ break;
+ case 2: /*10*/
+ /* Reserved. */
+ return 0;
+ case 3: /* 11: for testing - instruction memory */
+ offset = (offset % 0x800);
+ *phys = SIM_D10V_MEMORY_INSN + offset;
+ if (offset + nr_bytes > 0x800)
+ /* don't cross VM boundary */
+ nr_bytes = 0x800 - offset;
+ last_to = "test-insn";
+ break;
+ }
+ return nr_bytes;
+}
+
+unsigned long
+sim_d10v_translate_addr (unsigned long memaddr,
+ int nr_bytes,
+ unsigned long *targ_addr,
+ void *regcache,
+ unsigned long (*dmap_register) (void *regcache,
+ int reg_nr),
+ unsigned long (*imap_register) (void *regcache,
+ int reg_nr))
+{
+ unsigned long phys;
+ unsigned long seg;
+ unsigned long off;
+
+ last_from = "unknown";
+ last_to = "unknown";
+
+ seg = (memaddr >> 24);
+ off = (memaddr & 0xffffffL);
+
+ /* However, if we've asked to use the previous generation of segment
+ mapping, rearrange the segments as follows. */
+
+ if (old_segment_mapping)
+ {
+ switch (seg)
{
- (*d10v_callback->printf_filtered) (d10v_callback, "sim_read %d bytes from 0x%2x:%6x\n", size, segment, addr);
+ case 0x00: /* DMAP translated memory */
+ seg = 0x10;
+ break;
+ case 0x01: /* IMAP translated memory */
+ seg = 0x11;
+ break;
+ case 0x10: /* On-chip data memory */
+ seg = 0x02;
+ break;
+ case 0x11: /* On-chip insn memory */
+ seg = 0x01;
+ break;
+ case 0x12: /* Unified memory */
+ seg = 0x00;
+ break;
}
}
-#endif
- /* to access data, we use the following mapping
- 0x00xxxxxx: Logical data address segment (DMAP translated memory)
- 0x01xxxxxx: Logical instruction address segment (IMAP translated memory)
- 0x10xxxxxx: Physical data memory segment (On-chip data memory)
- 0x11xxxxxx: Physical instruction memory segment (On-chip insn memory)
- 0x12xxxxxx: Phisical unified memory segment (Unified memory)
- */
-
- switch (segment)
+ switch (seg)
{
- case 0x00: /* DMAP translated memory */
- {
- int byte;
- for (byte = 0; byte < size; byte++)
- {
- uint8 *mem = dmem_addr (addr + byte);
- if (mem == NULL)
- return byte;
- else if (write_p)
- *mem = buffer[byte];
- else
- buffer[byte] = *mem;
- }
- return byte;
- }
+ case 0x00: /* Physical unified memory */
+ last_from = "phys-unified";
+ last_to = "unified";
+ phys = SIM_D10V_MEMORY_UNIFIED + off;
+ if ((off % SEGMENT_SIZE) + nr_bytes > SEGMENT_SIZE)
+ nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE);
+ break;
- case 0x01: /* IMAP translated memory */
- {
- int byte;
- for (byte = 0; byte < size; byte++)
- {
- uint8 *mem = imem_addr (addr + byte);
- if (mem == NULL)
- return byte;
- else if (write_p)
- *mem = buffer[byte];
- else
- buffer[byte] = *mem;
- }
- return byte;
- }
+ case 0x01: /* Physical instruction memory */
+ last_from = "phys-insn";
+ last_to = "chip-insn";
+ phys = SIM_D10V_MEMORY_INSN + off;
+ if ((off % SEGMENT_SIZE) + nr_bytes > SEGMENT_SIZE)
+ nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE);
+ break;
+
+ case 0x02: /* Physical data memory segment */
+ last_from = "phys-data";
+ last_to = "chip-data";
+ phys = SIM_D10V_MEMORY_DATA + off;
+ if ((off % SEGMENT_SIZE) + nr_bytes > SEGMENT_SIZE)
+ nr_bytes = SEGMENT_SIZE - (off % SEGMENT_SIZE);
+ break;
+
+ case 0x10: /* in logical data address segment */
+ nr_bytes = sim_d10v_translate_dmap_addr (off, nr_bytes, &phys, regcache,
+ dmap_register);
+ break;
- case 0x10: /* On-chip data memory */
+ case 0x11: /* in logical instruction address segment */
+ nr_bytes = sim_d10v_translate_imap_addr (off, nr_bytes, &phys, regcache,
+ imap_register);
+ break;
+
+ default:
+ return 0;
+ }
+
+ *targ_addr = phys;
+ return nr_bytes;
+}
+
+/* Return a pointer into the raw buffer designated by phys_addr. It
+ is assumed that the client has already ensured that the access
+ isn't going to cross a segment boundary. */
+
+uint8 *
+map_memory (unsigned phys_addr)
+{
+ uint8 **memory;
+ uint8 *raw;
+ unsigned offset;
+ int segment = ((phys_addr >> 24) & 0xff);
+
+ switch (segment)
+ {
+
+ case 0x00: /* Unified memory */
{
- addr &= ((1 << DMEM_SIZE) - 1);
- if ((addr + size) > (1 << DMEM_SIZE))
- {
- (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: data address 0x%x is outside range 0-0x%x.\n",
- addr + size - 1, (1 << DMEM_SIZE) - 1);
- return (0);
- }
- memory = State.dmem + addr;
+ memory = &State.mem.unif[(phys_addr / SEGMENT_SIZE) % UMEM_SEGMENTS];
+ last_segname = "umem";
break;
}
-
- case 0x11: /* On-chip insn memory */
+
+ case 0x01: /* On-chip insn memory */
{
- addr &= ((1 << IMEM_SIZE) - 1);
- if ((addr + size) > (1 << IMEM_SIZE))
- {
- (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: instruction address 0x%x is outside range 0-0x%x.\n",
- addr + size - 1, (1 << IMEM_SIZE) - 1);
- return (0);
- }
- memory = State.imem + addr;
+ memory = &State.mem.insn[(phys_addr / SEGMENT_SIZE) % IMEM_SEGMENTS];
+ last_segname = "imem";
+ break;
}
-
- case 0x12: /* Unified memory */
+
+ case 0x02: /* On-chip data memory */
{
- int startsegment, startoffset; /* Segment and offset within segment where xfer starts */
- int endsegment, endoffset; /* Segment and offset within segment where xfer ends */
-
- startsegment = addr >> UMEM_SIZE;
- startoffset = addr & ((1 << UMEM_SIZE) - 1);
- endsegment = (addr + size) >> UMEM_SIZE;
- endoffset = (addr + size) & ((1 << UMEM_SIZE) - 1);
-
- /* FIXME: We do not currently implement xfers across segments,
- so detect this case and fail gracefully. */
-
- if ((startsegment != endsegment) && !((endsegment == (startsegment + 1)) && endoffset == 0))
+ if ((phys_addr & 0xff00) == 0xff00)
{
- (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: Unimplemented support for transfers across unified memory segment boundaries\n");
- return (0);
- }
- if (!State.umem[startsegment])
- {
-#ifdef DEBUG
- if ((d10v_debug & DEBUG_MEMSIZE) != 0)
+ phys_addr = (phys_addr & 0xffff);
+ if (phys_addr == DMAP2_SHADDOW)
{
- (*d10v_callback->printf_filtered) (d10v_callback,"Allocating %s bytes unified memory to region %d\n",
- add_commas (buffer, sizeof (buffer), (1UL<<IMEM_SIZE)), startsegment);
+ phys_addr = DMAP2_OFFSET;
+ last_segname = "dmap";
}
-#endif
- State.umem[startsegment] = (uint8 *)calloc(1,1<<UMEM_SIZE);
- }
- if (!State.umem[startsegment])
- {
- (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: Memory allocation of 0x%x bytes failed.\n", 1<<UMEM_SIZE);
- return (0);
+ else
+ last_segname = "reg";
}
- memory = State.umem[startsegment] + startoffset;
+ else
+ last_segname = "dmem";
+ memory = &State.mem.data[(phys_addr / SEGMENT_SIZE) % DMEM_SEGMENTS];
break;
}
-
+
default:
- {
- (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: address 0x%lx is not in valid range\n", (long) addr);
- (*d10v_callback->printf_filtered) (d10v_callback, "0x00xxxxxx: Logical data address segment (DMAP translated memory)\n");
- (*d10v_callback->printf_filtered) (d10v_callback, "0x01xxxxxx: Logical instruction address segment (IMAP translated memory)\n");
- (*d10v_callback->printf_filtered) (d10v_callback, "0x10xxxxxx: Physical data memory segment (On-chip data memory)\n");
- (*d10v_callback->printf_filtered) (d10v_callback, "0x11xxxxxx: Physical instruction memory segment (On-chip insn memory)\n");
- (*d10v_callback->printf_filtered) (d10v_callback, "0x12xxxxxx: Phisical unified memory segment (Unified memory)\n");
- return (0);
- }
+ /* OOPS! */
+ last_segname = "scrap";
+ return State.mem.fault;
}
+
+ if (*memory == NULL)
+ {
+ *memory = calloc (1, SEGMENT_SIZE);
+ if (*memory == NULL)
+ {
+ (*d10v_callback->printf_filtered) (d10v_callback, "Malloc failed.\n");
+ return State.mem.fault;
+ }
+ }
+
+ offset = (phys_addr % SEGMENT_SIZE);
+ raw = *memory + offset;
+ return raw;
+}
+
+/* Transfer data to/from simulated memory. Since a bug in either the
+ simulated program or in gdb or the simulator itself may cause a
+ bogus address to be passed in, we need to do some sanity checking
+ on addresses to make sure they are within bounds. When an address
+ fails the bounds check, treat it as a zero length read/write rather
+ than aborting the entire run. */
+
+static int
+xfer_mem (SIM_ADDR virt,
+ unsigned char *buffer,
+ int size,
+ int write_p)
+{
+ uint8 *memory;
+ unsigned long phys;
+ int phys_size;
+ phys_size = sim_d10v_translate_addr (virt, size, &phys, NULL,
+ dmap_register, imap_register);
+ if (phys_size == 0)
+ return 0;
+
+ memory = map_memory (phys);
+
+#ifdef DEBUG
+ if ((d10v_debug & DEBUG_INSTRUCTION) != 0)
+ {
+ (*d10v_callback->printf_filtered)
+ (d10v_callback,
+ "sim_%s %d bytes: 0x%08lx (%s) -> 0x%08lx (%s) -> 0x%08lx (%s)\n",
+ (write_p ? "write" : "read"),
+ phys_size, virt, last_from,
+ phys, last_to,
+ (long) memory, last_segname);
+ }
+#endif
if (write_p)
{
- memcpy (memory, buffer, size);
+ memcpy (memory, buffer, phys_size);
}
else
{
- memcpy (buffer, memory, size);
+ memcpy (buffer, memory, phys_size);
}
-
- return size;
+
+ return phys_size;
}
sim_open (kind, callback, abfd, argv)
SIM_OPEN_KIND kind;
host_callback *callback;
- struct _bfd *abfd;
+ struct bfd *abfd;
char **argv;
{
struct simops *s;
sim_kind = kind;
d10v_callback = callback;
myname = argv[0];
+ old_segment_mapping = 0;
+ /* NOTE: This argument parsing is only effective when this function
+ is called by GDB. Standalone argument parsing is handled by
+ sim/common/run.c. */
for (p = argv + 1; *p; ++p)
{
+ if (strcmp (*p, "-oldseg") == 0)
+ old_segment_mapping = 1;
#ifdef DEBUG
- if (strcmp (*p, "-t") == 0)
+ else if (strcmp (*p, "-t") == 0)
d10v_debug = DEBUG;
- else
+ else if (strncmp (*p, "-t", 2) == 0)
+ d10v_debug = atoi (*p + 2);
#endif
+ else
(*d10v_callback->printf_filtered) (d10v_callback, "ERROR: unsupported option(s): %s\n",*p);
}
}
/* reset the processor state */
- if (!State.imem)
- sim_size(1);
+ if (!State.mem.data[0])
+ sim_size (1);
sim_create_inferior ((SIM_DESC) 1, NULL, NULL, NULL);
/* Fudge our descriptor. */
(*d10v_callback->printf_filtered) (d10v_callback, "sim_set_profile_size %d\n",n);
}
-
uint8 *
-dmem_addr( addr )
- uint32 addr;
+dmem_addr (uint16 offset)
{
- int seg;
+ unsigned long phys;
+ uint8 *mem;
+ int phys_size;
- addr &= 0xffff;
+ /* Note: DMEM address range is 0..0x10000. Calling code can compute
+ things like ``0xfffe + 0x0e60 == 0x10e5d''. Since offset's type
+ is uint16 this is modulo'ed onto 0x0e5d. */
- if (addr > 0xbfff)
+ phys_size = sim_d10v_translate_dmap_addr (offset, 1, &phys, NULL,
+ dmap_register);
+ if (phys_size == 0)
{
- if ( (addr & 0xfff0) != 0xff00)
- {
- (*d10v_callback->printf_filtered) (d10v_callback, "Data address 0x%lx is in I/O space, pc = 0x%lx.\n",
- (long)addr, (long)decode_pc ());
- State.exception = SIGBUS;
- }
-
- return State.dmem + addr;
+ mem = State.mem.fault;
}
-
- if (addr > 0x7fff)
- {
- if (DMAP & 0x1000)
- {
- /* instruction memory */
- return (DMAP & 0xf) * 0x4000 + State.imem + (addr - 0x8000);
- }
- else
- {
- /* unified memory */
- /* this is ugly because we allocate unified memory in 128K segments and */
- /* dmap addresses 16k segments */
- seg = (DMAP & 0x3ff) >> 3;
- if (State.umem[seg] == NULL)
- {
+ else
+ mem = map_memory (phys);
#ifdef DEBUG
- (*d10v_callback->printf_filtered) (d10v_callback,"Allocating %d bytes unified memory to region %d\n", 1<<UMEM_SIZE, seg);
-#endif
- State.umem[seg] = (uint8 *)calloc(1,1<<UMEM_SIZE);
- if (!State.umem[seg])
- {
- (*d10v_callback->printf_filtered) (d10v_callback,
- "ERROR: alloc failed. unified memory region %d unmapped, pc = 0x%lx\n",
- seg, (long)decode_pc ());
- State.exception = SIGBUS;
- }
- }
- return State.umem[seg] + (DMAP & 7) * 0x4000 + (addr - 0x8000);
- }
+ if ((d10v_debug & DEBUG_MEMORY))
+ {
+ (*d10v_callback->printf_filtered)
+ (d10v_callback,
+ "mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> 0x%08lx (%s)\n",
+ offset, last_from,
+ phys, phys_size, last_to,
+ (long) mem, last_segname);
}
- return State.dmem + addr;
+#endif
+ return mem;
}
-
uint8 *
-imem_addr (uint32 pc)
+imem_addr (uint32 offset)
{
- uint16 imap;
-
- if (pc & 0x20000)
- imap = IMAP1;
- else
- imap = IMAP0;
-
- if (imap & 0x1000)
- return State.imem + pc;
-
- if (State.umem[imap & 0xff] == NULL)
- return 0;
-
- /* Discard upper bit(s) of PC in case IMAP1 selects unified memory. */
- pc &= (1 << UMEM_SIZE) - 1;
-
- return State.umem[imap & 0xff] + pc;
+ unsigned long phys;
+ uint8 *mem;
+ int phys_size = sim_d10v_translate_imap_addr (offset, 1, &phys, NULL,
+ imap_register);
+ if (phys_size == 0)
+ {
+ return State.mem.fault;
+ }
+ mem = map_memory (phys);
+#ifdef DEBUG
+ if ((d10v_debug & DEBUG_MEMORY))
+ {
+ (*d10v_callback->printf_filtered)
+ (d10v_callback,
+ "mem: 0x%08x (%s) -> 0x%08lx %d (%s) -> 0x%08lx (%s)\n",
+ offset, last_from,
+ phys, phys_size, last_to,
+ (long) mem, last_segname);
+ }
+#endif
+ return mem;
}
-
static int stop_simulator = 0;
int
int step, siggnal;
{
uint32 inst;
- int do_iba;
uint8 *iaddr;
/* (*d10v_callback->printf_filtered) (d10v_callback, "sim_resume (%d,%d) PC=0x%x\n",step,siggnal,PC); */
if (step)
sim_stop (sd);
+ switch (siggnal)
+ {
+ case 0:
+ break;
+#ifdef SIGBUS
+ case SIGBUS:
+#endif
+ case SIGSEGV:
+ SET_BPC (PC);
+ SET_BPSW (PSW);
+ SET_HW_PSW ((PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT)));
+ JMP (AE_VECTOR_START);
+ SLOT_FLUSH ();
+ break;
+ case SIGILL:
+ SET_BPC (PC);
+ SET_BPSW (PSW);
+ SET_HW_PSW ((PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT)));
+ JMP (RIE_VECTOR_START);
+ SLOT_FLUSH ();
+ break;
+ default:
+ /* just ignore it */
+ break;
+ }
+
do
{
iaddr = imem_addr ((uint32)PC << 2);
- if (iaddr == NULL)
+ if (iaddr == State.mem.fault)
{
State.exception = SIGBUS;
break;
State.pc_changed = 0;
ins_type_counters[ (int)INS_CYCLES ]++;
- /* check to see if IBA should be triggered after
- this instruction */
- if (State.DB && (PC == IBA))
- do_iba = 1;
- else
- do_iba = 0;
-
switch (inst & 0xC0000000)
{
case 0xC0000000:
break;
}
- /* calculate the next PC */
+ /* If the PC of the current instruction matches RPT_E then
+ schedule a branch to the loop start. If one of those
+ instructions happens to be a branch, than that instruction
+ will be ignored */
if (!State.pc_changed)
{
- if (State.RP && PC == RPT_E)
+ if (PSW_RP && PC == RPT_E)
{
/* Note: The behavour of a branch instruction at RPT_E
- is implementation dependant, this simulator takes the
- branch. Branching to RPT_E is valid, the instruction
- must be executed before the loop is taken. */
- RPT_C -= 1;
- if (RPT_C == 0)
+ is implementation dependant, this simulator takes the
+ branch. Branching to RPT_E is valid, the instruction
+ must be executed before the loop is taken. */
+ if (RPT_C == 1)
{
- State.RP = 0;
- PC++;
+ SET_PSW_RP (0);
+ SET_RPT_C (0);
+ SET_PC (PC + 1);
}
else
- PC = RPT_S;
+ {
+ SET_RPT_C (RPT_C - 1);
+ SET_PC (RPT_S);
+ }
}
else
- PC++;
- }
+ SET_PC (PC + 1);
+ }
- if (do_iba)
+ /* Check for a breakpoint trap on this instruction. This
+ overrides any pending branches or loops */
+ if (PSW_DB && PC == IBA)
+ {
+ SET_BPC (PC);
+ SET_BPSW (PSW);
+ SET_PSW (PSW & PSW_SM_BIT);
+ SET_PC (SDBT_VECTOR_START);
+ }
+
+ /* Writeback all the DATA / PC changes */
+ SLOT_FLUSH ();
+
+#ifdef NEED_UI_LOOP_HOOK
+ if (ui_loop_hook != NULL && ui_loop_hook_counter-- < 0)
{
- BPC = PC;
- move_to_cr (BPSW_CR, PSW);
- move_to_cr (PSW_CR, PSW & PSW_SM_BIT);
- PC = SDBT_VECTOR_START;
+ ui_loop_hook_counter = UI_LOOP_POLL_INTERVAL;
+ ui_loop_hook (0);
}
+#endif /* NEED_UI_LOOP_HOOK */
}
while ( !State.exception && !stop_simulator);
State.exception = SIGTRAP;
}
-int
-sim_trace (sd)
- SIM_DESC sd;
+void
+sim_set_trace (void)
{
#ifdef DEBUG
d10v_debug = DEBUG;
#endif
- sim_resume (sd, 0, 0);
- return 1;
}
void
SIM_RC
sim_create_inferior (sd, abfd, argv, env)
SIM_DESC sd;
- struct _bfd *abfd;
+ struct bfd *abfd;
char **argv;
char **env;
{
bfd_vma start_address;
/* reset all state information */
- memset (&State.regs, 0, (int)&State.imem - (int)&State.regs[0]);
+ memset (&State.regs, 0, (int)&State.mem - (int)&State.regs);
- if (argv)
- {
- /* a hack to set r0/r1 with argc/argv */
- /* some high memory that won't be overwritten by the stack soon */
- bfd_vma addr = State.regs[0] = 0x7C00;
- int p = 20;
- int i = 0;
- while (argv[i])
- {
- int size = strlen (argv[i]) + 1;
- SW (addr + 2*i, addr + p);
- sim_write (sd, addr + 0, argv[i], size);
- p += size;
- i++;
- }
- State.regs[1] = i;
- }
+ /* There was a hack here to copy the values of argc and argv into r0
+ and r1. The values were also saved into some high memory that
+ won't be overwritten by the stack (0x7C00). The reason for doing
+ this was to allow the 'run' program to accept arguments. Without
+ the hack, this is not possible anymore. If the simulator is run
+ from the debugger, arguments cannot be passed in, so this makes
+ no difference. */
/* set PC */
if (abfd != NULL)
if (d10v_debug)
(*d10v_callback->printf_filtered) (d10v_callback, "sim_create_inferior: PC=0x%lx\n", (long) start_address);
#endif
- PC = start_address >> 2;
+ SET_CREG (PC_CR, start_address >> 2);
- /* cpu resets imap0 to 0 and imap1 to 0x7f, but D10V-EVA board */
- /* resets imap0 and imap1 to 0x1000. */
- if (1)
+ /* cpu resets imap0 to 0 and imap1 to 0x7f, but D10V-EVA board
+ initializes imap0 and imap1 to 0x1000 as part of its ROM
+ initialization. */
+ if (old_segment_mapping)
{
- SET_IMAP0 (0x0000);
- SET_IMAP1 (0x007f);
- SET_DMAP (0x0000);
+ /* External memory startup. This is the HARD reset state. */
+ set_imap_register (0, 0x0000);
+ set_imap_register (1, 0x007f);
+ set_dmap_register (0, 0x2000);
+ set_dmap_register (1, 0x2000);
+ set_dmap_register (2, 0x0000); /* Old DMAP */
+ set_dmap_register (3, 0x0000);
}
else
{
- SET_IMAP0(0x1000);
- SET_IMAP1(0x1000);
- SET_DMAP(0);
+ /* Internal memory startup. This is the ROM intialized state. */
+ set_imap_register (0, 0x1000);
+ set_imap_register (1, 0x1000);
+ set_dmap_register (0, 0x2000);
+ set_dmap_register (1, 0x2000);
+ set_dmap_register (2, 0x2000); /* DMAP2 initial internal value is
+ 0x2000 on the new board. */
+ set_dmap_register (3, 0x0000);
}
+ SLOT_FLUSH ();
return SIM_RC_OK;
}
case SIG_D10V_EXIT: /* exit trap */
*reason = sim_exited;
- *sigrc = State.regs[0];
+ *sigrc = GPR (0);
+ break;
+
+ case SIG_D10V_BUS:
+ *reason = sim_stopped;
+#ifdef SIGBUS
+ *sigrc = SIGBUS;
+#else
+ *sigrc = SIGSEGV;
+#endif
break;
default: /* some signal */
stop_simulator = 0;
}
-void
-sim_fetch_register (sd, rn, memory)
+int
+sim_fetch_register (sd, rn, memory, length)
SIM_DESC sd;
int rn;
unsigned char *memory;
+ int length;
{
- if (rn > 34)
- WRITE_64 (memory, State.a[rn-35]);
- else if (rn == 32)
- WRITE_16 (memory, IMAP0);
- else if (rn == 33)
- WRITE_16 (memory, IMAP1);
- else if (rn == 34)
- WRITE_16 (memory, DMAP);
- else if (rn >= 16)
- WRITE_16 (memory, move_from_cr (rn - 16));
- else
- WRITE_16 (memory, State.regs[rn]);
+ int size;
+ switch ((enum sim_d10v_regs) rn)
+ {
+ case SIM_D10V_R0_REGNUM:
+ case SIM_D10V_R1_REGNUM:
+ case SIM_D10V_R2_REGNUM:
+ case SIM_D10V_R3_REGNUM:
+ case SIM_D10V_R4_REGNUM:
+ case SIM_D10V_R5_REGNUM:
+ case SIM_D10V_R6_REGNUM:
+ case SIM_D10V_R7_REGNUM:
+ case SIM_D10V_R8_REGNUM:
+ case SIM_D10V_R9_REGNUM:
+ case SIM_D10V_R10_REGNUM:
+ case SIM_D10V_R11_REGNUM:
+ case SIM_D10V_R12_REGNUM:
+ case SIM_D10V_R13_REGNUM:
+ case SIM_D10V_R14_REGNUM:
+ case SIM_D10V_R15_REGNUM:
+ WRITE_16 (memory, GPR (rn - SIM_D10V_R0_REGNUM));
+ size = 2;
+ break;
+ case SIM_D10V_CR0_REGNUM:
+ case SIM_D10V_CR1_REGNUM:
+ case SIM_D10V_CR2_REGNUM:
+ case SIM_D10V_CR3_REGNUM:
+ case SIM_D10V_CR4_REGNUM:
+ case SIM_D10V_CR5_REGNUM:
+ case SIM_D10V_CR6_REGNUM:
+ case SIM_D10V_CR7_REGNUM:
+ case SIM_D10V_CR8_REGNUM:
+ case SIM_D10V_CR9_REGNUM:
+ case SIM_D10V_CR10_REGNUM:
+ case SIM_D10V_CR11_REGNUM:
+ case SIM_D10V_CR12_REGNUM:
+ case SIM_D10V_CR13_REGNUM:
+ case SIM_D10V_CR14_REGNUM:
+ case SIM_D10V_CR15_REGNUM:
+ WRITE_16 (memory, CREG (rn - SIM_D10V_CR0_REGNUM));
+ size = 2;
+ break;
+ case SIM_D10V_A0_REGNUM:
+ case SIM_D10V_A1_REGNUM:
+ WRITE_64 (memory, ACC (rn - SIM_D10V_A0_REGNUM));
+ size = 8;
+ break;
+ case SIM_D10V_SPI_REGNUM:
+ /* PSW_SM indicates that the current SP is the USER
+ stack-pointer. */
+ WRITE_16 (memory, spi_register ());
+ size = 2;
+ break;
+ case SIM_D10V_SPU_REGNUM:
+ /* PSW_SM indicates that the current SP is the USER
+ stack-pointer. */
+ WRITE_16 (memory, spu_register ());
+ size = 2;
+ break;
+ case SIM_D10V_IMAP0_REGNUM:
+ case SIM_D10V_IMAP1_REGNUM:
+ WRITE_16 (memory, imap_register (NULL, rn - SIM_D10V_IMAP0_REGNUM));
+ size = 2;
+ break;
+ case SIM_D10V_DMAP0_REGNUM:
+ case SIM_D10V_DMAP1_REGNUM:
+ case SIM_D10V_DMAP2_REGNUM:
+ case SIM_D10V_DMAP3_REGNUM:
+ WRITE_16 (memory, dmap_register (NULL, rn - SIM_D10V_DMAP0_REGNUM));
+ size = 2;
+ break;
+ case SIM_D10V_TS2_DMAP_REGNUM:
+ size = 0;
+ break;
+ default:
+ size = 0;
+ break;
+ }
+ return size;
}
-void
-sim_store_register (sd, rn, memory)
+int
+sim_store_register (sd, rn, memory, length)
SIM_DESC sd;
int rn;
unsigned char *memory;
+ int length;
{
- if (rn > 34)
- State.a[rn-35] = READ_64 (memory) & MASK40;
- else if (rn == 34)
- SET_DMAP( READ_16(memory) );
- else if (rn == 33)
- SET_IMAP1( READ_16(memory) );
- else if (rn == 32)
- SET_IMAP0( READ_16(memory) );
- else if (rn >= 16)
- move_to_cr (rn - 16, READ_16 (memory));
- else
- State.regs[rn]= READ_16 (memory);
+ int size;
+ switch ((enum sim_d10v_regs) rn)
+ {
+ case SIM_D10V_R0_REGNUM:
+ case SIM_D10V_R1_REGNUM:
+ case SIM_D10V_R2_REGNUM:
+ case SIM_D10V_R3_REGNUM:
+ case SIM_D10V_R4_REGNUM:
+ case SIM_D10V_R5_REGNUM:
+ case SIM_D10V_R6_REGNUM:
+ case SIM_D10V_R7_REGNUM:
+ case SIM_D10V_R8_REGNUM:
+ case SIM_D10V_R9_REGNUM:
+ case SIM_D10V_R10_REGNUM:
+ case SIM_D10V_R11_REGNUM:
+ case SIM_D10V_R12_REGNUM:
+ case SIM_D10V_R13_REGNUM:
+ case SIM_D10V_R14_REGNUM:
+ case SIM_D10V_R15_REGNUM:
+ SET_GPR (rn - SIM_D10V_R0_REGNUM, READ_16 (memory));
+ size = 2;
+ break;
+ case SIM_D10V_CR0_REGNUM:
+ case SIM_D10V_CR1_REGNUM:
+ case SIM_D10V_CR2_REGNUM:
+ case SIM_D10V_CR3_REGNUM:
+ case SIM_D10V_CR4_REGNUM:
+ case SIM_D10V_CR5_REGNUM:
+ case SIM_D10V_CR6_REGNUM:
+ case SIM_D10V_CR7_REGNUM:
+ case SIM_D10V_CR8_REGNUM:
+ case SIM_D10V_CR9_REGNUM:
+ case SIM_D10V_CR10_REGNUM:
+ case SIM_D10V_CR11_REGNUM:
+ case SIM_D10V_CR12_REGNUM:
+ case SIM_D10V_CR13_REGNUM:
+ case SIM_D10V_CR14_REGNUM:
+ case SIM_D10V_CR15_REGNUM:
+ SET_CREG (rn - SIM_D10V_CR0_REGNUM, READ_16 (memory));
+ size = 2;
+ break;
+ case SIM_D10V_A0_REGNUM:
+ case SIM_D10V_A1_REGNUM:
+ SET_ACC (rn - SIM_D10V_A0_REGNUM, READ_64 (memory) & MASK40);
+ size = 8;
+ break;
+ case SIM_D10V_SPI_REGNUM:
+ /* PSW_SM indicates that the current SP is the USER
+ stack-pointer. */
+ set_spi_register (READ_16 (memory));
+ size = 2;
+ break;
+ case SIM_D10V_SPU_REGNUM:
+ set_spu_register (READ_16 (memory));
+ size = 2;
+ break;
+ case SIM_D10V_IMAP0_REGNUM:
+ case SIM_D10V_IMAP1_REGNUM:
+ set_imap_register (rn - SIM_D10V_IMAP0_REGNUM, READ_16(memory));
+ size = 2;
+ break;
+ case SIM_D10V_DMAP0_REGNUM:
+ case SIM_D10V_DMAP1_REGNUM:
+ case SIM_D10V_DMAP2_REGNUM:
+ case SIM_D10V_DMAP3_REGNUM:
+ set_dmap_register (rn - SIM_D10V_DMAP0_REGNUM, READ_16(memory));
+ size = 2;
+ break;
+ case SIM_D10V_TS2_DMAP_REGNUM:
+ size = 0;
+ break;
+ default:
+ size = 0;
+ break;
+ }
+ SLOT_FLUSH ();
+ return size;
}
projects / deliverable / binutils-gdb.git / blobdiff