#ifdef HAVE_UNISTD_H
#include <unistd.h>
#endif
+#ifdef HAVE_STRING_H
+#include <string.h>
+#endif
-#include "d10v_sim.h"
+#include "sim-main.h"
#include "simops.h"
#include "targ-vals.h"
-extern char *strrchr ();
+#define EXCEPTION(sig) sim_engine_halt (sd, cpu, NULL, PC, sim_stopped, sig)
enum op_types {
OP_VOID,
OP_CONSTANT4,
OP_MEMREF,
OP_MEMREF2,
+ OP_MEMREF3,
OP_POSTDEC,
OP_POSTINC,
OP_PREDEC,
PSW_MASK = (PSW_SM_BIT
| PSW_EA_BIT
| PSW_DB_BIT
- | PSW_DM_BIT
| PSW_IE_BIT
| PSW_RP_BIT
| PSW_MD_BIT
| PSW_F0_BIT
| PSW_F1_BIT
| PSW_C_BIT),
+ /* The following bits in the PSW _can't_ be set by instructions such
+ as mvtc. */
+ PSW_HW_MASK = (PSW_MASK | PSW_DM_BIT)
};
reg_t
-move_to_cr (int cr, reg_t mask, reg_t val)
+move_to_cr (SIM_DESC sd, SIM_CPU *cpu, int cr, reg_t mask, reg_t val, int psw_hw_p)
{
/* A MASK bit is set when the corresponding bit in the CR should
be left alone */
switch (cr)
{
case PSW_CR:
- val &= PSW_MASK;
+ if (psw_hw_p)
+ val &= PSW_HW_MASK;
+ else
+ val &= PSW_MASK;
if ((mask & PSW_SM_BIT) == 0)
{
- int new_sm = (val & PSW_SM_BIT) != 0;
- SET_HELD_SP (PSW_SM, GPR (SP_IDX)); /* save old SP */
- if (PSW_SM != new_sm)
- SET_GPR (SP_IDX, HELD_SP (new_sm)); /* restore new SP */
+ int new_psw_sm = (val & PSW_SM_BIT) != 0;
+ /* save old SP */
+ SET_HELD_SP (PSW_SM, GPR (SP_IDX));
+ if (PSW_SM != new_psw_sm)
+ /* restore new SP */
+ SET_GPR (SP_IDX, HELD_SP (new_psw_sm));
}
if ((mask & (PSW_ST_BIT | PSW_FX_BIT)) == 0)
{
if (val & PSW_ST_BIT && !(val & PSW_FX_BIT))
{
- (*d10v_callback->printf_filtered)
- (d10v_callback,
+ sim_io_printf
+ (sd,
"ERROR at PC 0x%x: ST can only be set when FX is set.\n",
PC<<2);
- State.exception = SIGILL;
+ EXCEPTION (SIM_SIGILL);
}
}
/* keep an up-to-date psw around for tracing */
break;
case BPSW_CR:
case DPSW_CR:
- val &= PSW_MASK;
+ /* Just like PSW, mask things like DM out. */
+ if (psw_hw_p)
+ val &= PSW_HW_MASK;
+ else
+ val &= PSW_MASK;
break;
case MOD_S_CR:
case MOD_E_CR:
}
#ifdef DEBUG
-static void trace_input_func PARAMS ((char *name,
- enum op_types in1,
- enum op_types in2,
- enum op_types in3));
+static void trace_input_func (SIM_DESC sd,
+ const char *name,
+ enum op_types in1,
+ enum op_types in2,
+ enum op_types in3);
-#define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0)
+#define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (sd, name, in1, in2, in3); } while (0)
#ifndef SIZE_INSTRUCTION
#define SIZE_INSTRUCTION 8
#endif
static void
-trace_input_func (name, in1, in2, in3)
- char *name;
- enum op_types in1;
- enum op_types in2;
- enum op_types in3;
+trace_input_func (SIM_DESC sd, const char *name, enum op_types in1, enum op_types in2, enum op_types in3)
{
char *comma;
enum op_types in[3];
}
if ((d10v_debug & DEBUG_LINE_NUMBER) == 0)
- (*d10v_callback->printf_filtered) (d10v_callback,
+ sim_io_printf (sd,
"0x%.*x %s: %-*s ",
SIZE_PC, (unsigned)PC,
type,
else
{
buf[0] = '\0';
- byte_pc = decode_pc ();
- if (text && byte_pc >= text_start && byte_pc < text_end)
+ byte_pc = PC;
+ if (STATE_TEXT_SECTION (sd)
+ && byte_pc >= STATE_TEXT_START (sd)
+ && byte_pc < STATE_TEXT_END (sd))
{
filename = (const char *)0;
functionname = (const char *)0;
linenumber = 0;
- if (bfd_find_nearest_line (prog_bfd, text, (struct symbol_cache_entry **)0, byte_pc - text_start,
+ if (bfd_find_nearest_line (STATE_PROG_BFD (sd),
+ STATE_TEXT_SECTION (sd),
+ (struct bfd_symbol **)0,
+ byte_pc - STATE_TEXT_START (sd),
&filename, &functionname, &linenumber))
{
p = buf;
}
}
- (*d10v_callback->printf_filtered) (d10v_callback,
+ sim_io_printf (sd,
"0x%.*x %s: %-*.*s %-*s ",
SIZE_PC, (unsigned)PC,
type,
comma = ",";
break;
+ case OP_MEMREF3:
+ sprintf (p, "%s@%d", comma, OP[i]);
+ p += strlen (p);
+ comma = ",";
+ break;
+
case OP_POSTINC:
sprintf (p, "%s@r%d+", comma, OP[i]);
p += strlen (p);
{
*p++ = '\n';
*p = '\0';
- (*d10v_callback->printf_filtered) (d10v_callback, "%s", buf);
+ sim_io_printf (sd, "%s", buf);
}
else
{
*p = '\0';
- (*d10v_callback->printf_filtered) (d10v_callback, "%-*s", SIZE_OPERANDS, buf);
+ sim_io_printf (sd, "%-*s", SIZE_OPERANDS, buf);
p = buf;
for (i = 0; i < 3; i++)
switch (in[i])
{
case OP_VOID:
- (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "");
+ sim_io_printf (sd, "%*s", SIZE_VALUES, "");
break;
case OP_REG_OUTPUT:
case OP_CR_OUTPUT:
case OP_ACCUM_OUTPUT:
case OP_FLAG_OUTPUT:
- (*d10v_callback->printf_filtered) (d10v_callback, "%*s", SIZE_VALUES, "---");
+ sim_io_printf (sd, "%*s", SIZE_VALUES, "---");
break;
case OP_REG:
case OP_POSTDEC:
case OP_POSTINC:
case OP_PREDEC:
- (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
+ sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
(uint16) GPR (OP[i]));
break;
+ case OP_MEMREF3:
+ sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "", (uint16) OP[i]);
+ break;
+
case OP_DREG:
tmp = (long)((((uint32) GPR (OP[i])) << 16) | ((uint32) GPR (OP[i] + 1)));
- (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
+ sim_io_printf (sd, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp);
break;
case OP_CR:
case OP_CR_REVERSE:
- (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
+ sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
(uint16) CREG (OP[i]));
break;
case OP_ACCUM:
case OP_ACCUM_REVERSE:
- (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "",
+ sim_io_printf (sd, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "",
((int)(ACC (OP[i]) >> 32) & 0xff),
((unsigned long) ACC (OP[i])) & 0xffffffff);
break;
case OP_CONSTANT16:
- (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
+ sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
(uint16)OP[i]);
break;
case OP_CONSTANT4:
- (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
+ sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
(uint16)SEXT4(OP[i]));
break;
case OP_CONSTANT8:
- (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
+ sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
(uint16)SEXT8(OP[i]));
break;
case OP_CONSTANT3:
- (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
+ sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
(uint16)SEXT3(OP[i]));
break;
case OP_FLAG:
if (OP[i] == 0)
- (*d10v_callback->printf_filtered) (d10v_callback, "%*sF0 = %d", SIZE_VALUES-6, "",
+ sim_io_printf (sd, "%*sF0 = %d", SIZE_VALUES-6, "",
PSW_F0 != 0);
else if (OP[i] == 1)
- (*d10v_callback->printf_filtered) (d10v_callback, "%*sF1 = %d", SIZE_VALUES-6, "",
+ sim_io_printf (sd, "%*sF1 = %d", SIZE_VALUES-6, "",
PSW_F1 != 0);
else
- (*d10v_callback->printf_filtered) (d10v_callback, "%*sC = %d", SIZE_VALUES-5, "",
+ sim_io_printf (sd, "%*sC = %d", SIZE_VALUES-5, "",
PSW_C != 0);
break;
case OP_MEMREF2:
- (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
+ sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
(uint16)OP[i]);
- (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
+ sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
(uint16)GPR (OP[i + 1]));
i++;
break;
case OP_R0:
- (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
+ sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
(uint16) GPR (0));
break;
case OP_R1:
- (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
+ sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
(uint16) GPR (1));
break;
case OP_R2:
- (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
+ sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "",
(uint16) GPR (2));
break;
}
}
- (*d10v_callback->flush_stdout) (d10v_callback);
+ sim_io_flush_stdout (sd);
}
static void
-do_trace_output_flush (void)
+do_trace_output_flush (SIM_DESC sd)
{
- (*d10v_callback->flush_stdout) (d10v_callback);
+ sim_io_flush_stdout (sd);
}
static void
-do_trace_output_finish (void)
+do_trace_output_finish (SIM_DESC sd)
{
- (*d10v_callback->printf_filtered) (d10v_callback,
+ sim_io_printf (sd,
" F0=%d F1=%d C=%d\n",
(State.trace.psw & PSW_F0_BIT) != 0,
(State.trace.psw & PSW_F1_BIT) != 0,
(State.trace.psw & PSW_C_BIT) != 0);
- (*d10v_callback->flush_stdout) (d10v_callback);
+ sim_io_flush_stdout (sd);
}
static void
-trace_output_40 (uint64 val)
+trace_output_40 (SIM_DESC sd, uint64 val)
{
if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
{
- (*d10v_callback->printf_filtered) (d10v_callback,
+ sim_io_printf (sd,
" :: %*s0x%.2x%.8lx",
SIZE_VALUES - 12,
"",
((int)(val >> 32) & 0xff),
((unsigned long) val) & 0xffffffff);
- do_trace_output_finish ();
+ do_trace_output_finish (sd);
}
}
static void
-trace_output_32 (uint32 val)
+trace_output_32 (SIM_DESC sd, uint32 val)
{
if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
{
- (*d10v_callback->printf_filtered) (d10v_callback,
+ sim_io_printf (sd,
" :: %*s0x%.8x",
SIZE_VALUES - 10,
"",
(int) val);
- do_trace_output_finish ();
+ do_trace_output_finish (sd);
}
}
static void
-trace_output_16 (uint16 val)
+trace_output_16 (SIM_DESC sd, uint16 val)
{
if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
{
- (*d10v_callback->printf_filtered) (d10v_callback,
+ sim_io_printf (sd,
" :: %*s0x%.4x",
SIZE_VALUES - 6,
"",
(int) val);
- do_trace_output_finish ();
+ do_trace_output_finish (sd);
}
}
static void
-trace_output_void ()
+trace_output_void (SIM_DESC sd)
{
if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
{
- (*d10v_callback->printf_filtered) (d10v_callback, "\n");
- do_trace_output_flush ();
+ sim_io_printf (sd, "\n");
+ do_trace_output_flush (sd);
}
}
static void
-trace_output_flag ()
+trace_output_flag (SIM_DESC sd)
{
if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
{
- (*d10v_callback->printf_filtered) (d10v_callback,
+ sim_io_printf (sd,
" :: %*s",
SIZE_VALUES,
"");
- do_trace_output_finish ();
+ do_trace_output_finish (sd);
}
}
/* abs */
void
-OP_4607 ()
+OP_4607 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("abs", OP_REG, OP_VOID, OP_VOID);
else
SET_PSW_F0 (0);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* abs */
void
-OP_5607 ()
+OP_5607 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID);
SET_PSW_F0 (0);
}
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* add */
void
-OP_200 ()
+OP_200 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 a = GPR (OP[0]);
uint16 b = GPR (OP[1]);
trace_input ("add", OP_REG, OP_REG, OP_VOID);
SET_PSW_C (a > tmp);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* add */
void
-OP_1201 ()
+OP_1201 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
tmp = SEXT40(ACC (OP[0])) + (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1));
else
tmp = (tmp & MASK40);
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* add */
void
-OP_1203 ()
+OP_1203 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
tmp = SEXT40(ACC (OP[0])) + SEXT40(ACC (OP[1]));
else
tmp = (tmp & MASK40);
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* add2w */
void
-OP_1200 ()
+OP_1200 (SIM_DESC sd, SIM_CPU *cpu)
{
uint32 tmp;
uint32 a = (GPR (OP[0])) << 16 | GPR (OP[0] + 1);
SET_PSW_C (tmp < a);
SET_GPR (OP[0] + 0, (tmp >> 16));
SET_GPR (OP[0] + 1, (tmp & 0xFFFF));
- trace_output_32 (tmp);
+ trace_output_32 (sd, tmp);
}
/* add3 */
void
-OP_1000000 ()
+OP_1000000 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 a = GPR (OP[1]);
uint16 b = OP[2];
trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
SET_PSW_C (tmp < a);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* addac3 */
void
-OP_17000200 ()
+OP_17000200 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
tmp = SEXT40(ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1));
trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
SET_GPR (OP[0] + 0, ((tmp >> 16) & 0xffff));
SET_GPR (OP[0] + 1, (tmp & 0xffff));
- trace_output_32 (tmp);
+ trace_output_32 (sd, tmp);
}
/* addac3 */
void
-OP_17000202 ()
+OP_17000202 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
tmp = SEXT40(ACC (OP[1])) + SEXT40(ACC (OP[2]));
trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
SET_GPR (OP[0] + 1, tmp & 0xffff);
- trace_output_32 (tmp);
+ trace_output_32 (sd, tmp);
}
/* addac3s */
void
-OP_17001200 ()
+OP_17001200 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
SET_PSW_F1 (PSW_F0);
}
SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
SET_GPR (OP[0] + 1, (tmp & 0xffff));
- trace_output_32 (tmp);
+ trace_output_32 (sd, tmp);
}
/* addac3s */
void
-OP_17001202 ()
+OP_17001202 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
SET_PSW_F1 (PSW_F0);
}
SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff);
SET_GPR (OP[0] + 1, (tmp & 0xffff));
- trace_output_32 (tmp);
+ trace_output_32 (sd, tmp);
}
/* addi */
void
-OP_201 ()
+OP_201 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 a = GPR (OP[0]);
uint16 b;
trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID);
SET_PSW_C (tmp < a);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* and */
void
-OP_C00 ()
+OP_C00 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 tmp = GPR (OP[0]) & GPR (OP[1]);
trace_input ("and", OP_REG, OP_REG, OP_VOID);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* and3 */
void
-OP_6000000 ()
+OP_6000000 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 tmp = GPR (OP[1]) & OP[2];
trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* bclri */
void
-OP_C01 ()
+OP_C01 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID);
tmp = (GPR (OP[0]) &~(0x8000 >> OP[1]));
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* bl.s */
void
-OP_4900 ()
+OP_4900 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("bl.s", OP_CONSTANT8, OP_R0, OP_R1);
SET_GPR (13, PC + 1);
JMP( PC + SEXT8 (OP[0]));
- trace_output_void ();
+ trace_output_void (sd);
}
/* bl.l */
void
-OP_24800000 ()
+OP_24800000 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("bl.l", OP_CONSTANT16, OP_R0, OP_R1);
SET_GPR (13, (PC + 1));
JMP (PC + OP[0]);
- trace_output_void ();
+ trace_output_void (sd);
}
/* bnoti */
void
-OP_A01 ()
+OP_A01 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID);
tmp = (GPR (OP[0]) ^ (0x8000 >> OP[1]));
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* bra.s */
void
-OP_4800 ()
+OP_4800 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("bra.s", OP_CONSTANT8, OP_VOID, OP_VOID);
JMP (PC + SEXT8 (OP[0]));
- trace_output_void ();
+ trace_output_void (sd);
}
/* bra.l */
void
-OP_24000000 ()
+OP_24000000 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID);
JMP (PC + OP[0]);
- trace_output_void ();
+ trace_output_void (sd);
}
/* brf0f.s */
void
-OP_4A00 ()
+OP_4A00 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("brf0f.s", OP_CONSTANT8, OP_VOID, OP_VOID);
if (!PSW_F0)
JMP (PC + SEXT8 (OP[0]));
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* brf0f.l */
void
-OP_25000000 ()
+OP_25000000 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID);
if (!PSW_F0)
JMP (PC + OP[0]);
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* brf0t.s */
void
-OP_4B00 ()
+OP_4B00 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("brf0t.s", OP_CONSTANT8, OP_VOID, OP_VOID);
if (PSW_F0)
JMP (PC + SEXT8 (OP[0]));
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* brf0t.l */
void
-OP_25800000 ()
+OP_25800000 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID);
if (PSW_F0)
JMP (PC + OP[0]);
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* bseti */
void
-OP_801 ()
+OP_801 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID);
tmp = (GPR (OP[0]) | (0x8000 >> OP[1]));
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* btsti */
void
-OP_E01 ()
+OP_E01 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID);
SET_PSW_F1 (PSW_F0);
SET_PSW_F0 ((GPR (OP[0]) & (0x8000 >> OP[1])) ? 1 : 0);
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* clrac */
void
-OP_5601 ()
+OP_5601 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID);
SET_ACC (OP[0], 0);
- trace_output_40 (0);
+ trace_output_40 (sd, 0);
}
/* cmp */
void
-OP_600 ()
+OP_600 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("cmp", OP_REG, OP_REG, OP_VOID);
SET_PSW_F1 (PSW_F0);
SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)(GPR (OP[1]))) ? 1 : 0);
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* cmp */
void
-OP_1603 ()
+OP_1603 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID);
SET_PSW_F1 (PSW_F0);
SET_PSW_F0 ((SEXT40(ACC (OP[0])) < SEXT40(ACC (OP[1]))) ? 1 : 0);
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* cmpeq */
void
-OP_400 ()
+OP_400 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID);
SET_PSW_F1 (PSW_F0);
SET_PSW_F0 ((GPR (OP[0]) == GPR (OP[1])) ? 1 : 0);
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* cmpeq */
void
-OP_1403 ()
+OP_1403 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID);
SET_PSW_F1 (PSW_F0);
SET_PSW_F0 (((ACC (OP[0]) & MASK40) == (ACC (OP[1]) & MASK40)) ? 1 : 0);
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* cmpeqi.s */
void
-OP_401 ()
+OP_401 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT4, OP_VOID);
SET_PSW_F1 (PSW_F0);
SET_PSW_F0 ((GPR (OP[0]) == (reg_t) SEXT4 (OP[1])) ? 1 : 0);
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* cmpeqi.l */
void
-OP_2000000 ()
+OP_2000000 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID);
SET_PSW_F1 (PSW_F0);
SET_PSW_F0 ((GPR (OP[0]) == (reg_t)OP[1]) ? 1 : 0);
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* cmpi.s */
void
-OP_601 ()
+OP_601 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID);
SET_PSW_F1 (PSW_F0);
SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)SEXT4(OP[1])) ? 1 : 0);
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* cmpi.l */
void
-OP_3000000 ()
+OP_3000000 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID);
SET_PSW_F1 (PSW_F0);
SET_PSW_F0 (((int16)(GPR (OP[0])) < (int16)(OP[1])) ? 1 : 0);
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* cmpu */
void
-OP_4600 ()
+OP_4600 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("cmpu", OP_REG, OP_REG, OP_VOID);
SET_PSW_F1 (PSW_F0);
SET_PSW_F0 ((GPR (OP[0]) < GPR (OP[1])) ? 1 : 0);
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* cmpui */
void
-OP_23000000 ()
+OP_23000000 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID);
SET_PSW_F1 (PSW_F0);
SET_PSW_F0 ((GPR (OP[0]) < (reg_t)OP[1]) ? 1 : 0);
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* cpfg */
void
-OP_4E09 ()
+OP_4E09 (SIM_DESC sd, SIM_CPU *cpu)
{
uint8 val;
else
SET_PSW_F1 (val);
- trace_output_flag ();
+ trace_output_flag (sd);
+}
+
+/* cpfg */
+void
+OP_4E0F (SIM_DESC sd, SIM_CPU *cpu)
+{
+ uint8 val;
+
+ trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID);
+
+ if (OP[1] == 0)
+ val = PSW_F0;
+ else if (OP[1] == 1)
+ val = PSW_F1;
+ else
+ val = PSW_C;
+ if (OP[0] == 0)
+ SET_PSW_F0 (val);
+ else
+ SET_PSW_F1 (val);
+
+ trace_output_flag (sd);
}
/* dbt */
void
-OP_5F20 ()
+OP_5F20 (SIM_DESC sd, SIM_CPU *cpu)
{
- /* d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); */
+ /* sim_io_printf (sd, "***** DBT ***** PC=%x\n",PC); */
/* GDB uses the instruction pair ``dbt || nop'' as a break-point.
The conditional below is for either of the instruction pairs
trace_input ("dbt", OP_VOID, OP_VOID, OP_VOID);
SET_DPC (PC + 1);
SET_DPSW (PSW);
- SET_PSW (PSW_DM_BIT | (PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT)));
+ SET_HW_PSW (PSW_DM_BIT | (PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT)));
JMP (DBT_VECTOR_START);
- trace_output_void ();
+ trace_output_void (sd);
}
else
- {
- State.exception = SIGTRAP;
- }
+ sim_engine_halt (sd, cpu, NULL, PC, sim_stopped, SIM_SIGTRAP);
}
/* divs */
void
-OP_14002800 ()
+OP_14002800 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 foo, tmp, tmpf;
uint16 hi;
lo = ((GPR (OP[0] + 1) << 1) | tmpf);
SET_GPR (OP[0] + 0, hi);
SET_GPR (OP[0] + 1, lo);
- trace_output_32 (((uint32) hi << 16) | lo);
+ trace_output_32 (sd, ((uint32) hi << 16) | lo);
}
/* exef0f */
void
-OP_4E04 ()
+OP_4E04 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID);
State.exe = (PSW_F0 == 0);
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* exef0t */
void
-OP_4E24 ()
+OP_4E24 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID);
State.exe = (PSW_F0 != 0);
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* exef1f */
void
-OP_4E40 ()
+OP_4E40 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID);
State.exe = (PSW_F1 == 0);
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* exef1t */
void
-OP_4E42 ()
+OP_4E42 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID);
State.exe = (PSW_F1 != 0);
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* exefaf */
void
-OP_4E00 ()
+OP_4E00 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID);
State.exe = (PSW_F0 == 0) & (PSW_F1 == 0);
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* exefat */
void
-OP_4E02 ()
+OP_4E02 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID);
State.exe = (PSW_F0 == 0) & (PSW_F1 != 0);
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* exetaf */
void
-OP_4E20 ()
+OP_4E20 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID);
State.exe = (PSW_F0 != 0) & (PSW_F1 == 0);
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* exetat */
void
-OP_4E22 ()
+OP_4E22 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID);
State.exe = (PSW_F0 != 0) & (PSW_F1 != 0);
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* exp */
void
-OP_15002A00 ()
+OP_15002A00 (SIM_DESC sd, SIM_CPU *cpu)
{
uint32 tmp, foo;
int i;
if (tmp & foo)
{
SET_GPR (OP[0], (i - 1));
- trace_output_16 (i - 1);
+ trace_output_16 (sd, i - 1);
return;
}
foo >>= 1;
}
SET_GPR (OP[0], 16);
- trace_output_16 (16);
+ trace_output_16 (sd, 16);
}
/* exp */
void
-OP_15002A02 ()
+OP_15002A02 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp, foo;
int i;
if (tmp & foo)
{
SET_GPR (OP[0], i - 9);
- trace_output_16 (i - 9);
+ trace_output_16 (sd, i - 9);
return;
}
foo >>= 1;
}
SET_GPR (OP[0], 16);
- trace_output_16 (16);
+ trace_output_16 (sd, 16);
}
/* jl */
void
-OP_4D00 ()
+OP_4D00 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("jl", OP_REG, OP_R0, OP_R1);
SET_GPR (13, PC + 1);
JMP (GPR (OP[0]));
- trace_output_void ();
+ trace_output_void (sd);
}
/* jmp */
void
-OP_4C00 ()
+OP_4C00 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("jmp", OP_REG,
(OP[0] == 13) ? OP_R0 : OP_VOID,
(OP[0] == 13) ? OP_R1 : OP_VOID);
JMP (GPR (OP[0]));
- trace_output_void ();
+ trace_output_void (sd);
}
/* ld */
void
-OP_30000000 ()
+OP_30000000 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 tmp;
+ uint16 addr = OP[1] + GPR (OP[2]);
trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
- tmp = RW (OP[1] + GPR (OP[2]));
+ if ((addr & 1))
+ {
+ trace_output_void (sd);
+ EXCEPTION (SIM_SIGBUS);
+ }
+ tmp = RW (addr);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* ld */
void
-OP_6401 ()
+OP_6401 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 tmp;
+ uint16 addr = GPR (OP[1]);
trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
- tmp = RW (GPR (OP[1]));
+ if ((addr & 1))
+ {
+ trace_output_void (sd);
+ EXCEPTION (SIM_SIGBUS);
+ }
+ tmp = RW (addr);
SET_GPR (OP[0], tmp);
if (OP[0] != OP[1])
INC_ADDR (OP[1], -2);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* ld */
void
-OP_6001 ()
+OP_6001 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 tmp;
+ uint16 addr = GPR (OP[1]);
trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
- tmp = RW (GPR (OP[1]));
+ if ((addr & 1))
+ {
+ trace_output_void (sd);
+ EXCEPTION (SIM_SIGBUS);
+ }
+ tmp = RW (addr);
SET_GPR (OP[0], tmp);
if (OP[0] != OP[1])
INC_ADDR (OP[1], 2);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* ld */
void
-OP_6000 ()
+OP_6000 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 tmp;
+ uint16 addr = GPR (OP[1]);
trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
- tmp = RW (GPR (OP[1]));
+ if ((addr & 1))
+ {
+ trace_output_void (sd);
+ EXCEPTION (SIM_SIGBUS);
+ }
+ tmp = RW (addr);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
+}
+
+/* ld */
+void
+OP_32010000 (SIM_DESC sd, SIM_CPU *cpu)
+{
+ uint16 tmp;
+ uint16 addr = OP[1];
+ trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF3, OP_VOID);
+ if ((addr & 1))
+ {
+ trace_output_void (sd);
+ EXCEPTION (SIM_SIGBUS);
+ }
+ tmp = RW (addr);
+ SET_GPR (OP[0], tmp);
+ trace_output_16 (sd, tmp);
}
/* ld2w */
void
-OP_31000000 ()
+OP_31000000 (SIM_DESC sd, SIM_CPU *cpu)
{
int32 tmp;
- uint16 addr = GPR (OP[2]);
+ uint16 addr = OP[1] + GPR (OP[2]);
trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
- tmp = RLW (OP[1] + addr);
+ if ((addr & 1))
+ {
+ trace_output_void (sd);
+ EXCEPTION (SIM_SIGBUS);
+ }
+ tmp = RLW (addr);
SET_GPR32 (OP[0], tmp);
- trace_output_32 (tmp);
+ trace_output_32 (sd, tmp);
}
/* ld2w */
void
-OP_6601 ()
+OP_6601 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 addr = GPR (OP[1]);
int32 tmp;
trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID);
+ if ((addr & 1))
+ {
+ trace_output_void (sd);
+ EXCEPTION (SIM_SIGBUS);
+ }
tmp = RLW (addr);
SET_GPR32 (OP[0], tmp);
- if (OP[0] != OP[1])
+ if (OP[0] != OP[1] && ((OP[0] + 1) != OP[1]))
INC_ADDR (OP[1], -4);
- trace_output_32 (tmp);
+ trace_output_32 (sd, tmp);
}
/* ld2w */
void
-OP_6201 ()
+OP_6201 (SIM_DESC sd, SIM_CPU *cpu)
{
int32 tmp;
uint16 addr = GPR (OP[1]);
trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID);
+ if ((addr & 1))
+ {
+ trace_output_void (sd);
+ EXCEPTION (SIM_SIGBUS);
+ }
tmp = RLW (addr);
SET_GPR32 (OP[0], tmp);
- if (OP[0] != OP[1])
+ if (OP[0] != OP[1] && ((OP[0] + 1) != OP[1]))
INC_ADDR (OP[1], 4);
- trace_output_32 (tmp);
+ trace_output_32 (sd, tmp);
}
/* ld2w */
void
-OP_6200 ()
+OP_6200 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 addr = GPR (OP[1]);
int32 tmp;
trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
- tmp = RLW (addr + 0);
+ if ((addr & 1))
+ {
+ trace_output_void (sd);
+ EXCEPTION (SIM_SIGBUS);
+ }
+ tmp = RLW (addr);
+ SET_GPR32 (OP[0], tmp);
+ trace_output_32 (sd, tmp);
+}
+
+/* ld2w */
+void
+OP_33010000 (SIM_DESC sd, SIM_CPU *cpu)
+{
+ int32 tmp;
+ uint16 addr = OP[1];
+ trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF3, OP_VOID);
+ if ((addr & 1))
+ {
+ trace_output_void (sd);
+ EXCEPTION (SIM_SIGBUS);
+ }
+ tmp = RLW (addr);
SET_GPR32 (OP[0], tmp);
- trace_output_32 (tmp);
+ trace_output_32 (sd, tmp);
}
/* ldb */
void
-OP_38000000 ()
+OP_38000000 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
tmp = SEXT8 (RB (OP[1] + GPR (OP[2])));
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* ldb */
void
-OP_7000 ()
+OP_7000 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
tmp = SEXT8 (RB (GPR (OP[1])));
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* ldi.s */
void
-OP_4001 ()
+OP_4001 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID);
tmp = SEXT4 (OP[1]);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* ldi.l */
void
-OP_20000000 ()
+OP_20000000 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("ldi.l", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID);
tmp = OP[1];
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* ldub */
void
-OP_39000000 ()
+OP_39000000 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
tmp = RB (OP[1] + GPR (OP[2]));
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* ldub */
void
-OP_7200 ()
+OP_7200 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
tmp = RB (GPR (OP[1]));
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* mac */
void
-OP_2A00 ()
+OP_2A00 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
else
tmp = (tmp & MASK40);
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* macsu */
void
-OP_1A00 ()
+OP_1A00 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
tmp = SEXT40 ((tmp << 1) & MASK40);
tmp = ((SEXT40 (ACC (OP[0])) + tmp) & MASK40);
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* macu */
void
-OP_3A00 ()
+OP_3A00 (SIM_DESC sd, SIM_CPU *cpu)
{
uint64 tmp;
uint32 src1;
tmp = (tmp << 1);
tmp = ((ACC (OP[0]) + tmp) & MASK40);
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* max */
void
-OP_2600 ()
+OP_2600 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("max", OP_REG, OP_REG, OP_VOID);
SET_PSW_F0 (0);
}
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* max */
void
-OP_3600 ()
+OP_3600 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
SET_PSW_F0 (0);
}
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* max */
void
-OP_3602 ()
+OP_3602 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID);
SET_PSW_F0 (0);
}
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* min */
void
-OP_2601 ()
+OP_2601 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("min", OP_REG, OP_REG, OP_VOID);
SET_PSW_F0 (0);
}
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* min */
void
-OP_3601 ()
+OP_3601 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
SET_PSW_F0 (0);
}
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* min */
void
-OP_3603 ()
+OP_3603 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID);
SET_PSW_F0 (0);
}
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* msb */
void
-OP_2800 ()
+OP_2800 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
tmp = (tmp & MASK40);
}
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* msbsu */
void
-OP_1800 ()
+OP_1800 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
tmp = SEXT40( (tmp << 1) & MASK40);
tmp = ((SEXT40 (ACC (OP[0])) - tmp) & MASK40);
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* msbu */
void
-OP_3800 ()
+OP_3800 (SIM_DESC sd, SIM_CPU *cpu)
{
uint64 tmp;
uint32 src1;
tmp = (tmp << 1);
tmp = ((ACC (OP[0]) - tmp) & MASK40);
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* mul */
void
-OP_2E00 ()
+OP_2E00 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("mul", OP_REG, OP_REG, OP_VOID);
tmp = GPR (OP[0]) * GPR (OP[1]);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* mulx */
void
-OP_2C00 ()
+OP_2C00 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
else
tmp = (tmp & MASK40);
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* mulxsu */
void
-OP_1C00 ()
+OP_1C00 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
tmp <<= 1;
tmp = (tmp & MASK40);
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* mulxu */
void
-OP_3C00 ()
+OP_3C00 (SIM_DESC sd, SIM_CPU *cpu)
{
uint64 tmp;
uint32 src1;
tmp <<= 1;
tmp = (tmp & MASK40);
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* mv */
void
-OP_4000 ()
+OP_4000 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID);
tmp = GPR (OP[1]);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* mv2w */
void
-OP_5000 ()
+OP_5000 (SIM_DESC sd, SIM_CPU *cpu)
{
int32 tmp;
trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID);
tmp = GPR32 (OP[1]);
SET_GPR32 (OP[0], tmp);
- trace_output_32 (tmp);
+ trace_output_32 (sd, tmp);
}
/* mv2wfac */
void
-OP_3E00 ()
+OP_3E00 (SIM_DESC sd, SIM_CPU *cpu)
{
int32 tmp;
trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID);
tmp = ACC (OP[1]);
SET_GPR32 (OP[0], tmp);
- trace_output_32 (tmp);
+ trace_output_32 (sd, tmp);
}
/* mv2wtac */
void
-OP_3E01 ()
+OP_3E01 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
trace_input ("mv2wtac", OP_DREG, OP_ACCUM_OUTPUT, OP_VOID);
tmp = ((SEXT16 (GPR (OP[0])) << 16 | GPR (OP[0] + 1)) & MASK40);
SET_ACC (OP[1], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* mvac */
void
-OP_3E03 ()
+OP_3E03 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID);
tmp = ACC (OP[1]);
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* mvb */
void
-OP_5400 ()
+OP_5400 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID);
tmp = SEXT8 (GPR (OP[1]) & 0xff);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* mvf0f */
void
-OP_4400 ()
+OP_4400 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
- trace_input ("mf0f", OP_REG_OUTPUT, OP_REG, OP_VOID);
+ trace_input ("mvf0f", OP_REG_OUTPUT, OP_REG, OP_VOID);
if (PSW_F0 == 0)
{
tmp = GPR (OP[1]);
}
else
tmp = GPR (OP[0]);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* mvf0t */
void
-OP_4401 ()
+OP_4401 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
- trace_input ("mf0t", OP_REG_OUTPUT, OP_REG, OP_VOID);
+ trace_input ("mvf0t", OP_REG_OUTPUT, OP_REG, OP_VOID);
if (PSW_F0)
{
tmp = GPR (OP[1]);
}
else
tmp = GPR (OP[0]);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* mvfacg */
void
-OP_1E04 ()
+OP_1E04 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
tmp = ((ACC (OP[1]) >> 32) & 0xff);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* mvfachi */
void
-OP_1E00 ()
+OP_1E00 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
tmp = (ACC (OP[1]) >> 16);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* mvfaclo */
void
-OP_1E02 ()
+OP_1E02 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
tmp = ACC (OP[1]);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* mvfc */
void
-OP_5200 ()
+OP_5200 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
tmp = CREG (OP[1]);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* mvtacg */
void
-OP_1E41 ()
+OP_1E41 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID);
tmp = ((ACC (OP[1]) & MASK32)
| ((int64)(GPR (OP[0]) & 0xff) << 32));
SET_ACC (OP[1], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* mvtachi */
void
-OP_1E01 ()
+OP_1E01 (SIM_DESC sd, SIM_CPU *cpu)
{
uint64 tmp;
trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID);
tmp = ACC (OP[1]) & 0xffff;
tmp = ((SEXT16 (GPR (OP[0])) << 16 | tmp) & MASK40);
SET_ACC (OP[1], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* mvtaclo */
void
-OP_1E21 ()
+OP_1E21 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID);
tmp = ((SEXT16 (GPR (OP[0]))) & MASK40);
SET_ACC (OP[1], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* mvtc */
void
-OP_5600 ()
+OP_5600 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
tmp = GPR (OP[0]);
tmp = SET_CREG (OP[1], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* mvub */
void
-OP_5401 ()
+OP_5401 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID);
tmp = (GPR (OP[1]) & 0xff);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* neg */
void
-OP_4605 ()
+OP_4605 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("neg", OP_REG, OP_VOID, OP_VOID);
tmp = - GPR (OP[0]);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* neg */
void
-OP_5605 ()
+OP_5605 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
else
tmp = (tmp & MASK40);
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* nop */
void
-OP_5E00 ()
+OP_5E00 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
break;
}
- trace_output_void ();
+ trace_output_void (sd);
}
/* not */
void
-OP_4603 ()
+OP_4603 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("not", OP_REG, OP_VOID, OP_VOID);
tmp = ~GPR (OP[0]);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* or */
void
-OP_800 ()
+OP_800 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("or", OP_REG, OP_REG, OP_VOID);
tmp = (GPR (OP[0]) | GPR (OP[1]));
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* or3 */
void
-OP_4000000 ()
+OP_4000000 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
tmp = (GPR (OP[1]) | OP[2]);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* rac */
void
-OP_5201 ()
+OP_5201 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
int shift = SEXT3 (OP[2]);
trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
if (OP[1] != 0)
{
- (*d10v_callback->printf_filtered) (d10v_callback,
+ sim_io_printf (sd,
"ERROR at PC 0x%x: instruction only valid for A0\n",
PC<<2);
- State.exception = SIGILL;
+ EXCEPTION (SIM_SIGILL);
}
SET_PSW_F1 (PSW_F0);
SET_PSW_F0 (0);
}
SET_GPR32 (OP[0], tmp);
- trace_output_32 (tmp);
+ trace_output_32 (sd, tmp);
}
/* rachi */
void
-OP_4201 ()
+OP_4201 (SIM_DESC sd, SIM_CPU *cpu)
{
signed64 tmp;
int shift = SEXT3 (OP[2]);
SET_PSW_F0 (0);
}
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* rep */
void
-OP_27000000 ()
+OP_27000000 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID);
SET_RPT_S (PC + 1);
SET_PSW_RP (1);
if (GPR (OP[0]) == 0)
{
- (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep with count=0 is illegal.\n");
- State.exception = SIGILL;
+ sim_io_printf (sd, "ERROR: rep with count=0 is illegal.\n");
+ EXCEPTION (SIM_SIGILL);
}
if (OP[1] < 4)
{
- (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: rep must include at least 4 instructions.\n");
- State.exception = SIGILL;
+ sim_io_printf (sd, "ERROR: rep must include at least 4 instructions.\n");
+ EXCEPTION (SIM_SIGILL);
}
- trace_output_void ();
+ trace_output_void (sd);
}
/* repi */
void
-OP_2F000000 ()
+OP_2F000000 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID);
SET_RPT_S (PC + 1);
SET_PSW_RP (1);
if (OP[0] == 0)
{
- (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi with count=0 is illegal.\n");
- State.exception = SIGILL;
+ sim_io_printf (sd, "ERROR: repi with count=0 is illegal.\n");
+ EXCEPTION (SIM_SIGILL);
}
if (OP[1] < 4)
{
- (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: repi must include at least 4 instructions.\n");
- State.exception = SIGILL;
+ sim_io_printf (sd, "ERROR: repi must include at least 4 instructions.\n");
+ EXCEPTION (SIM_SIGILL);
}
- trace_output_void ();
+ trace_output_void (sd);
}
/* rtd */
void
-OP_5F60 ()
+OP_5F60 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("rtd", OP_VOID, OP_VOID, OP_VOID);
SET_CREG (PSW_CR, DPSW);
JMP(DPC);
- trace_output_void ();
+ trace_output_void (sd);
}
/* rte */
void
-OP_5F40 ()
+OP_5F40 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("rte", OP_VOID, OP_VOID, OP_VOID);
SET_CREG (PSW_CR, BPSW);
JMP(BPC);
- trace_output_void ();
+ trace_output_void (sd);
+}
+
+/* sac */
+void OP_5209 (SIM_DESC sd, SIM_CPU *cpu)
+{
+ int64 tmp;
+
+ trace_input ("sac", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
+
+ tmp = SEXT40(ACC (OP[1]));
+
+ SET_PSW_F1 (PSW_F0);
+
+ if (tmp > SEXT40(MAX32))
+ {
+ tmp = (MAX32);
+ SET_PSW_F0 (1);
+ }
+ else if (tmp < SEXT40(MIN32))
+ {
+ tmp = 0x80000000;
+ SET_PSW_F0 (1);
+ }
+ else
+ {
+ tmp = (tmp & MASK32);
+ SET_PSW_F0 (0);
+ }
+
+ SET_GPR32 (OP[0], tmp);
+
+ trace_output_40 (sd, tmp);
+}
+
+/* sachi */
+void
+OP_4209 (SIM_DESC sd, SIM_CPU *cpu)
+{
+ int64 tmp;
+
+ trace_input ("sachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
+
+ tmp = SEXT40(ACC (OP[1]));
+
+ SET_PSW_F1 (PSW_F0);
+
+ if (tmp > SEXT40(MAX32))
+ {
+ tmp = 0x7fff;
+ SET_PSW_F0 (1);
+ }
+ else if (tmp < SEXT40(MIN32))
+ {
+ tmp = 0x8000;
+ SET_PSW_F0 (1);
+ }
+ else
+ {
+ tmp >>= 16;
+ SET_PSW_F0 (0);
+ }
+
+ SET_GPR (OP[0], tmp);
+
+ trace_output_16 (sd, OP[0]);
}
/* sadd */
void
-OP_1223 ()
+OP_1223 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
else
tmp = (tmp & MASK40);
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* setf0f */
void
-OP_4611 ()
+OP_4611 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID);
tmp = ((PSW_F0 == 0) ? 1 : 0);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* setf0t */
void
-OP_4613 ()
+OP_4613 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID);
tmp = ((PSW_F0 == 1) ? 1 : 0);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
+}
+
+/* slae */
+void
+OP_3220 (SIM_DESC sd, SIM_CPU *cpu)
+{
+ int64 tmp;
+ int16 reg;
+
+ trace_input ("slae", OP_ACCUM, OP_REG, OP_VOID);
+
+ reg = SEXT16 (GPR (OP[1]));
+
+ if (reg >= 17 || reg <= -17)
+ {
+ sim_io_printf (sd, "ERROR: shift value %d too large.\n", reg);
+ EXCEPTION (SIM_SIGILL);
+ }
+
+ tmp = SEXT40 (ACC (OP[0]));
+
+ if (PSW_ST && (tmp < SEXT40 (MIN32) || tmp > SEXT40 (MAX32)))
+ {
+ sim_io_printf (sd, "ERROR: accumulator value 0x%.2x%.8lx out of range\n", ((int)(tmp >> 32) & 0xff), ((unsigned long) tmp) & 0xffffffff);
+ EXCEPTION (SIM_SIGILL);
+ }
+
+ if (reg >= 0 && reg <= 16)
+ {
+ tmp = SEXT56 ((SEXT56 (tmp)) << (GPR (OP[1])));
+ if (PSW_ST)
+ {
+ if (tmp > SEXT40(MAX32))
+ tmp = (MAX32);
+ else if (tmp < SEXT40(MIN32))
+ tmp = (MIN32);
+ else
+ tmp = (tmp & MASK40);
+ }
+ else
+ tmp = (tmp & MASK40);
+ }
+ else
+ {
+ tmp = (SEXT40 (ACC (OP[0]))) >> (-GPR (OP[1]));
+ }
+
+ SET_ACC(OP[0], tmp);
+
+ trace_output_40 (sd, tmp);
}
/* sleep */
void
-OP_5FC0 ()
+OP_5FC0 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID);
SET_PSW_IE (1);
- trace_output_void ();
+ trace_output_void (sd);
}
/* sll */
void
-OP_2200 ()
+OP_2200 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("sll", OP_REG, OP_REG, OP_VOID);
tmp = (GPR (OP[0]) << (GPR (OP[1]) & 0xf));
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* sll */
void
-OP_3200 ()
+OP_3200 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID);
tmp = SEXT40 (ACC (OP[0])) << (GPR (OP[1]) & 31);
else
{
- (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
- State.exception = SIGILL;
- return;
+ sim_io_printf (sd, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
+ EXCEPTION (SIM_SIGILL);
}
if (PSW_ST)
else
tmp = (tmp & MASK40);
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* slli */
void
-OP_2201 ()
+OP_2201 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID);
tmp = (GPR (OP[0]) << OP[1]);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* slli */
void
-OP_3201 ()
+OP_3201 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
else
tmp = (tmp & MASK40);
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* slx */
void
-OP_460B ()
+OP_460B (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
- trace_input ("slx", OP_REG, OP_FLAG, OP_VOID);
+ trace_input ("slx", OP_REG, OP_VOID, OP_VOID);
tmp = ((GPR (OP[0]) << 1) | PSW_F0);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* sra */
void
-OP_2400 ()
+OP_2400 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("sra", OP_REG, OP_REG, OP_VOID);
tmp = (((int16)(GPR (OP[0]))) >> (GPR (OP[1]) & 0xf));
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* sra */
void
-OP_3400 ()
+OP_3400 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID);
if ((GPR (OP[1]) & 31) <= 16)
{
int64 tmp = ((SEXT40(ACC (OP[0])) >> (GPR (OP[1]) & 31)) & MASK40);
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
else
{
- (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
- State.exception = SIGILL;
- return;
+ sim_io_printf (sd, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
+ EXCEPTION (SIM_SIGILL);
}
}
/* srai */
void
-OP_2401 ()
+OP_2401 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID);
tmp = (((int16)(GPR (OP[0]))) >> OP[1]);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* srai */
void
-OP_3401 ()
+OP_3401 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
if (OP[1] == 0)
trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID);
tmp = ((SEXT40(ACC (OP[0])) >> OP[1]) & MASK40);
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* srl */
void
-OP_2000 ()
+OP_2000 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("srl", OP_REG, OP_REG, OP_VOID);
tmp = (GPR (OP[0]) >> (GPR (OP[1]) & 0xf));
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* srl */
void
-OP_3000 ()
+OP_3000 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID);
if ((GPR (OP[1]) & 31) <= 16)
{
int64 tmp = ((uint64)((ACC (OP[0]) & MASK40) >> (GPR (OP[1]) & 31)));
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
else
{
- (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
- State.exception = SIGILL;
- return;
+ sim_io_printf (sd, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31);
+ EXCEPTION (SIM_SIGILL);
}
}
/* srli */
void
-OP_2001 ()
+OP_2001 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID);
tmp = (GPR (OP[0]) >> OP[1]);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* srli */
void
-OP_3001 ()
+OP_3001 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
if (OP[1] == 0)
trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
tmp = ((uint64)(ACC (OP[0]) & MASK40) >> OP[1]);
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* srx */
void
-OP_4609 ()
+OP_4609 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 tmp;
- trace_input ("srx", OP_REG, OP_FLAG, OP_VOID);
+ trace_input ("srx", OP_REG, OP_VOID, OP_VOID);
tmp = PSW_F0 << 15;
tmp = ((GPR (OP[0]) >> 1) | tmp);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* st */
void
-OP_34000000 ()
+OP_34000000 (SIM_DESC sd, SIM_CPU *cpu)
{
+ uint16 addr = OP[1] + GPR (OP[2]);
trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID);
- SW (OP[1] + GPR (OP[2]), GPR (OP[0]));
- trace_output_void ();
+ if ((addr & 1))
+ {
+ trace_output_void (sd);
+ EXCEPTION (SIM_SIGBUS);
+ }
+ SW (addr, GPR (OP[0]));
+ trace_output_void (sd);
}
/* st */
void
-OP_6800 ()
+OP_6800 (SIM_DESC sd, SIM_CPU *cpu)
{
+ uint16 addr = GPR (OP[1]);
trace_input ("st", OP_REG, OP_MEMREF, OP_VOID);
- SW (GPR (OP[1]), GPR (OP[0]));
- trace_output_void ();
+ if ((addr & 1))
+ {
+ trace_output_void (sd);
+ EXCEPTION (SIM_SIGBUS);
+ }
+ SW (addr, GPR (OP[0]));
+ trace_output_void (sd);
}
/* st */
+/* st Rsrc1,@-SP */
void
-OP_6C1F ()
+OP_6C1F (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 addr = GPR (OP[1]) - 2;
trace_input ("st", OP_REG, OP_PREDEC, OP_VOID);
if (OP[1] != 15)
{
- (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
- State.exception = SIGILL;
- return;
+ sim_io_printf (sd, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
+ EXCEPTION (SIM_SIGILL);
+ }
+ if ((addr & 1))
+ {
+ trace_output_void (sd);
+ EXCEPTION (SIM_SIGBUS);
}
SW (addr, GPR (OP[0]));
SET_GPR (OP[1], addr);
- trace_output_void ();
+ trace_output_void (sd);
}
/* st */
void
-OP_6801 ()
+OP_6801 (SIM_DESC sd, SIM_CPU *cpu)
{
+ uint16 addr = GPR (OP[1]);
trace_input ("st", OP_REG, OP_POSTINC, OP_VOID);
- SW (GPR (OP[1]), GPR (OP[0]));
+ if ((addr & 1))
+ {
+ trace_output_void (sd);
+ EXCEPTION (SIM_SIGBUS);
+ }
+ SW (addr, GPR (OP[0]));
INC_ADDR (OP[1], 2);
- trace_output_void ();
+ trace_output_void (sd);
}
/* st */
void
-OP_6C01 ()
+OP_6C01 (SIM_DESC sd, SIM_CPU *cpu)
{
+ uint16 addr = GPR (OP[1]);
trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID);
if ( OP[1] == 15 )
{
- (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
- State.exception = SIGILL;
- return;
+ sim_io_printf (sd, "ERROR: cannot post-decrement register r15 (SP).\n");
+ EXCEPTION (SIM_SIGILL);
}
- SW (GPR (OP[1]), GPR (OP[0]));
+ if ((addr & 1))
+ {
+ trace_output_void (sd);
+ EXCEPTION (SIM_SIGBUS);
+ }
+ SW (addr, GPR (OP[0]));
INC_ADDR (OP[1], -2);
- trace_output_void ();
+ trace_output_void (sd);
+}
+
+/* st */
+void
+OP_36010000 (SIM_DESC sd, SIM_CPU *cpu)
+{
+ uint16 addr = OP[1];
+ trace_input ("st", OP_REG, OP_MEMREF3, OP_VOID);
+ if ((addr & 1))
+ {
+ trace_output_void (sd);
+ EXCEPTION (SIM_SIGBUS);
+ }
+ SW (addr, GPR (OP[0]));
+ trace_output_void (sd);
}
/* st2w */
void
-OP_35000000 ()
+OP_35000000 (SIM_DESC sd, SIM_CPU *cpu)
{
+ uint16 addr = GPR (OP[2])+ OP[1];
trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID);
- SW (GPR (OP[2])+ OP[1] + 0, GPR (OP[0] + 0));
- SW (GPR (OP[2])+ OP[1] + 2, GPR (OP[0] + 1));
- trace_output_void ();
+ if ((addr & 1))
+ {
+ trace_output_void (sd);
+ EXCEPTION (SIM_SIGBUS);
+ }
+ SW (addr + 0, GPR (OP[0] + 0));
+ SW (addr + 2, GPR (OP[0] + 1));
+ trace_output_void (sd);
}
/* st2w */
void
-OP_6A00 ()
+OP_6A00 (SIM_DESC sd, SIM_CPU *cpu)
{
+ uint16 addr = GPR (OP[1]);
trace_input ("st2w", OP_DREG, OP_MEMREF, OP_VOID);
- SW (GPR (OP[1]) + 0, GPR (OP[0] + 0));
- SW (GPR (OP[1]) + 2, GPR (OP[0] + 1));
- trace_output_void ();
+ if ((addr & 1))
+ {
+ trace_output_void (sd);
+ EXCEPTION (SIM_SIGBUS);
+ }
+ SW (addr + 0, GPR (OP[0] + 0));
+ SW (addr + 2, GPR (OP[0] + 1));
+ trace_output_void (sd);
}
/* st2w */
void
-OP_6E1F ()
+OP_6E1F (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 addr = GPR (OP[1]) - 4;
trace_input ("st2w", OP_DREG, OP_PREDEC, OP_VOID);
if ( OP[1] != 15 )
{
- (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
- State.exception = SIGILL;
- return;
+ sim_io_printf (sd, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
+ EXCEPTION (SIM_SIGILL);
+ }
+ if ((addr & 1))
+ {
+ trace_output_void (sd);
+ EXCEPTION (SIM_SIGBUS);
}
SW (addr + 0, GPR (OP[0] + 0));
SW (addr + 2, GPR (OP[0] + 1));
SET_GPR (OP[1], addr);
- trace_output_void ();
+ trace_output_void (sd);
}
/* st2w */
void
-OP_6A01 ()
+OP_6A01 (SIM_DESC sd, SIM_CPU *cpu)
{
+ uint16 addr = GPR (OP[1]);
trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID);
- SW (GPR (OP[1]) + 0, GPR (OP[0] + 0));
- SW (GPR (OP[1]) + 2, GPR (OP[0] + 1));
+ if ((addr & 1))
+ {
+ trace_output_void (sd);
+ EXCEPTION (SIM_SIGBUS);
+ }
+ SW (addr + 0, GPR (OP[0] + 0));
+ SW (addr + 2, GPR (OP[0] + 1));
INC_ADDR (OP[1], 4);
- trace_output_void ();
+ trace_output_void (sd);
}
/* st2w */
void
-OP_6E01 ()
+OP_6E01 (SIM_DESC sd, SIM_CPU *cpu)
{
+ uint16 addr = GPR (OP[1]);
trace_input ("st2w", OP_DREG, OP_POSTDEC, OP_VOID);
if ( OP[1] == 15 )
{
- (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
- State.exception = SIGILL;
- return;
+ sim_io_printf (sd, "ERROR: cannot post-decrement register r15 (SP).\n");
+ EXCEPTION (SIM_SIGILL);
+ }
+ if ((addr & 1))
+ {
+ trace_output_void (sd);
+ EXCEPTION (SIM_SIGBUS);
}
- SW (GPR (OP[1]) + 0, GPR (OP[0] + 0));
- SW (GPR (OP[1]) + 2, GPR (OP[0] + 1));
+ SW (addr + 0, GPR (OP[0] + 0));
+ SW (addr + 2, GPR (OP[0] + 1));
INC_ADDR (OP[1], -4);
- trace_output_void ();
+ trace_output_void (sd);
+}
+
+/* st2w */
+void
+OP_37010000 (SIM_DESC sd, SIM_CPU *cpu)
+{
+ uint16 addr = OP[1];
+ trace_input ("st2w", OP_DREG, OP_MEMREF3, OP_VOID);
+ if ((addr & 1))
+ {
+ trace_output_void (sd);
+ EXCEPTION (SIM_SIGBUS);
+ }
+ SW (addr + 0, GPR (OP[0] + 0));
+ SW (addr + 2, GPR (OP[0] + 1));
+ trace_output_void (sd);
}
/* stb */
void
-OP_3C000000 ()
+OP_3C000000 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID);
SB (GPR (OP[2]) + OP[1], GPR (OP[0]));
- trace_output_void ();
+ trace_output_void (sd);
}
/* stb */
void
-OP_7800 ()
+OP_7800 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID);
SB (GPR (OP[1]), GPR (OP[0]));
- trace_output_void ();
+ trace_output_void (sd);
}
/* stop */
void
-OP_5FE0 ()
+OP_5FE0 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("stop", OP_VOID, OP_VOID, OP_VOID);
- State.exception = SIG_D10V_STOP;
- trace_output_void ();
+ trace_output_void (sd);
+ sim_engine_halt (sd, cpu, NULL, PC, sim_exited, 0);
}
/* sub */
void
-OP_0 ()
+OP_0 (SIM_DESC sd, SIM_CPU *cpu)
{
uint16 a = GPR (OP[0]);
uint16 b = GPR (OP[1]);
compute the carry/overflow bits. */
SET_PSW_C (a >= b);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* sub */
void
-OP_1001 ()
+OP_1001 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
tmp = (tmp & MASK40);
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* sub */
void
-OP_1003 ()
+OP_1003 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
tmp = (tmp & MASK40);
SET_ACC (OP[0], tmp);
- trace_output_40 (tmp);
+ trace_output_40 (sd, tmp);
}
/* sub2w */
void
-OP_1000 ()
+OP_1000 (SIM_DESC sd, SIM_CPU *cpu)
{
uint32 tmp, a, b;
tmp = a - b;
SET_PSW_C (a >= b);
SET_GPR32 (OP[0], tmp);
- trace_output_32 (tmp);
+ trace_output_32 (sd, tmp);
}
/* subac3 */
void
-OP_17000000 ()
+OP_17000000 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM);
tmp = SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)) - SEXT40 (ACC (OP[2]));
SET_GPR32 (OP[0], tmp);
- trace_output_32 (tmp);
+ trace_output_32 (sd, tmp);
}
/* subac3 */
void
-OP_17000002 ()
+OP_17000002 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM);
tmp = SEXT40 (ACC (OP[1])) - SEXT40(ACC (OP[2]));
SET_GPR32 (OP[0], tmp);
- trace_output_32 (tmp);
+ trace_output_32 (sd, tmp);
}
/* subac3s */
void
-OP_17001000 ()
+OP_17001000 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
SET_PSW_F0 (0);
}
SET_GPR32 (OP[0], tmp);
- trace_output_32 (tmp);
+ trace_output_32 (sd, tmp);
}
/* subac3s */
void
-OP_17001002 ()
+OP_17001002 (SIM_DESC sd, SIM_CPU *cpu)
{
int64 tmp;
SET_PSW_F0 (0);
}
SET_GPR32 (OP[0], tmp);
- trace_output_32 (tmp);
+ trace_output_32 (sd, tmp);
}
/* subi */
void
-OP_1 ()
+OP_1 (SIM_DESC sd, SIM_CPU *cpu)
{
unsigned tmp;
if (OP[1] == 0)
+ (unsigned)(unsigned16) ( - OP[1]));
SET_PSW_C (tmp >= (1 << 16));
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* trap */
void
-OP_5F00 ()
+OP_5F00 (SIM_DESC sd, SIM_CPU *cpu)
{
+ host_callback *cb = STATE_CALLBACK (sd);
+
trace_input ("trap", OP_CONSTANT4, OP_VOID, OP_VOID);
- trace_output_void ();
+ trace_output_void (sd);
switch (OP[0])
{
if (first_time)
{
first_time = 0;
- (*d10v_callback->printf_filtered) (d10v_callback, "Trap # PC ");
+ sim_io_printf (sd, "Trap # PC ");
for (i = 0; i < 16; i++)
- (*d10v_callback->printf_filtered) (d10v_callback, " %sr%d", (i > 9) ? "" : " ", i);
- (*d10v_callback->printf_filtered) (d10v_callback, " a0 a1 f0 f1 c\n");
+ sim_io_printf (sd, " %sr%d", (i > 9) ? "" : " ", i);
+ sim_io_printf (sd, " a0 a1 f0 f1 c\n");
}
- (*d10v_callback->printf_filtered) (d10v_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
+ sim_io_printf (sd, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
for (i = 0; i < 16; i++)
- (*d10v_callback->printf_filtered) (d10v_callback, " %.4x", (int) GPR (i));
+ sim_io_printf (sd, " %.4x", (int) GPR (i));
for (i = 0; i < 2; i++)
- (*d10v_callback->printf_filtered) (d10v_callback, " %.2x%.8lx",
+ sim_io_printf (sd, " %.2x%.8lx",
((int)(ACC (i) >> 32) & 0xff),
((unsigned long) ACC (i)) & 0xffffffff);
- (*d10v_callback->printf_filtered) (d10v_callback, " %d %d %d\n",
+ sim_io_printf (sd, " %d %d %d\n",
PSW_F0 != 0, PSW_F1 != 0, PSW_C != 0);
- (*d10v_callback->flush_stdout) (d10v_callback);
+ sim_io_flush_stdout (sd);
break;
}
#endif
/* Turn a pointer in a register into a pointer into real memory. */
-#define MEMPTR(x) ((char *)(dmem_addr(x)))
+#define MEMPTR(x) ((char *)(dmem_addr (sd, cpu, x)))
switch (FUNC)
{
case TARGET_SYS_fork:
trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID);
RETVAL (fork ());
- trace_output_16 (result);
+ trace_output_16 (sd, result);
break;
#define getpid() 47
case TARGET_SYS_getpid:
trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
RETVAL (getpid ());
- trace_output_16 (result);
+ trace_output_16 (sd, result);
break;
case TARGET_SYS_kill:
trace_input ("<kill>", OP_R0, OP_R1, OP_VOID);
if (PARM1 == getpid ())
{
- trace_output_void ();
- State.exception = PARM2;
+ trace_output_void (sd);
+ sim_engine_halt (sd, cpu, NULL, PC, sim_stopped, PARM2);
}
else
{
if (os_sig == -1)
{
- trace_output_void ();
- (*d10v_callback->printf_filtered) (d10v_callback, "Unknown signal %d\n", PARM2);
- (*d10v_callback->flush_stdout) (d10v_callback);
- State.exception = SIGILL;
+ trace_output_void (sd);
+ sim_io_printf (sd, "Unknown signal %d\n", PARM2);
+ sim_io_flush_stdout (sd);
+ EXCEPTION (SIM_SIGILL);
}
else
{
RETVAL (kill (PARM1, PARM2));
- trace_output_16 (result);
+ trace_output_16 (sd, result);
}
}
break;
trace_input ("<execve>", OP_R0, OP_R1, OP_R2);
RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
(char **)MEMPTR (PARM3)));
- trace_output_16 (result);
+ trace_output_16 (sd, result);
break;
#ifdef TARGET_SYS_execv
case TARGET_SYS_execv:
trace_input ("<execv>", OP_R0, OP_R1, OP_VOID);
RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL));
- trace_output_16 (result);
+ trace_output_16 (sd, result);
break;
#endif
SW (buf, host_fd[0]);
buf += sizeof(uint16);
SW (buf, host_fd[1]);
- trace_output_16 (result);
+ trace_output_16 (sd, result);
}
break;
RETVAL (wait (&status));
if (PARM1)
SW (PARM1, status);
- trace_output_16 (result);
+ trace_output_16 (sd, result);
}
break;
#endif
case TARGET_SYS_getpid:
trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
RETVAL (1);
- trace_output_16 (result);
+ trace_output_16 (sd, result);
break;
case TARGET_SYS_kill:
trace_input ("<kill>", OP_REG, OP_REG, OP_VOID);
- trace_output_void ();
- State.exception = PARM2;
+ trace_output_void (sd);
+ sim_engine_halt (sd, cpu, NULL, PC, sim_stopped, PARM2);
break;
#endif
case TARGET_SYS_read:
trace_input ("<read>", OP_R0, OP_R1, OP_R2);
- RETVAL (d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2),
- PARM3));
- trace_output_16 (result);
+ RETVAL (cb->read (cb, PARM1, MEMPTR (PARM2), PARM3));
+ trace_output_16 (sd, result);
break;
case TARGET_SYS_write:
trace_input ("<write>", OP_R0, OP_R1, OP_R2);
if (PARM1 == 1)
- RETVAL ((int)d10v_callback->write_stdout (d10v_callback,
- MEMPTR (PARM2), PARM3));
+ RETVAL ((int)cb->write_stdout (cb, MEMPTR (PARM2), PARM3));
else
- RETVAL ((int)d10v_callback->write (d10v_callback, PARM1,
- MEMPTR (PARM2), PARM3));
- trace_output_16 (result);
+ RETVAL ((int)cb->write (cb, PARM1, MEMPTR (PARM2), PARM3));
+ trace_output_16 (sd, result);
break;
case TARGET_SYS_lseek:
trace_input ("<lseek>", OP_R0, OP_R1, OP_R2);
- RETVAL32 (d10v_callback->lseek (d10v_callback, PARM1,
- ((((unsigned long) PARM2) << 16)
- || (unsigned long) PARM3),
- PARM4));
- trace_output_32 (result);
+ RETVAL32 (cb->lseek (cb, PARM1,
+ ((((unsigned long) PARM2) << 16)
+ || (unsigned long) PARM3),
+ PARM4));
+ trace_output_32 (sd, result);
break;
case TARGET_SYS_close:
trace_input ("<close>", OP_R0, OP_VOID, OP_VOID);
- RETVAL (d10v_callback->close (d10v_callback, PARM1));
- trace_output_16 (result);
+ RETVAL (cb->close (cb, PARM1));
+ trace_output_16 (sd, result);
break;
case TARGET_SYS_open:
trace_input ("<open>", OP_R0, OP_R1, OP_R2);
- RETVAL (d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2));
- trace_output_16 (result);
+ RETVAL (cb->open (cb, MEMPTR (PARM1), PARM2));
+ trace_output_16 (sd, result);
break;
case TARGET_SYS_exit:
trace_input ("<exit>", OP_R0, OP_VOID, OP_VOID);
- State.exception = SIG_D10V_EXIT;
- trace_output_void ();
+ trace_output_void (sd);
+ sim_engine_halt (sd, cpu, NULL, PC, sim_exited, GPR (0));
break;
#ifdef TARGET_SYS_stat
SLW (buf+28, host_stat.st_mtime);
SLW (buf+36, host_stat.st_ctime);
}
- trace_output_16 (result);
+ trace_output_16 (sd, result);
break;
#endif
case TARGET_SYS_chown:
trace_input ("<chown>", OP_R0, OP_R1, OP_R2);
RETVAL (chown (MEMPTR (PARM1), PARM2, PARM3));
- trace_output_16 (result);
+ trace_output_16 (sd, result);
break;
case TARGET_SYS_chmod:
trace_input ("<chmod>", OP_R0, OP_R1, OP_R2);
RETVAL (chmod (MEMPTR (PARM1), PARM2));
- trace_output_16 (result);
+ trace_output_16 (sd, result);
break;
#if 0
/* Cast the second argument to void *, to avoid type mismatch
if a prototype is present. */
RETVAL (utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2)));
- trace_output_16 (result);
+ trace_output_16 (sd, result);
break;
#endif
#endif
case TARGET_SYS_time:
trace_input ("<time>", OP_R0, OP_R1, OP_R2);
RETVAL32 (time (PARM1 ? MEMPTR (PARM1) : NULL));
- trace_output_32 (result);
+ trace_output_32 (sd, result);
break;
#endif
#endif
default:
- d10v_callback->error (d10v_callback, "Unknown syscall %d", FUNC);
+ cb->error (cb, "Unknown syscall %d", FUNC);
}
if ((uint16) result == (uint16) -1)
- RETERR (d10v_callback->get_errno(d10v_callback));
+ RETERR (cb->get_errno (cb));
else
RETERR (0);
break;
/* tst0i */
void
-OP_7000000 ()
+OP_7000000 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID);
SET_PSW_F1 (PSW_F0);;
SET_PSW_F0 ((GPR (OP[0]) & OP[1]) ? 1 : 0);
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* tst1i */
void
-OP_F000000 ()
+OP_F000000 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID);
SET_PSW_F1 (PSW_F0);
SET_PSW_F0 ((~(GPR (OP[0])) & OP[1]) ? 1 : 0);
- trace_output_flag ();
+ trace_output_flag (sd);
}
/* wait */
void
-OP_5F80 ()
+OP_5F80 (SIM_DESC sd, SIM_CPU *cpu)
{
trace_input ("wait", OP_VOID, OP_VOID, OP_VOID);
SET_PSW_IE (1);
- trace_output_void ();
+ trace_output_void (sd);
}
/* xor */
void
-OP_A00 ()
+OP_A00 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("xor", OP_REG, OP_REG, OP_VOID);
tmp = (GPR (OP[0]) ^ GPR (OP[1]));
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
/* xor3 */
void
-OP_5000000 ()
+OP_5000000 (SIM_DESC sd, SIM_CPU *cpu)
{
int16 tmp;
trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
tmp = (GPR (OP[1]) ^ OP[2]);
SET_GPR (OP[0], tmp);
- trace_output_16 (tmp);
+ trace_output_16 (sd, tmp);
}
-
projects / deliverable / binutils-gdb.git / blobdiff