Make the objfile destructor private

[deliverable/binutils-gdb.git] / sim / frv / profile.h

diff --git a/sim/frv/profile.h b/sim/frv/profile.h
index ec36cf6022ea51888efa3eb2c1fa05c95aed5b13..cca415fdb5e2ff803d7e2f7095adef26f91605cb 100644 (file)
--- a/sim/frv/profile.h
+++ b/sim/frv/profile.h
@@ -1,22 +1,21 @@
 /* Profiling definitions for the FRV simulator
-   Copyright (C) 1998, 1999, 2000, 2001, 2003 Free Software Foundation, Inc.
+   Copyright (C) 1998-2019 Free Software Foundation, Inc.
    Contributed by Red Hat.
 
 This file is part of the GNU Simulators.
 
 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+the Free Software Foundation; either version 3 of the License, or
+(at your option) any later version.
 
 This program is distributed in the hope that it will be useful,
 but WITHOUT ANY WARRANTY; without even the implied warranty of
 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+You should have received a copy of the GNU General Public License
+along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
 
 #ifndef PROFILE_H
 #define PROFILE_H
@@ -45,6 +44,8 @@ typedef struct
   int idiv_busy[2];      /* Cycles until integer division unit is available.  */
   int fdiv_busy[2];      /* Cycles until float division unit is available.  */
   int fsqrt_busy[2];     /* Cycles until square root unit is available.  */
+  int float_busy[4];     /* Cycles until floating point unit is available.  */
+  int media_busy[4];     /* Cycles until media unit is available.  */
   int branch_penalty;    /* Cycles until branch is complete.  */
 
   int gr_latency[64];    /* Cycles until target GR is available.  */
@@ -72,6 +73,8 @@ typedef struct
   int branch_hint;       /* hint field from branch insn.  */
   USI branch_address;    /* Address of predicted branch.  */
   USI insn_fetch_address;/* Address of sequential insns fetched.  */
+  int mclracc_acc;       /* ACC number of register cleared by mclracc.  */
+  int mclracc_A;         /* A field of mclracc.  */
 
   /* We need to know when the first branch of a vliw insn is taken, so that
      we don't consider the remaining branches in the vliw insn.  */
@@ -111,18 +114,24 @@ void update_FR_latency (SIM_CPU *, INT, int);
 void update_FRdouble_latency (SIM_CPU *, INT, int);
 void update_FR_latency_for_load (SIM_CPU *, INT, int);
 void update_FRdouble_latency_for_load (SIM_CPU *, INT, int);
+void update_FR_ptime (SIM_CPU *, INT, int);
+void update_FRdouble_ptime (SIM_CPU *, INT, int);
 void decrease_ACC_busy (SIM_CPU *, INT, int);
 void decrease_FR_busy (SIM_CPU *, INT, int);
 void decrease_GR_busy (SIM_CPU *, INT, int);
 void increase_FR_busy (SIM_CPU *, INT, int);
+void increase_ACC_busy (SIM_CPU *, INT, int);
 void update_ACC_latency (SIM_CPU *, INT, int);
 void update_CCR_latency (SIM_CPU *, INT, int);
 void update_SPR_latency (SIM_CPU *, INT, int);
 void update_idiv_resource_latency (SIM_CPU *, INT, int);
 void update_fdiv_resource_latency (SIM_CPU *, INT, int);
 void update_fsqrt_resource_latency (SIM_CPU *, INT, int);
+void update_float_resource_latency (SIM_CPU *, INT, int);
+void update_media_resource_latency (SIM_CPU *, INT, int);
 void update_branch_penalty (SIM_CPU *, int);
 void update_ACC_ptime (SIM_CPU *, INT, int);
+void update_SPR_ptime (SIM_CPU *, INT, int);
 void vliw_wait_for_GR (SIM_CPU *, INT);
 void vliw_wait_for_GRdouble (SIM_CPU *, INT);
 void vliw_wait_for_FR (SIM_CPU *, INT);
@@ -133,17 +142,23 @@ void vliw_wait_for_SPR (SIM_CPU *, INT);
 void vliw_wait_for_idiv_resource (SIM_CPU *, INT);
 void vliw_wait_for_fdiv_resource (SIM_CPU *, INT);
 void vliw_wait_for_fsqrt_resource (SIM_CPU *, INT);
+void vliw_wait_for_float_resource (SIM_CPU *, INT);
+void vliw_wait_for_media_resource (SIM_CPU *, INT);
 void load_wait_for_GR (SIM_CPU *, INT);
 void load_wait_for_FR (SIM_CPU *, INT);
 void load_wait_for_GRdouble (SIM_CPU *, INT);
 void load_wait_for_FRdouble (SIM_CPU *, INT);
 void enforce_full_fr_latency (SIM_CPU *, INT);
+void enforce_full_acc_latency (SIM_CPU *, INT);
 int post_wait_for_FR (SIM_CPU *, INT);
 int post_wait_for_FRdouble (SIM_CPU *, INT);
 int post_wait_for_ACC (SIM_CPU *, INT);
 int post_wait_for_CCR (SIM_CPU *, INT);
+int post_wait_for_SPR (SIM_CPU *, INT);
 int post_wait_for_fdiv (SIM_CPU *, INT);
 int post_wait_for_fsqrt (SIM_CPU *, INT);
+int post_wait_for_float (SIM_CPU *, INT);
+int post_wait_for_media (SIM_CPU *, INT);
 
 void trace_vliw_wait_cycles (SIM_CPU *);
 void handle_resource_wait (SIM_CPU *);