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[deliverable/binutils-gdb.git] / sim / m32r / decodex.c

diff --git a/sim/m32r/decodex.c b/sim/m32r/decodex.c
index 8f6ba67e5ef54982e561d5447269043e6ad8b078..77211bcb74a8d6a9302e9eefea27dc3c7b01b221 100644 (file)
--- a/sim/m32r/decodex.c
+++ b/sim/m32r/decodex.c
@@ -2,22 +2,22 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+Copyright 1996-2020 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 3 of the License, or
-(at your option) any later version.
+   This file is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program.  If not, see <http://www.gnu.org/licenses/>.
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, see <http://www.gnu.org/licenses/>.
 
 */
 
@@ -177,7 +177,8 @@ static const struct insn_sem m32rxf_insn_sem[] =
   { M32R_INSN_BTST, M32RXF_INSN_BTST, M32RXF_SFMT_BTST, M32RXF_INSN_PAR_BTST, M32RXF_INSN_WRITE_BTST },
 };
 
-static const struct insn_sem m32rxf_insn_sem_invalid = {
+static const struct insn_sem m32rxf_insn_sem_invalid =
+{
   VIRTUAL_INSN_X_INVALID, M32RXF_INSN_X_INVALID, M32RXF_SFMT_EMPTY, NOPAR, NOPAR
 };
 
@@ -227,7 +228,7 @@ m32rxf_init_idesc_table (SIM_CPU *cpu)
     init_idesc (cpu, id, t);
 
   /* Now fill in the values for the chosen cpu.  */
-  for (t = m32rxf_insn_sem, tend = t + sizeof (m32rxf_insn_sem) / sizeof (*t);
+  for (t = m32rxf_insn_sem, tend = t + ARRAY_SIZE (m32rxf_insn_sem);
        t != tend; ++t)
     {
       init_idesc (cpu, & table[t->index], t);
@@ -251,14 +252,14 @@ m32rxf_init_idesc_table (SIM_CPU *cpu)
 
 const IDESC *
 m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
-              CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn,
+              CGEN_INSN_WORD base_insn, CGEN_INSN_WORD entire_insn,
               ARGBUF *abuf)
 {
   /* Result of decoder.  */
   M32RXF_INSN_TYPE itype;
 
   {
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 
     {
       unsigned int val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0)));
@@ -276,8 +277,14 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 8) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = M32RXF_INSN_CMPZ; goto extract_sfmt_cmpz;
-          case 3 : itype = M32RXF_INSN_PCMPBZ; goto extract_sfmt_cmpz;
+          case 0 :
+            if ((entire_insn & 0xfff0) == 0x70)
+              { itype = M32RXF_INSN_CMPZ; goto extract_sfmt_cmpz; }
+            itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 3 :
+            if ((entire_insn & 0xfff0) == 0x370)
+              { itype = M32RXF_INSN_PCMPBZ; goto extract_sfmt_cmpz; }
+            itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -288,7 +295,10 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
       case 12 : itype = M32RXF_INSN_AND; goto extract_sfmt_add;
       case 13 : itype = M32RXF_INSN_XOR; goto extract_sfmt_add;
       case 14 : itype = M32RXF_INSN_OR; goto extract_sfmt_add;
-      case 15 : itype = M32RXF_INSN_BTST; goto extract_sfmt_btst;
+      case 15 :
+        if ((entire_insn & 0xf8f0) == 0xf0)
+          { itype = M32RXF_INSN_BTST; goto extract_sfmt_btst; }
+        itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
       case 16 : itype = M32RXF_INSN_SRL; goto extract_sfmt_add;
       case 18 : itype = M32RXF_INSN_SRA; goto extract_sfmt_add;
       case 20 : itype = M32RXF_INSN_SLL; goto extract_sfmt_add;
@@ -301,15 +311,33 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 8) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = M32RXF_INSN_JC; goto extract_sfmt_jc;
-          case 1 : itype = M32RXF_INSN_JNC; goto extract_sfmt_jc;
-          case 2 : itype = M32RXF_INSN_JL; goto extract_sfmt_jl;
-          case 3 : itype = M32RXF_INSN_JMP; goto extract_sfmt_jmp;
+          case 0 :
+            if ((entire_insn & 0xfff0) == 0x1cc0)
+              { itype = M32RXF_INSN_JC; goto extract_sfmt_jc; }
+            itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0xfff0) == 0x1dc0)
+              { itype = M32RXF_INSN_JNC; goto extract_sfmt_jc; }
+            itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0xfff0) == 0x1ec0)
+              { itype = M32RXF_INSN_JL; goto extract_sfmt_jl; }
+            itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 3 :
+            if ((entire_insn & 0xfff0) == 0x1fc0)
+              { itype = M32RXF_INSN_JMP; goto extract_sfmt_jmp; }
+            itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
-      case 29 : itype = M32RXF_INSN_RTE; goto extract_sfmt_rte;
-      case 31 : itype = M32RXF_INSN_TRAP; goto extract_sfmt_trap;
+      case 29 :
+        if ((entire_insn & 0xffff) == 0x10d6)
+          { itype = M32RXF_INSN_RTE; goto extract_sfmt_rte; }
+        itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 31 :
+        if ((entire_insn & 0xfff0) == 0x10f0)
+          { itype = M32RXF_INSN_TRAP; goto extract_sfmt_trap; }
+        itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
       case 32 : itype = M32RXF_INSN_STB; goto extract_sfmt_stb;
       case 33 : itype = M32RXF_INSN_STB_PLUS; goto extract_sfmt_stb_plus;
       case 34 : itype = M32RXF_INSN_STH; goto extract_sfmt_sth;
@@ -368,18 +396,33 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 0) & (1 << 0)));
           switch (val)
           {
-          case 0 : itype = M32RXF_INSN_MVTACHI_A; goto extract_sfmt_mvtachi_a;
-          case 1 : itype = M32RXF_INSN_MVTACLO_A; goto extract_sfmt_mvtachi_a;
+          case 0 :
+            if ((entire_insn & 0xf0f3) == 0x5070)
+              { itype = M32RXF_INSN_MVTACHI_A; goto extract_sfmt_mvtachi_a; }
+            itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0xf0f3) == 0x5071)
+              { itype = M32RXF_INSN_MVTACLO_A; goto extract_sfmt_mvtachi_a; }
+            itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
-      case 88 : itype = M32RXF_INSN_RACH_DSI; goto extract_sfmt_rac_dsi;
-      case 89 : itype = M32RXF_INSN_RAC_DSI; goto extract_sfmt_rac_dsi;
+      case 88 :
+        if ((entire_insn & 0xf3f2) == 0x5080)
+          { itype = M32RXF_INSN_RACH_DSI; goto extract_sfmt_rac_dsi; }
+        itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 89 :
+        if ((entire_insn & 0xf3f2) == 0x5090)
+          { itype = M32RXF_INSN_RAC_DSI; goto extract_sfmt_rac_dsi; }
+        itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
       case 90 : itype = M32RXF_INSN_MULWU1; goto extract_sfmt_mulwu1;
       case 91 : itype = M32RXF_INSN_MACWU1; goto extract_sfmt_macwu1;
       case 92 : itype = M32RXF_INSN_MACLH1; goto extract_sfmt_macwu1;
       case 93 : itype = M32RXF_INSN_MSBLO; goto extract_sfmt_msblo;
-      case 94 : itype = M32RXF_INSN_SADD; goto extract_sfmt_sadd;
+      case 94 :
+        if ((entire_insn & 0xffff) == 0x50e4)
+          { itype = M32RXF_INSN_SADD; goto extract_sfmt_sadd; }
+        itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
       case 95 :
         {
           unsigned int val = (((insn >> 0) & (3 << 0)));
@@ -412,13 +455,22 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 7) & (15 << 1)) | ((insn >> 0) & (1 << 0)));
           switch (val)
           {
-          case 0 : itype = M32RXF_INSN_NOP; goto extract_sfmt_nop;
+          case 0 :
+            if ((entire_insn & 0xffff) == 0x7000)
+              { itype = M32RXF_INSN_NOP; goto extract_sfmt_nop; }
+            itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
           case 2 : /* fall through */
           case 3 : itype = M32RXF_INSN_SETPSW; goto extract_sfmt_setpsw;
           case 4 : /* fall through */
           case 5 : itype = M32RXF_INSN_CLRPSW; goto extract_sfmt_clrpsw;
-          case 9 : itype = M32RXF_INSN_SC; goto extract_sfmt_sc;
-          case 11 : itype = M32RXF_INSN_SNC; goto extract_sfmt_sc;
+          case 9 :
+            if ((entire_insn & 0xffff) == 0x7401)
+              { itype = M32RXF_INSN_SC; goto extract_sfmt_sc; }
+            itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 11 :
+            if ((entire_insn & 0xffff) == 0x7501)
+              { itype = M32RXF_INSN_SNC; goto extract_sfmt_sc; }
+            itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
           case 16 : /* fall through */
           case 17 : itype = M32RXF_INSN_BCL8; goto extract_sfmt_bcl8;
           case 18 : /* fall through */
@@ -464,16 +516,31 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
           default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
-      case 132 : itype = M32RXF_INSN_CMPI; goto extract_sfmt_cmpi;
-      case 133 : itype = M32RXF_INSN_CMPUI; goto extract_sfmt_cmpi;
+      case 132 :
+        if ((entire_insn & 0xfff00000) == 0x80400000)
+          { itype = M32RXF_INSN_CMPI; goto extract_sfmt_cmpi; }
+        itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 133 :
+        if ((entire_insn & 0xfff00000) == 0x80500000)
+          { itype = M32RXF_INSN_CMPUI; goto extract_sfmt_cmpi; }
+        itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
       case 134 :
         {
-          unsigned int val = (((insn >> -8) & (3 << 0)));
+          unsigned int val = (((entire_insn >> 8) & (3 << 0)));
           switch (val)
           {
-          case 0 : itype = M32RXF_INSN_SAT; goto extract_sfmt_sat;
-          case 2 : itype = M32RXF_INSN_SATH; goto extract_sfmt_satb;
-          case 3 : itype = M32RXF_INSN_SATB; goto extract_sfmt_satb;
+          case 0 :
+            if ((entire_insn & 0xf0f0ffff) == 0x80600000)
+              { itype = M32RXF_INSN_SAT; goto extract_sfmt_sat; }
+            itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 2 :
+            if ((entire_insn & 0xf0f0ffff) == 0x80600200)
+              { itype = M32RXF_INSN_SATH; goto extract_sfmt_satb; }
+            itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 3 :
+            if ((entire_insn & 0xf0f0ffff) == 0x80600300)
+              { itype = M32RXF_INSN_SATB; goto extract_sfmt_satb; }
+            itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -484,26 +551,50 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
       case 142 : itype = M32RXF_INSN_OR3; goto extract_sfmt_or3;
       case 144 :
         {
-          unsigned int val = (((insn >> -12) & (1 << 0)));
+          unsigned int val = (((entire_insn >> 4) & (1 << 0)));
           switch (val)
           {
-          case 0 : itype = M32RXF_INSN_DIV; goto extract_sfmt_div;
-          case 1 : itype = M32RXF_INSN_DIVH; goto extract_sfmt_div;
+          case 0 :
+            if ((entire_insn & 0xf0f0ffff) == 0x90000000)
+              { itype = M32RXF_INSN_DIV; goto extract_sfmt_div; }
+            itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0xf0f0ffff) == 0x90000010)
+              { itype = M32RXF_INSN_DIVH; goto extract_sfmt_div; }
+            itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
-      case 145 : itype = M32RXF_INSN_DIVU; goto extract_sfmt_div;
-      case 146 : itype = M32RXF_INSN_REM; goto extract_sfmt_div;
-      case 147 : itype = M32RXF_INSN_REMU; goto extract_sfmt_div;
+      case 145 :
+        if ((entire_insn & 0xf0f0ffff) == 0x90100000)
+          { itype = M32RXF_INSN_DIVU; goto extract_sfmt_div; }
+        itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 146 :
+        if ((entire_insn & 0xf0f0ffff) == 0x90200000)
+          { itype = M32RXF_INSN_REM; goto extract_sfmt_div; }
+        itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 147 :
+        if ((entire_insn & 0xf0f0ffff) == 0x90300000)
+          { itype = M32RXF_INSN_REMU; goto extract_sfmt_div; }
+        itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
       case 152 : itype = M32RXF_INSN_SRL3; goto extract_sfmt_sll3;
       case 154 : itype = M32RXF_INSN_SRA3; goto extract_sfmt_sll3;
       case 156 : itype = M32RXF_INSN_SLL3; goto extract_sfmt_sll3;
-      case 159 : itype = M32RXF_INSN_LDI16; goto extract_sfmt_ldi16;
+      case 159 :
+        if ((entire_insn & 0xf0ff0000) == 0x90f00000)
+          { itype = M32RXF_INSN_LDI16; goto extract_sfmt_ldi16; }
+        itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
       case 160 : itype = M32RXF_INSN_STB_D; goto extract_sfmt_stb_d;
       case 162 : itype = M32RXF_INSN_STH_D; goto extract_sfmt_sth_d;
       case 164 : itype = M32RXF_INSN_ST_D; goto extract_sfmt_st_d;
-      case 166 : itype = M32RXF_INSN_BSET; goto extract_sfmt_bset;
-      case 167 : itype = M32RXF_INSN_BCLR; goto extract_sfmt_bset;
+      case 166 :
+        if ((entire_insn & 0xf8f00000) == 0xa0600000)
+          { itype = M32RXF_INSN_BSET; goto extract_sfmt_bset; }
+        itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 167 :
+        if ((entire_insn & 0xf8f00000) == 0xa0700000)
+          { itype = M32RXF_INSN_BCLR; goto extract_sfmt_bset; }
+        itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
       case 168 : itype = M32RXF_INSN_LDB_D; goto extract_sfmt_ldb_d;
       case 169 : itype = M32RXF_INSN_LDUB_D; goto extract_sfmt_ldb_d;
       case 170 : itype = M32RXF_INSN_LDH_D; goto extract_sfmt_ldh_d;
@@ -511,13 +602,34 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
       case 172 : itype = M32RXF_INSN_LD_D; goto extract_sfmt_ld_d;
       case 176 : itype = M32RXF_INSN_BEQ; goto extract_sfmt_beq;
       case 177 : itype = M32RXF_INSN_BNE; goto extract_sfmt_beq;
-      case 184 : itype = M32RXF_INSN_BEQZ; goto extract_sfmt_beqz;
-      case 185 : itype = M32RXF_INSN_BNEZ; goto extract_sfmt_beqz;
-      case 186 : itype = M32RXF_INSN_BLTZ; goto extract_sfmt_beqz;
-      case 187 : itype = M32RXF_INSN_BGEZ; goto extract_sfmt_beqz;
-      case 188 : itype = M32RXF_INSN_BLEZ; goto extract_sfmt_beqz;
-      case 189 : itype = M32RXF_INSN_BGTZ; goto extract_sfmt_beqz;
-      case 220 : itype = M32RXF_INSN_SETH; goto extract_sfmt_seth;
+      case 184 :
+        if ((entire_insn & 0xfff00000) == 0xb0800000)
+          { itype = M32RXF_INSN_BEQZ; goto extract_sfmt_beqz; }
+        itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 185 :
+        if ((entire_insn & 0xfff00000) == 0xb0900000)
+          { itype = M32RXF_INSN_BNEZ; goto extract_sfmt_beqz; }
+        itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 186 :
+        if ((entire_insn & 0xfff00000) == 0xb0a00000)
+          { itype = M32RXF_INSN_BLTZ; goto extract_sfmt_beqz; }
+        itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 187 :
+        if ((entire_insn & 0xfff00000) == 0xb0b00000)
+          { itype = M32RXF_INSN_BGEZ; goto extract_sfmt_beqz; }
+        itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 188 :
+        if ((entire_insn & 0xfff00000) == 0xb0c00000)
+          { itype = M32RXF_INSN_BLEZ; goto extract_sfmt_beqz; }
+        itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 189 :
+        if ((entire_insn & 0xfff00000) == 0xb0d00000)
+          { itype = M32RXF_INSN_BGTZ; goto extract_sfmt_beqz; }
+        itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+      case 220 :
+        if ((entire_insn & 0xf0ff0000) == 0xd0c00000)
+          { itype = M32RXF_INSN_SETH; goto extract_sfmt_seth; }
+        itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
       case 224 : /* fall through */
       case 225 : /* fall through */
       case 226 : /* fall through */
@@ -554,12 +666,30 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
           unsigned int val = (((insn >> 8) & (7 << 0)));
           switch (val)
           {
-          case 0 : itype = M32RXF_INSN_BCL24; goto extract_sfmt_bcl24;
-          case 1 : itype = M32RXF_INSN_BNCL24; goto extract_sfmt_bcl24;
-          case 4 : itype = M32RXF_INSN_BC24; goto extract_sfmt_bc24;
-          case 5 : itype = M32RXF_INSN_BNC24; goto extract_sfmt_bc24;
-          case 6 : itype = M32RXF_INSN_BL24; goto extract_sfmt_bl24;
-          case 7 : itype = M32RXF_INSN_BRA24; goto extract_sfmt_bra24;
+          case 0 :
+            if ((entire_insn & 0xff000000) == 0xf8000000)
+              { itype = M32RXF_INSN_BCL24; goto extract_sfmt_bcl24; }
+            itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 1 :
+            if ((entire_insn & 0xff000000) == 0xf9000000)
+              { itype = M32RXF_INSN_BNCL24; goto extract_sfmt_bcl24; }
+            itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 4 :
+            if ((entire_insn & 0xff000000) == 0xfc000000)
+              { itype = M32RXF_INSN_BC24; goto extract_sfmt_bc24; }
+            itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 5 :
+            if ((entire_insn & 0xff000000) == 0xfd000000)
+              { itype = M32RXF_INSN_BNC24; goto extract_sfmt_bc24; }
+            itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 6 :
+            if ((entire_insn & 0xff000000) == 0xfe000000)
+              { itype = M32RXF_INSN_BL24; goto extract_sfmt_bl24; }
+            itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
+          case 7 :
+            if ((entire_insn & 0xff000000) == 0xff000000)
+              { itype = M32RXF_INSN_BRA24; goto extract_sfmt_bra24; }
+            itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
           default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
           }
         }
@@ -573,11 +703,11 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_empty:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-#define FLD(f) abuf->fields.fmt_empty.f
+#define FLD(f) abuf->fields.sfmt_empty.f
 
 
   /* Record the fields for the semantic handler.  */
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *) 0));
 
 #undef FLD
     return idesc;
@@ -586,7 +716,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_add:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_add.f
     UINT f_r1;
     UINT f_r2;
@@ -599,7 +729,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   FLD (f_r2) = f_r2;
   FLD (i_dr) = & CPU (h_gr)[f_r1];
   FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -617,7 +747,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_add3:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_add3.f
     UINT f_r1;
     UINT f_r2;
@@ -625,7 +755,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
 
     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
+    f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16);
 
   /* Record the fields for the semantic handler.  */
   FLD (f_simm16) = f_simm16;
@@ -633,7 +763,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   FLD (f_r1) = f_r1;
   FLD (i_sr) = & CPU (h_gr)[f_r2];
   FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -650,7 +780,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_and3:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_and3.f
     UINT f_r1;
     UINT f_r2;
@@ -666,7 +796,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   FLD (f_r1) = f_r1;
   FLD (i_sr) = & CPU (h_gr)[f_r2];
   FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and3", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and3", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -683,7 +813,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_or3:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_and3.f
     UINT f_r1;
     UINT f_r2;
@@ -699,7 +829,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   FLD (f_r1) = f_r1;
   FLD (i_sr) = & CPU (h_gr)[f_r2];
   FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_or3", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_or3", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -716,19 +846,19 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_addi:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_addi.f
     UINT f_r1;
     INT f_simm8;
 
     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8);
+    f_simm8 = EXTRACT_MSB0_SINT (insn, 16, 8, 8);
 
   /* Record the fields for the semantic handler.  */
   FLD (f_r1) = f_r1;
   FLD (f_simm8) = f_simm8;
   FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addi", "f_r1 0x%x", 'x', f_r1, "f_simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addi", "f_r1 0x%x", 'x', f_r1, "f_simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -745,7 +875,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_addv:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_add.f
     UINT f_r1;
     UINT f_r2;
@@ -758,7 +888,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   FLD (f_r2) = f_r2;
   FLD (i_dr) = & CPU (h_gr)[f_r1];
   FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -776,7 +906,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_addv3:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_add3.f
     UINT f_r1;
     UINT f_r2;
@@ -784,7 +914,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
 
     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
+    f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16);
 
   /* Record the fields for the semantic handler.  */
   FLD (f_simm16) = f_simm16;
@@ -792,7 +922,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   FLD (f_r1) = f_r1;
   FLD (i_sr) = & CPU (h_gr)[f_r2];
   FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -809,7 +939,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_addx:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_add.f
     UINT f_r1;
     UINT f_r2;
@@ -822,7 +952,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   FLD (f_r2) = f_r2;
   FLD (i_dr) = & CPU (h_gr)[f_r1];
   FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addx", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addx", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -840,15 +970,15 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_bc8:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_bl8.f
     SI f_disp8;
 
-    f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
+    f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
 
   /* Record the fields for the semantic handler.  */
   FLD (i_disp8) = f_disp8;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -863,15 +993,15 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_bc24:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_bl24.f
     SI f_disp24;
 
-    f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));
+    f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc));
 
   /* Record the fields for the semantic handler.  */
   FLD (i_disp24) = f_disp24;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -886,7 +1016,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_beq:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_beq.f
     UINT f_r1;
     UINT f_r2;
@@ -894,7 +1024,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
 
     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc));
+    f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc));
 
   /* Record the fields for the semantic handler.  */
   FLD (f_r1) = f_r1;
@@ -902,7 +1032,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   FLD (i_disp16) = f_disp16;
   FLD (i_src1) = & CPU (h_gr)[f_r1];
   FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beq", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beq", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -919,19 +1049,19 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_beqz:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_beq.f
     UINT f_r2;
     SI f_disp16;
 
     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc));
+    f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc));
 
   /* Record the fields for the semantic handler.  */
   FLD (f_r2) = f_r2;
   FLD (i_disp16) = f_disp16;
   FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beqz", "f_r2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, "src2 0x%x", 'x', f_r2, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beqz", "f_r2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, "src2 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -947,15 +1077,15 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_bl8:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_bl8.f
     SI f_disp8;
 
-    f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
+    f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
 
   /* Record the fields for the semantic handler.  */
   FLD (i_disp8) = f_disp8;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -971,15 +1101,15 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_bl24:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_bl24.f
     SI f_disp24;
 
-    f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));
+    f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc));
 
   /* Record the fields for the semantic handler.  */
   FLD (i_disp24) = f_disp24;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -995,15 +1125,15 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_bcl8:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_bl8.f
     SI f_disp8;
 
-    f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
+    f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
 
   /* Record the fields for the semantic handler.  */
   FLD (i_disp8) = f_disp8;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcl8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcl8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1019,15 +1149,15 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_bcl24:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_bl24.f
     SI f_disp24;
 
-    f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));
+    f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc));
 
   /* Record the fields for the semantic handler.  */
   FLD (i_disp24) = f_disp24;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcl24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcl24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1043,15 +1173,15 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_bra8:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_bl8.f
     SI f_disp8;
 
-    f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
+    f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
 
   /* Record the fields for the semantic handler.  */
   FLD (i_disp8) = f_disp8;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1066,15 +1196,15 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_bra24:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_bl24.f
     SI f_disp24;
 
-    f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));
+    f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc));
 
   /* Record the fields for the semantic handler.  */
   FLD (i_disp24) = f_disp24;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1089,7 +1219,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_cmp:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_st_plus.f
     UINT f_r1;
     UINT f_r2;
@@ -1102,7 +1232,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   FLD (f_r2) = f_r2;
   FLD (i_src1) = & CPU (h_gr)[f_r1];
   FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1119,19 +1249,19 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_cmpi:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_st_d.f
     UINT f_r2;
     INT f_simm16;
 
     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
+    f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16);
 
   /* Record the fields for the semantic handler.  */
   FLD (f_simm16) = f_simm16;
   FLD (f_r2) = f_r2;
   FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpi", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "src2 0x%x", 'x', f_r2, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpi", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "src2 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1147,7 +1277,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_cmpz:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_st_plus.f
     UINT f_r2;
 
@@ -1156,7 +1286,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   /* Record the fields for the semantic handler.  */
   FLD (f_r2) = f_r2;
   FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpz", "f_r2 0x%x", 'x', f_r2, "src2 0x%x", 'x', f_r2, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpz", "f_r2 0x%x", 'x', f_r2, "src2 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1172,7 +1302,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_div:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_add.f
     UINT f_r1;
     UINT f_r2;
@@ -1185,7 +1315,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   FLD (f_r2) = f_r2;
   FLD (i_dr) = & CPU (h_gr)[f_r1];
   FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_div", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_div", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1203,7 +1333,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_jc:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_jl.f
     UINT f_r2;
 
@@ -1212,7 +1342,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   /* Record the fields for the semantic handler.  */
   FLD (f_r2) = f_r2;
   FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jc", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jc", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1228,7 +1358,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_jl:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_jl.f
     UINT f_r2;
 
@@ -1237,7 +1367,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   /* Record the fields for the semantic handler.  */
   FLD (f_r2) = f_r2;
   FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1254,7 +1384,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_jmp:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_jl.f
     UINT f_r2;
 
@@ -1263,7 +1393,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   /* Record the fields for the semantic handler.  */
   FLD (f_r2) = f_r2;
   FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jmp", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jmp", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1279,7 +1409,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_ld:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_ld_plus.f
     UINT f_r1;
     UINT f_r2;
@@ -1292,7 +1422,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   FLD (f_r1) = f_r1;
   FLD (i_sr) = & CPU (h_gr)[f_r2];
   FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1309,7 +1439,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_ld_d:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_add3.f
     UINT f_r1;
     UINT f_r2;
@@ -1317,7 +1447,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
 
     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
+    f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16);
 
   /* Record the fields for the semantic handler.  */
   FLD (f_simm16) = f_simm16;
@@ -1325,7 +1455,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   FLD (f_r1) = f_r1;
   FLD (i_sr) = & CPU (h_gr)[f_r2];
   FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1342,7 +1472,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_ldb:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_ld_plus.f
     UINT f_r1;
     UINT f_r2;
@@ -1355,7 +1485,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   FLD (f_r1) = f_r1;
   FLD (i_sr) = & CPU (h_gr)[f_r2];
   FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1372,7 +1502,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_ldb_d:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_add3.f
     UINT f_r1;
     UINT f_r2;
@@ -1380,7 +1510,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
 
     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
+    f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16);
 
   /* Record the fields for the semantic handler.  */
   FLD (f_simm16) = f_simm16;
@@ -1388,7 +1518,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   FLD (f_r1) = f_r1;
   FLD (i_sr) = & CPU (h_gr)[f_r2];
   FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1405,7 +1535,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_ldh:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_ld_plus.f
     UINT f_r1;
     UINT f_r2;
@@ -1418,7 +1548,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   FLD (f_r1) = f_r1;
   FLD (i_sr) = & CPU (h_gr)[f_r2];
   FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldh", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldh", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1435,7 +1565,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_ldh_d:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_add3.f
     UINT f_r1;
     UINT f_r2;
@@ -1443,7 +1573,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
 
     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
+    f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16);
 
   /* Record the fields for the semantic handler.  */
   FLD (f_simm16) = f_simm16;
@@ -1451,7 +1581,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   FLD (f_r1) = f_r1;
   FLD (i_sr) = & CPU (h_gr)[f_r2];
   FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldh_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldh_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1468,7 +1598,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_ld_plus:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_ld_plus.f
     UINT f_r1;
     UINT f_r2;
@@ -1481,7 +1611,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   FLD (f_r1) = f_r1;
   FLD (i_sr) = & CPU (h_gr)[f_r2];
   FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_plus", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_plus", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1499,7 +1629,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_ld24:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_ld24.f
     UINT f_r1;
     UINT f_uimm24;
@@ -1511,7 +1641,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   FLD (f_r1) = f_r1;
   FLD (i_uimm24) = f_uimm24;
   FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld24", "f_r1 0x%x", 'x', f_r1, "uimm24 0x%x", 'x', f_uimm24, "dr 0x%x", 'x', f_r1, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld24", "f_r1 0x%x", 'x', f_r1, "uimm24 0x%x", 'x', f_uimm24, "dr 0x%x", 'x', f_r1, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1527,19 +1657,19 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_ldi8:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_addi.f
     UINT f_r1;
     INT f_simm8;
 
     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
-    f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8);
+    f_simm8 = EXTRACT_MSB0_SINT (insn, 16, 8, 8);
 
   /* Record the fields for the semantic handler.  */
   FLD (f_simm8) = f_simm8;
   FLD (f_r1) = f_r1;
   FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi8", "f_simm8 0x%x", 'x', f_simm8, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi8", "f_simm8 0x%x", 'x', f_simm8, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1555,19 +1685,19 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_ldi16:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_add3.f
     UINT f_r1;
     INT f_simm16;
 
     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
-    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
+    f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16);
 
   /* Record the fields for the semantic handler.  */
   FLD (f_simm16) = f_simm16;
   FLD (f_r1) = f_r1;
   FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi16", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi16", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1583,7 +1713,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_lock:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_ld_plus.f
     UINT f_r1;
     UINT f_r2;
@@ -1596,7 +1726,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   FLD (f_r1) = f_r1;
   FLD (i_sr) = & CPU (h_gr)[f_r2];
   FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lock", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lock", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1613,7 +1743,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_machi_a:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_machi_a.f
     UINT f_r1;
     UINT f_acc;
@@ -1629,7 +1759,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   FLD (f_r2) = f_r2;
   FLD (i_src1) = & CPU (h_gr)[f_r1];
   FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_machi_a", "f_acc 0x%x", 'x', f_acc, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_machi_a", "f_acc 0x%x", 'x', f_acc, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1646,7 +1776,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_mulhi_a:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_machi_a.f
     UINT f_r1;
     UINT f_acc;
@@ -1662,7 +1792,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   FLD (f_acc) = f_acc;
   FLD (i_src1) = & CPU (h_gr)[f_r1];
   FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulhi_a", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "f_acc 0x%x", 'x', f_acc, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulhi_a", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "f_acc 0x%x", 'x', f_acc, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1679,7 +1809,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_mv:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_ld_plus.f
     UINT f_r1;
     UINT f_r2;
@@ -1692,7 +1822,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   FLD (f_r1) = f_r1;
   FLD (i_sr) = & CPU (h_gr)[f_r2];
   FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mv", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mv", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1709,7 +1839,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_mvfachi_a:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_mvfachi_a.f
     UINT f_r1;
     UINT f_accs;
@@ -1721,7 +1851,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   FLD (f_accs) = f_accs;
   FLD (f_r1) = f_r1;
   FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfachi_a", "f_accs 0x%x", 'x', f_accs, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfachi_a", "f_accs 0x%x", 'x', f_accs, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1737,7 +1867,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_mvfc:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_ld_plus.f
     UINT f_r1;
     UINT f_r2;
@@ -1749,7 +1879,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   FLD (f_r2) = f_r2;
   FLD (f_r1) = f_r1;
   FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfc", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfc", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1765,7 +1895,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_mvtachi_a:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_mvtachi_a.f
     UINT f_r1;
     UINT f_accs;
@@ -1777,7 +1907,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   FLD (f_accs) = f_accs;
   FLD (f_r1) = f_r1;
   FLD (i_src1) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtachi_a", "f_accs 0x%x", 'x', f_accs, "f_r1 0x%x", 'x', f_r1, "src1 0x%x", 'x', f_r1, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtachi_a", "f_accs 0x%x", 'x', f_accs, "f_r1 0x%x", 'x', f_r1, "src1 0x%x", 'x', f_r1, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1793,7 +1923,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_mvtc:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_ld_plus.f
     UINT f_r1;
     UINT f_r2;
@@ -1805,7 +1935,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   FLD (f_r2) = f_r2;
   FLD (f_r1) = f_r1;
   FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtc", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtc", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1821,11 +1951,11 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_nop:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-#define FLD(f) abuf->fields.fmt_empty.f
+#define FLD(f) abuf->fields.sfmt_empty.f
 
 
   /* Record the fields for the semantic handler.  */
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nop", (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nop", (char *) 0));
 
 #undef FLD
     return idesc;
@@ -1834,7 +1964,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_rac_dsi:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_rac_dsi.f
     UINT f_accd;
     UINT f_accs;
@@ -1848,7 +1978,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   FLD (f_accs) = f_accs;
   FLD (f_imm1) = f_imm1;
   FLD (f_accd) = f_accd;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rac_dsi", "f_accs 0x%x", 'x', f_accs, "f_imm1 0x%x", 'x', f_imm1, "f_accd 0x%x", 'x', f_accd, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rac_dsi", "f_accs 0x%x", 'x', f_accs, "f_imm1 0x%x", 'x', f_imm1, "f_accd 0x%x", 'x', f_accd, (char *) 0));
 
 #undef FLD
     return idesc;
@@ -1857,11 +1987,11 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_rte:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-#define FLD(f) abuf->fields.fmt_empty.f
+#define FLD(f) abuf->fields.sfmt_empty.f
 
 
   /* Record the fields for the semantic handler.  */
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rte", (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rte", (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1876,7 +2006,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_seth:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_seth.f
     UINT f_r1;
     UINT f_hi16;
@@ -1888,7 +2018,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   FLD (f_hi16) = f_hi16;
   FLD (f_r1) = f_r1;
   FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_seth", "f_hi16 0x%x", 'x', f_hi16, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_seth", "f_hi16 0x%x", 'x', f_hi16, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1904,7 +2034,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_sll3:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_add3.f
     UINT f_r1;
     UINT f_r2;
@@ -1912,7 +2042,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
 
     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
+    f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16);
 
   /* Record the fields for the semantic handler.  */
   FLD (f_simm16) = f_simm16;
@@ -1920,7 +2050,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   FLD (f_r1) = f_r1;
   FLD (i_sr) = & CPU (h_gr)[f_r2];
   FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sll3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sll3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1937,7 +2067,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_slli:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_slli.f
     UINT f_r1;
     UINT f_uimm5;
@@ -1949,7 +2079,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   FLD (f_r1) = f_r1;
   FLD (f_uimm5) = f_uimm5;
   FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_slli", "f_r1 0x%x", 'x', f_r1, "f_uimm5 0x%x", 'x', f_uimm5, "dr 0x%x", 'x', f_r1, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_slli", "f_r1 0x%x", 'x', f_r1, "f_uimm5 0x%x", 'x', f_uimm5, "dr 0x%x", 'x', f_r1, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1966,7 +2096,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_st:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_st_plus.f
     UINT f_r1;
     UINT f_r2;
@@ -1979,7 +2109,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   FLD (f_r2) = f_r2;
   FLD (i_src1) = & CPU (h_gr)[f_r1];
   FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -1996,7 +2126,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_st_d:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_st_d.f
     UINT f_r1;
     UINT f_r2;
@@ -2004,7 +2134,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
 
     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
+    f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16);
 
   /* Record the fields for the semantic handler.  */
   FLD (f_simm16) = f_simm16;
@@ -2012,7 +2142,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   FLD (f_r2) = f_r2;
   FLD (i_src1) = & CPU (h_gr)[f_r1];
   FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -2029,7 +2159,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_stb:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_st_plus.f
     UINT f_r1;
     UINT f_r2;
@@ -2042,7 +2172,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   FLD (f_r2) = f_r2;
   FLD (i_src1) = & CPU (h_gr)[f_r1];
   FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -2059,7 +2189,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_stb_d:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_st_d.f
     UINT f_r1;
     UINT f_r2;
@@ -2067,7 +2197,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
 
     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
+    f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16);
 
   /* Record the fields for the semantic handler.  */
   FLD (f_simm16) = f_simm16;
@@ -2075,7 +2205,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   FLD (f_r2) = f_r2;
   FLD (i_src1) = & CPU (h_gr)[f_r1];
   FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -2092,7 +2222,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_sth:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_st_plus.f
     UINT f_r1;
     UINT f_r2;
@@ -2105,7 +2235,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   FLD (f_r2) = f_r2;
   FLD (i_src1) = & CPU (h_gr)[f_r1];
   FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -2122,7 +2252,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_sth_d:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_st_d.f
     UINT f_r1;
     UINT f_r2;
@@ -2130,7 +2260,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
 
     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
+    f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16);
 
   /* Record the fields for the semantic handler.  */
   FLD (f_simm16) = f_simm16;
@@ -2138,7 +2268,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   FLD (f_r2) = f_r2;
   FLD (i_src1) = & CPU (h_gr)[f_r1];
   FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -2155,7 +2285,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_st_plus:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_st_plus.f
     UINT f_r1;
     UINT f_r2;
@@ -2168,7 +2298,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   FLD (f_r2) = f_r2;
   FLD (i_src1) = & CPU (h_gr)[f_r1];
   FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -2186,7 +2316,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_sth_plus:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_st_plus.f
     UINT f_r1;
     UINT f_r2;
@@ -2199,7 +2329,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   FLD (f_r2) = f_r2;
   FLD (i_src1) = & CPU (h_gr)[f_r1];
   FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -2217,7 +2347,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_stb_plus:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_st_plus.f
     UINT f_r1;
     UINT f_r2;
@@ -2230,7 +2360,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   FLD (f_r2) = f_r2;
   FLD (i_src1) = & CPU (h_gr)[f_r1];
   FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -2248,7 +2378,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_trap:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_trap.f
     UINT f_uimm4;
 
@@ -2256,7 +2386,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
 
   /* Record the fields for the semantic handler.  */
   FLD (f_uimm4) = f_uimm4;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_trap", "f_uimm4 0x%x", 'x', f_uimm4, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_trap", "f_uimm4 0x%x", 'x', f_uimm4, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -2271,7 +2401,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_unlock:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_st_plus.f
     UINT f_r1;
     UINT f_r2;
@@ -2284,7 +2414,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   FLD (f_r2) = f_r2;
   FLD (i_src1) = & CPU (h_gr)[f_r1];
   FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_unlock", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_unlock", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -2301,7 +2431,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_satb:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_ld_plus.f
     UINT f_r1;
     UINT f_r2;
@@ -2314,7 +2444,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   FLD (f_r1) = f_r1;
   FLD (i_sr) = & CPU (h_gr)[f_r2];
   FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_satb", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_satb", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -2331,7 +2461,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_sat:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_ld_plus.f
     UINT f_r1;
     UINT f_r2;
@@ -2344,7 +2474,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   FLD (f_r1) = f_r1;
   FLD (i_sr) = & CPU (h_gr)[f_r2];
   FLD (i_dr) = & CPU (h_gr)[f_r1];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sat", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sat", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -2361,11 +2491,11 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_sadd:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-#define FLD(f) abuf->fields.fmt_empty.f
+#define FLD(f) abuf->fields.sfmt_empty.f
 
 
   /* Record the fields for the semantic handler.  */
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sadd", (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sadd", (char *) 0));
 
 #undef FLD
     return idesc;
@@ -2374,7 +2504,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_macwu1:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_st_plus.f
     UINT f_r1;
     UINT f_r2;
@@ -2387,7 +2517,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   FLD (f_r2) = f_r2;
   FLD (i_src1) = & CPU (h_gr)[f_r1];
   FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_macwu1", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_macwu1", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -2404,7 +2534,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_msblo:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_st_plus.f
     UINT f_r1;
     UINT f_r2;
@@ -2417,7 +2547,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   FLD (f_r2) = f_r2;
   FLD (i_src1) = & CPU (h_gr)[f_r1];
   FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_msblo", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_msblo", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -2434,7 +2564,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_mulwu1:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_st_plus.f
     UINT f_r1;
     UINT f_r2;
@@ -2447,7 +2577,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   FLD (f_r2) = f_r2;
   FLD (i_src1) = & CPU (h_gr)[f_r1];
   FLD (i_src2) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulwu1", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulwu1", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -2464,11 +2594,11 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_sc:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-#define FLD(f) abuf->fields.fmt_empty.f
+#define FLD(f) abuf->fields.sfmt_empty.f
 
 
   /* Record the fields for the semantic handler.  */
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sc", (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sc", (char *) 0));
 
 #undef FLD
     return idesc;
@@ -2477,7 +2607,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_clrpsw:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_clrpsw.f
     UINT f_uimm8;
 
@@ -2485,7 +2615,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
 
   /* Record the fields for the semantic handler.  */
   FLD (f_uimm8) = f_uimm8;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_clrpsw", "f_uimm8 0x%x", 'x', f_uimm8, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_clrpsw", "f_uimm8 0x%x", 'x', f_uimm8, (char *) 0));
 
 #undef FLD
     return idesc;
@@ -2494,7 +2624,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_setpsw:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_clrpsw.f
     UINT f_uimm8;
 
@@ -2502,7 +2632,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
 
   /* Record the fields for the semantic handler.  */
   FLD (f_uimm8) = f_uimm8;
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_setpsw", "f_uimm8 0x%x", 'x', f_uimm8, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_setpsw", "f_uimm8 0x%x", 'x', f_uimm8, (char *) 0));
 
 #undef FLD
     return idesc;
@@ -2511,7 +2641,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_bset:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_bset.f
     UINT f_uimm3;
     UINT f_r2;
@@ -2519,14 +2649,14 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
 
     f_uimm3 = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
-    f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
+    f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16);
 
   /* Record the fields for the semantic handler.  */
   FLD (f_simm16) = f_simm16;
   FLD (f_r2) = f_r2;
   FLD (f_uimm3) = f_uimm3;
   FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bset", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_uimm3 0x%x", 'x', f_uimm3, "sr 0x%x", 'x', f_r2, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bset", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_uimm3 0x%x", 'x', f_uimm3, "sr 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */
@@ -2542,7 +2672,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_btst:
   {
     const IDESC *idesc = &m32rxf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_bset.f
     UINT f_uimm3;
     UINT f_r2;
@@ -2554,7 +2684,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
   FLD (f_r2) = f_r2;
   FLD (f_uimm3) = f_uimm3;
   FLD (i_sr) = & CPU (h_gr)[f_r2];
-  TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_btst", "f_r2 0x%x", 'x', f_r2, "f_uimm3 0x%x", 'x', f_uimm3, "sr 0x%x", 'x', f_r2, (char *) 0));
+  CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_btst", "f_r2 0x%x", 'x', f_r2, "f_uimm3 0x%x", 'x', f_uimm3, "sr 0x%x", 'x', f_r2, (char *) 0));
 
 #if WITH_PROFILE_MODEL_P
   /* Record the fields for profiling.  */