ubsan: nds32: left shift cannot be represented in type 'int'

[deliverable/binutils-gdb.git] / sim / m32r / mloop.in

diff --git a/sim/m32r/mloop.in b/sim/m32r/mloop.in
index 15ad34b5a69e367c86c7e5a8afb90b36aecd003d..477458c785a1756a17ac3e482c1149bf4ede92ba 100644 (file)
--- a/sim/m32r/mloop.in
+++ b/sim/m32r/mloop.in
@@ -1,6 +1,6 @@
 # Simulator main loop for m32r. -*- C -*-
 #
-# Copyright (C) 1996-1998, 2007-2012 Free Software Foundation, Inc.
+# Copyright (C) 1996-2019 Free Software Foundation, Inc.
 #
 # This file is part of the GNU Simulators.
 #
@@ -113,8 +113,8 @@ execute (SIM_CPU *current_cpu, SCACHE *sc, int fast_p)
          if (PROFILE_MODEL_P (current_cpu)
              && ARGBUF_PROFILE_P (abuf))
            @cpu@_model_insn_before (current_cpu, 1 /*first_p*/);
-         TRACE_INSN_INIT (current_cpu, abuf, 1);
-         TRACE_INSN (current_cpu, idata,
+         CGEN_TRACE_INSN_INIT (current_cpu, abuf, 1);
+         CGEN_TRACE_INSN (current_cpu, idata,
                      (const struct argbuf *) abuf, abuf->addr);
        }
 #if WITH_SCACHE
@@ -133,7 +133,7 @@ execute (SIM_CPU *current_cpu, SCACHE *sc, int fast_p)
              cycles = (*idesc->timing->model_fn) (current_cpu, sc);
              @cpu@_model_insn_after (current_cpu, 1 /*last_p*/, cycles);
            }
-         TRACE_INSN_FINI (current_cpu, abuf, 1);
+         CGEN_TRACE_INSN_FINI (current_cpu, abuf, 1);
        }
 #else
       abort ();