/* m6811_cpu.c -- 68HC11&68HC12 CPU Emulation
- Copyright 1999, 2000, 2001, 2002, 2003, 2007, 2008, 2009, 2010, 2011
- Free Software Foundation, Inc.
+ Copyright 1999-2020 Free Software Foundation, Inc.
Written by Stephane Carrez (stcarrez@nerim.fr)
This file is part of GDB, GAS, and the GNU binutils.
}
uint16
-cpu_get_reg (sim_cpu* cpu, uint8 reg)
+cpu_get_reg (sim_cpu *cpu, uint8 reg)
{
switch (reg)
{
}
uint16
-cpu_get_src_reg (sim_cpu* cpu, uint8 reg)
+cpu_get_src_reg (sim_cpu *cpu, uint8 reg)
{
switch (reg)
{
}
void
-cpu_set_dst_reg (sim_cpu* cpu, uint8 reg, uint16 val)
+cpu_set_dst_reg (sim_cpu *cpu, uint8 reg, uint16 val)
{
switch (reg)
{
}
void
-cpu_set_reg (sim_cpu* cpu, uint8 reg, uint16 val)
+cpu_set_reg (sim_cpu *cpu, uint8 reg, uint16 val)
{
switch (reg)
{
/* Returns the address of a 68HC12 indexed operand.
Pre and post modifications are handled on the source register. */
uint16
-cpu_get_indexed_operand_addr (sim_cpu* cpu, int restrict)
+cpu_get_indexed_operand_addr (sim_cpu *cpu, int restricted)
{
uint8 reg;
uint16 sval;
/* [n,r] 16-bits offset indexed indirect. */
else if ((code & 0x07) == 3)
{
- if (restrict)
+ if (restricted)
{
return 0;
}
}
else if ((code & 0x4) == 0)
{
- if (restrict)
+ if (restricted)
{
return 0;
}
}
uint8
-cpu_get_indexed_operand8 (sim_cpu* cpu, int restrict)
+cpu_get_indexed_operand8 (sim_cpu *cpu, int restricted)
{
uint16 addr;
- addr = cpu_get_indexed_operand_addr (cpu, restrict);
+ addr = cpu_get_indexed_operand_addr (cpu, restricted);
return memory_read8 (cpu, addr);
}
uint16
-cpu_get_indexed_operand16 (sim_cpu* cpu, int restrict)
+cpu_get_indexed_operand16 (sim_cpu *cpu, int restricted)
{
uint16 addr;
- addr = cpu_get_indexed_operand_addr (cpu, restrict);
+ addr = cpu_get_indexed_operand_addr (cpu, restricted);
return memory_read16 (cpu, addr);
}
}
void
-cpu_ccr_update_tst8 (sim_cpu *proc, uint8 val)
+cpu_ccr_update_tst8 (sim_cpu *cpu, uint8 val)
{
- cpu_set_ccr_V (proc, 0);
- cpu_set_ccr_N (proc, val & 0x80 ? 1 : 0);
- cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
+ cpu_set_ccr_V (cpu, 0);
+ cpu_set_ccr_N (cpu, val & 0x80 ? 1 : 0);
+ cpu_set_ccr_Z (cpu, val == 0 ? 1 : 0);
}
/* Simulation of the dbcc/ibcc/tbcc 68HC12 conditional branch operations. */
void
-cpu_dbcc (sim_cpu* cpu)
+cpu_dbcc (sim_cpu *cpu)
{
uint8 code;
uint16 addr;
}
void
-cpu_exg (sim_cpu* cpu, uint8 code)
+cpu_exg (sim_cpu *cpu, uint8 code)
{
uint8 r1, r2;
uint16 src1;