score formatting

[deliverable/binutils-gdb.git] / sim / m68hc11 / m68hc11_sim.c

diff --git a/sim/m68hc11/m68hc11_sim.c b/sim/m68hc11/m68hc11_sim.c
index fe5985f8f1ccabb1587581079bdaf6c701db691f..143c028d1986f9bf0e2af98bfcd1c278d92c5554 100644 (file)
--- a/sim/m68hc11/m68hc11_sim.c
+++ b/sim/m68hc11/m68hc11_sim.c
@@ -1,22 +1,21 @@
 /* m6811_cpu.c -- 68HC11&68HC12 CPU Emulation
-   Copyright 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+   Copyright 1999-2020 Free Software Foundation, Inc.
    Written by Stephane Carrez (stcarrez@nerim.fr)
 
 This file is part of GDB, GAS, and the GNU binutils.
 
-GDB, GAS, and the GNU binutils are free software; you can redistribute
-them and/or modify them under the terms of the GNU General Public
-License as published by the Free Software Foundation; either version
-1, or (at your option) any later version.
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3 of the License, or
+(at your option) any later version.
 
-GDB, GAS, and the GNU binutils are distributed in the hope that they
-will be useful, but WITHOUT ANY WARRANTY; without even the implied
-warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
-the GNU General Public License for more details.
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
 
 You should have received a copy of the GNU General Public License
-along with this file; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
 
 #include "sim-main.h"
 #include "sim-assert.h"
@@ -27,6 +26,7 @@ enum {
   OPTION_CPU_RESET = OPTION_START,
   OPTION_EMUL_OS,
   OPTION_CPU_CONFIG,
+  OPTION_CPU_BOOTSTRAP,
   OPTION_CPU_MODE
 };
 
@@ -46,6 +46,10 @@ static const OPTION cpu_options[] =
       '\0', NULL, "Specify the initial CPU configuration register",
       cpu_option_handler },
 
+  { {"bootstrap", no_argument, NULL, OPTION_CPU_BOOTSTRAP },
+      '\0', NULL, "Start the processing in bootstrap mode",
+      cpu_option_handler },
+
   { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL }
 };
 
@@ -77,7 +81,11 @@ cpu_option_handler (SIM_DESC sd, sim_cpu *cpu,
       else
         cpu->cpu_use_local_config = 0;
       break;
-      
+
+    case OPTION_CPU_BOOTSTRAP:
+       cpu->cpu_start_mode = "bootstrap";
+       break;
+
     case OPTION_CPU_MODE:
       break;
     }
@@ -106,7 +114,7 @@ cpu_set_sp (sim_cpu *cpu, uint16 val)
 }
 
 uint16
-cpu_get_reg (sim_cpu* cpu, uint8 reg)
+cpu_get_reg (sim_cpu *cpu, uint8 reg)
 {
   switch (reg)
     {
@@ -128,7 +136,7 @@ cpu_get_reg (sim_cpu* cpu, uint8 reg)
 }
 
 uint16
-cpu_get_src_reg (sim_cpu* cpu, uint8 reg)
+cpu_get_src_reg (sim_cpu *cpu, uint8 reg)
 {
   switch (reg)
     {
@@ -162,7 +170,7 @@ cpu_get_src_reg (sim_cpu* cpu, uint8 reg)
 }
 
 void
-cpu_set_dst_reg (sim_cpu* cpu, uint8 reg, uint16 val)
+cpu_set_dst_reg (sim_cpu *cpu, uint8 reg, uint16 val)
 {
   switch (reg)
     {
@@ -204,7 +212,7 @@ cpu_set_dst_reg (sim_cpu* cpu, uint8 reg, uint16 val)
 }
 
 void
-cpu_set_reg (sim_cpu* cpu, uint8 reg, uint16 val)
+cpu_set_reg (sim_cpu *cpu, uint8 reg, uint16 val)
 {
   switch (reg)
     {
@@ -232,7 +240,7 @@ cpu_set_reg (sim_cpu* cpu, uint8 reg, uint16 val)
 /* Returns the address of a 68HC12 indexed operand.
    Pre and post modifications are handled on the source register.  */
 uint16
-cpu_get_indexed_operand_addr (sim_cpu* cpu, int restrict)
+cpu_get_indexed_operand_addr (sim_cpu *cpu, int restricted)
 {
   uint8 reg;
   uint16 sval;
@@ -277,7 +285,7 @@ cpu_get_indexed_operand_addr (sim_cpu* cpu, int restrict)
   /* [n,r] 16-bits offset indexed indirect.  */
   else if ((code & 0x07) == 3)
     {
-      if (restrict)
+      if (restricted)
        {
          return 0;
        }
@@ -289,7 +297,7 @@ cpu_get_indexed_operand_addr (sim_cpu* cpu, int restrict)
     }
   else if ((code & 0x4) == 0)
     {
-      if (restrict)
+      if (restricted)
        {
          return 0;
        }
@@ -337,20 +345,20 @@ cpu_get_indexed_operand_addr (sim_cpu* cpu, int restrict)
 }
 
 uint8
-cpu_get_indexed_operand8 (sim_cpu* cpu, int restrict)
+cpu_get_indexed_operand8 (sim_cpu *cpu, int restricted)
 {
   uint16 addr;
 
-  addr = cpu_get_indexed_operand_addr (cpu, restrict);
+  addr = cpu_get_indexed_operand_addr (cpu, restricted);
   return memory_read8 (cpu, addr);
 }
 
 uint16
-cpu_get_indexed_operand16 (sim_cpu* cpu, int restrict)
+cpu_get_indexed_operand16 (sim_cpu *cpu, int restricted)
 {
   uint16 addr;
 
-  addr = cpu_get_indexed_operand_addr (cpu, restrict);
+  addr = cpu_get_indexed_operand_addr (cpu, restricted);
   return memory_read16 (cpu, addr);
 }
 
@@ -464,6 +472,9 @@ cpu_initialize (SIM_DESC sd, sim_cpu *cpu)
   cpu->cpu_use_elf_start = 0;
   cpu->cpu_elf_start     = 0;
   cpu->cpu_use_local_config = 0;
+  cpu->bank_start = 0;
+  cpu->bank_end   = 0;
+  cpu->bank_shift = 0;
   cpu->cpu_config        = M6811_NOSEC | M6811_NOCOP | M6811_ROMON |
     M6811_EEON;
   interrupts_initialize (sd, cpu);
@@ -582,11 +593,20 @@ print_io_byte (SIM_DESC sd, const char *name, io_reg_desc *desc,
 }
 
 void
-cpu_ccr_update_tst8 (sim_cpu *proc, uint8 val)
+print_io_word (SIM_DESC sd, const char *name, io_reg_desc *desc,
+              uint16 val, uint16 addr)
+{
+  sim_io_printf (sd, "  %-9.9s @ 0x%04x 0x%04x ", name, addr, val);
+  if (desc)
+    print_io_reg_desc (sd, desc, val, 0);
+}
+
+void
+cpu_ccr_update_tst8 (sim_cpu *cpu, uint8 val)
 {
-  cpu_set_ccr_V (proc, 0);
-  cpu_set_ccr_N (proc, val & 0x80 ? 1 : 0);
-  cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
+  cpu_set_ccr_V (cpu, 0);
+  cpu_set_ccr_N (cpu, val & 0x80 ? 1 : 0);
+  cpu_set_ccr_Z (cpu, val == 0 ? 1 : 0);
 }
 
 
@@ -636,7 +656,7 @@ cpu_push_all (sim_cpu *cpu)
 
 /* Simulation of the dbcc/ibcc/tbcc 68HC12 conditional branch operations.  */
 void
-cpu_dbcc (sim_cpu* cpu)
+cpu_dbcc (sim_cpu *cpu)
 {
   uint8 code;
   uint16 addr;
@@ -677,7 +697,7 @@ cpu_dbcc (sim_cpu* cpu)
 }
 
 void
-cpu_exg (sim_cpu* cpu, uint8 code)
+cpu_exg (sim_cpu *cpu, uint8 code)
 {
   uint8 r1, r2;
   uint16 src1;
@@ -1037,7 +1057,8 @@ cpu_info (SIM_DESC sd, sim_cpu *cpu)
 {
   sim_io_printf (sd, "CPU info:\n");
   sim_io_printf (sd, "  Absolute cycle: %s\n",
-                 cycle_to_string (cpu, cpu->cpu_absolute_cycle));
+                 cycle_to_string (cpu, cpu->cpu_absolute_cycle,
+                                  PRINT_TIME | PRINT_CYCLE));
   
   sim_io_printf (sd, "  Syscall emulation: %s\n",
                  cpu->cpu_emul_syscall ? "yes, via 0xcd <n>" : "no");