sim: sim-stop/sim-reason/sim-reg: move to common obj list

[deliverable/binutils-gdb.git] / sim / mcore / ChangeLog

diff --git a/sim/mcore/ChangeLog b/sim/mcore/ChangeLog
index 70d7ae92fcc2099228965562a6dd06cc039d50f9..d6f0cd1a63d7a047cec3f3433c70384b1a522d04 100644 (file)
--- a/sim/mcore/ChangeLog
+++ b/sim/mcore/ChangeLog
@@ -1,3 +1,60 @@
+2015-11-15  Mike Frysinger  <vapier@gentoo.org>
+
+       * Makefile.in (SIM_OBJS): Delete sim-reason.o, sim-reg.o, and
+       sim-stop.o.
+
+2015-11-15  Mike Frysinger  <vapier@gentoo.org>
+
+       * interp.c (mcore_regset, LAST_VALID_CREG, NUM_MCORE_REGS: Move
+       to sim-main.h.
+       (cpu): Delete.
+       (gr, cr): Change from asregs to cpu.
+       (sr, vbr, esr, fsr, epc, fpc, ss0, ss1, ss2, ss3, ss4, gcr, gsr):
+       Change from asregs to cr.
+       (C_ON, C_VALUE, C_OFF, SET_C, CLR_C, NEW_C, SR_AF): Change from
+       cpu.sr to sr.
+       (set_active_regs): Define.
+       (set_initial_gprs): Rename scpu to cpu.  Change cpu.sr to sr and
+       cpu.gr to gr.  Replace for loop with memset.  Replace SR_AF with
+       set_active_regs.
+       (handle_trap1): Add cpu arg.
+       (process_stub): Likewise.  Change cpu.gr to gr.
+       (util): Rename scpu to cpu.  Change cpu.gr to gr.
+       (rbat, rhat, rlat, wbat, what, wlat, ILLEGAL, sim_engine_run,
+       mcore_reg_store, mcore_reg_fetch, sim_create_inferior): Rename scpu
+       to cpu.
+       (step_once): Likewise.  Replace SR_AF with set_active_regs.  Adjust
+       cpu.asregs to cpu.
+       (mcore_pc_get, mcore_pc_set): Adjust cpu->pc to cpu->regs.pc.
+       * sim-main.h (mcore_regset, LAST_VALID_CREG, NUM_MCORE_REGS: Move
+       from interp.c.
+       (_sim_cpu): Add regs, asints, active_gregs, ticks, stalls, cycles,
+       and insts members.
+
+2015-11-15  Mike Frysinger  <vapier@gentoo.org>
+
+       * Makefile.in (SIM_OBJS): Add sim-reg.o.
+       * interp.c (sim_store_register): Rename to ...
+       (mcore_reg_store): ... this.  Change SIM_DESC to SIM_CPU.
+       (sim_fetch_register): Rename to ...
+       (mcore_reg_fetch): ... this.  Change SIM_DESC to SIM_CPU.
+       (sim_open): Call CPU_REG_FETCH and CPU_REG_STORE.
+
+2015-11-15  Mike Frysinger  <vapier@gentoo.org>
+
+       * Makefile.in (SIM_OBJS): Add sim-reason.o and sim-resume.o.
+       * interp.c (struct mcore_regset): Delete exception.
+       (util): Add SIM_DESC and SIM_CPU args.  Call sim_engine_halt instead
+       of setting cpu.asregs.exception.
+       (ILLEGAL): Define.
+       (sim_resume): Rename to ...
+       (step_once): ... this.  Delete cpu.asregs.exception initialization.
+       Delete do/while statements while keeping the body.  Replace SIGTRAP
+       usage with sim_engine_halt(SIM_SIGTRAP).  Replace SIGILL usage with
+       ILLEGAL.  Pass sd and cpu down to util.
+       (sim_engine_run): Define.
+       (sim_stop_reason): Delete.
+
 2015-11-14  Mike Frysinger  <vapier@gentoo.org>
 
        * interp.c (sim_close): Delete.