+2015-11-15 Mike Frysinger <vapier@gentoo.org>
+
+ * Makefile.in (SIM_OBJS): Delete sim-reason.o, sim-reg.o, and
+ sim-stop.o.
+
+2015-11-15 Mike Frysinger <vapier@gentoo.org>
+
+ * interp.c (mcore_regset, LAST_VALID_CREG, NUM_MCORE_REGS: Move
+ to sim-main.h.
+ (cpu): Delete.
+ (gr, cr): Change from asregs to cpu.
+ (sr, vbr, esr, fsr, epc, fpc, ss0, ss1, ss2, ss3, ss4, gcr, gsr):
+ Change from asregs to cr.
+ (C_ON, C_VALUE, C_OFF, SET_C, CLR_C, NEW_C, SR_AF): Change from
+ cpu.sr to sr.
+ (set_active_regs): Define.
+ (set_initial_gprs): Rename scpu to cpu. Change cpu.sr to sr and
+ cpu.gr to gr. Replace for loop with memset. Replace SR_AF with
+ set_active_regs.
+ (handle_trap1): Add cpu arg.
+ (process_stub): Likewise. Change cpu.gr to gr.
+ (util): Rename scpu to cpu. Change cpu.gr to gr.
+ (rbat, rhat, rlat, wbat, what, wlat, ILLEGAL, sim_engine_run,
+ mcore_reg_store, mcore_reg_fetch, sim_create_inferior): Rename scpu
+ to cpu.
+ (step_once): Likewise. Replace SR_AF with set_active_regs. Adjust
+ cpu.asregs to cpu.
+ (mcore_pc_get, mcore_pc_set): Adjust cpu->pc to cpu->regs.pc.
+ * sim-main.h (mcore_regset, LAST_VALID_CREG, NUM_MCORE_REGS: Move
+ from interp.c.
+ (_sim_cpu): Add regs, asints, active_gregs, ticks, stalls, cycles,
+ and insts members.
+
+2015-11-15 Mike Frysinger <vapier@gentoo.org>
+
+ * Makefile.in (SIM_OBJS): Add sim-reg.o.
+ * interp.c (sim_store_register): Rename to ...
+ (mcore_reg_store): ... this. Change SIM_DESC to SIM_CPU.
+ (sim_fetch_register): Rename to ...
+ (mcore_reg_fetch): ... this. Change SIM_DESC to SIM_CPU.
+ (sim_open): Call CPU_REG_FETCH and CPU_REG_STORE.
+
+2015-11-15 Mike Frysinger <vapier@gentoo.org>
+
+ * Makefile.in (SIM_OBJS): Add sim-reason.o and sim-resume.o.
+ * interp.c (struct mcore_regset): Delete exception.
+ (util): Add SIM_DESC and SIM_CPU args. Call sim_engine_halt instead
+ of setting cpu.asregs.exception.
+ (ILLEGAL): Define.
+ (sim_resume): Rename to ...
+ (step_once): ... this. Delete cpu.asregs.exception initialization.
+ Delete do/while statements while keeping the body. Replace SIGTRAP
+ usage with sim_engine_halt(SIM_SIGTRAP). Replace SIGILL usage with
+ ILLEGAL. Pass sd and cpu down to util.
+ (sim_engine_run): Define.
+ (sim_stop_reason): Delete.
+
+2015-11-14 Mike Frysinger <vapier@gentoo.org>
+
+ * interp.c (sim_close): Delete.
+
+2015-06-23 Mike Frysinger <vapier@gentoo.org>
+
+ * configure: Regenerate.
+
+2015-06-17 Mike Frysinger <vapier@gentoo.org>
+
+ * interp.c (handle_trap1): Replace call to cb_syscall with
+ sim_syscall.
+
+2015-06-17 Mike Frysinger <vapier@gentoo.org>
+
+ * interp.c: Include sim-syscall.h.
+ (syscall_read_mem, syscall_write_mem): Delete.
+ (m32r_trap): Change syscall_read_mem/syscall_write_mem
+ to sim_syscall_read_mem/sim_syscall_write_mem.
+
+2015-06-12 Mike Frysinger <vapier@gentoo.org>
+
+ * configure: Regenerate.
+
+2015-06-12 Mike Frysinger <vapier@gentoo.org>
+
+ * configure: Regenerate.
+
+2015-04-21 Mike Frysinger <vapier@gentoo.org>
+
+ * interp.c (sim_resume): Change %x to %lx for all cpu registers.
+
+2015-04-21 Mike Frysinger <vapier@gentoo.org>
+
+ * interp.c (mcore_regset): Delete msize & memory.
+ (issue_messages, mem, wbat, what, wlat, rbat, what, wlat,
+ sim_memory_size, MEM_SIZE_FLOOR, sim_size, init_pointers): Delete.
+ (DEFAULT_MEMORY_SIZE): Define.
+ (set_initial_gprs): Delete memsize handling and call to init_pointers.
+ Change cpu.asregs.msize to DEFAULT_MEMORY_SIZE.
+ (syscall_read_mem): Change memcpy to sim_core_read_buffer.
+ (syscall_write_mem): Change memcpy to sim_core_write_buffer.
+ (process_stub): Change issue_messages to STATE_VERBOSE_P.
+ (util): Turn printf into a stub. Change issue_messages to
+ STATE_VERBOSE_P.
+ (rbat, rhat, rlat, wbat, what, wlat): Define to sim core funcs.
+ (sim_resume): Change issue_messages to STATE_VERBOSE_P.
+ Delete cpu.asregs.msize range checks.
+ (sim_write, sim_read): Delete.
+ (sim_store_register, sim_fetch_register): Delete call to
+ init_pointers.
+ (sim_open): Delete osize, call to sim_size, and issue_messages. Call
+ sim_do_commandf to setup memory.
+ (sim_create_inferior): Delete issue_messages handling. Change
+ cpu.asregs.msize to DEFAULT_MEMORY_SIZE. Change strcpy to
+ sim_core_write_buffer.
+
+2015-04-21 Mike Frysinger <vapier@gentoo.org>
+
+ * interp.c (WATCHFUNCTIONS): Undef it.
+ (sim_resume): Move WLhash behind WATCHFUNCTIONS.
+ (sim_do_command): Delete.
+
+2015-04-21 Mike Frysinger <vapier@gentoo.org>
+
+ * Makefile.in (NL_TARGET): Define.
+ * interp.c (NUM_ELEM, opened, log_open, log_close, is_opened): Delete.
+ (syscall_read_mem, syscall_write_mem): New functions.
+ (handle_trap1): Delete entire body. Replace with call to cb_syscall.
+
2015-04-18 Mike Frysinger <vapier@gentoo.org>
* sim-main.h (SIM_CPU): Delete.
* config.in: Ditto.
2008-06-06 Vladimir Prus <vladimir@codesourcery.com>
- Daniel Jacobowitz <dan@codesourcery.com>
- Joseph Myers <joseph@codesourcery.com>
+ Daniel Jacobowitz <dan@codesourcery.com>
+ Joseph Myers <joseph@codesourcery.com>
* configure: Regenerate.
* interp.c (target_big_endian): New variable.
(mcore_extract_unsigned_integer, mcore_store_unsigned_integer,
wlat, rlat, sim_resume, sim_load): Add supprot for little
- endian targets.
+ endian targets.
2000-01-13 Nick Clifton <nickc@cygnus.com>
1999-05-08 Felix Lee <flee@cygnus.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
-
+
1999-05-10 Nick Clifton <nickc@cygnus.com>
* interp.c (sim_resume): Record PC in case it is needed for error
projects / deliverable / binutils-gdb.git / blobdiff