+2006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
+
+ * configure: Regenerated.
+
+2006-05-15 Chao-ying Fu <fu@mips.com>
+
+ * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
+
+2006-04-18 Nick Clifton <nickc@redhat.com>
+
+ * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
+ statement.
+
+2006-03-29 Hans-Peter Nilsson <hp@axis.com>
+
+ * configure: Regenerate.
+
+2005-12-14 Chao-ying Fu <fu@mips.com>
+
+ * Makefile.in (SIM_OBJS): Add dsp.o.
+ (dsp.o): New dependency.
+ (IGEN_INCLUDE): Add dsp.igen.
+ * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
+ mipsisa64*-*-*): Add dsp to sim_igen_machine.
+ * configure: Regenerate.
+ * mips.igen: Add dsp model and include dsp.igen.
+ (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
+ because these instructions are extended in DSP ASE.
+ * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
+ adding 6 DSP accumulator registers and 1 DSP control register.
+ (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
+ AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
+ DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
+ DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
+ DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
+ DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
+ DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
+ DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
+ DSPCR_CCOND_SMASK): New define.
+ (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
+ * dsp.c, dsp.igen: New files for MIPS DSP ASE.
+
+2005-07-08 Ian Lance Taylor <ian@airs.com>
+
+ * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
+
+2005-06-16 David Ung <davidu@mips.com>
+ Nigel Stephens <nigel@mips.com>
+
+ * mips.igen: New mips16e model and include m16e.igen.
+ (check_u64): Add mips16e tag.
+ * m16e.igen: New file for MIPS16e instructions.
+ * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
+ mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
+ models.
+ * configure: Regenerate.
+
+2005-05-26 David Ung <davidu@mips.com>
+
+ * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
+ tags to all instructions which are applicable to the new ISAs.
+ (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
+ vr.igen.
+ * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
+ instructions.
+ * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
+ to mips.igen.
+ * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
+ * configure: Regenerate.
+
+2005-03-23 Mark Kettenis <kettenis@gnu.org>
+
+ * configure: Regenerate.
+
+2005-01-14 Andrew Cagney <cagney@gnu.org>
+
+ * configure.ac: Sinclude aclocal.m4 before common.m4. Add
+ explicit call to AC_CONFIG_HEADER.
+ * configure: Regenerate.
+
+2005-01-12 Andrew Cagney <cagney@gnu.org>
+
+ * configure.ac: Update to use ../common/common.m4.
+ * configure: Re-generate.
+
+2005-01-11 Andrew Cagney <cagney@localhost.localdomain>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+2005-01-07 Andrew Cagney <cagney@gnu.org>
+
+ * configure.ac: Rename configure.in, require autoconf 2.59.
+ * configure: Re-generate.
+
+2004-12-08 Hans-Peter Nilsson <hp@axis.com>
+
+ * configure: Regenerate for ../common/aclocal.m4 update.
+
+2004-09-24 Monika Chaddha <monika@acmet.com>
+
+ Committed by Andrew Cagney.
+ * m16.igen (CMP, CMPI): Fix assembler.
+
+2004-08-18 Chris Demetriou <cgd@broadcom.com>
+
+ * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
+ * configure: Regenerate.
+
+2004-06-25 Chris Demetriou <cgd@broadcom.com>
+
+ * configure.in (sim_m16_machine): Include mipsIII.
+ * configure: Regenerate.
+
+2004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
+
+ * mips/interp.c (decode_coproc): Sign-extend the address retrieved
+ from COP0_BADVADDR.
+ * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
+
+2004-04-10 Chris Demetriou <cgd@broadcom.com>
+
+ * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
+
+2004-04-09 Chris Demetriou <cgd@broadcom.com>
+
+ * mips.igen (check_fmt): Remove.
+ (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
+ (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
+ (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
+ (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
+ (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
+ (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
+ (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
+ (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
+ (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
+ (C.cnd.fmta): Remove incorrect call to check_fmt_p.
+
+2004-04-09 Chris Demetriou <cgd@broadcom.com>
+
+ * sb1.igen (check_sbx): New function.
+ (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
+
+2004-03-29 Chris Demetriou <cgd@broadcom.com>
+ Richard Sandiford <rsandifo@redhat.com>
+
+ * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
+ (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
+ * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
+ separate implementations for mipsIV and mipsV. Use new macros to
+ determine whether the restrictions apply.
+
+2004-01-19 Chris Demetriou <cgd@broadcom.com>
+
+ * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
+ (check_mult_hilo): Improve comments.
+ (check_div_hilo): Likewise. Also, fork off a new version
+ to handle mips32/mips64 (since there are no hazards to check
+ in MIPS32/MIPS64).
+
+2003-06-17 Richard Sandiford <rsandifo@redhat.com>
+
+ * mips.igen (do_dmultx): Fix check for negative operands.
+
+2003-05-16 Ian Lance Taylor <ian@airs.com>
+
+ * Makefile.in (SHELL): Make sure this is defined.
+ (various): Use $(SHELL) whenever we invoke move-if-change.
+
+2003-05-03 Chris Demetriou <cgd@broadcom.com>
+
+ * cp1.c: Tweak attribution slightly.
+ * cp1.h: Likewise.
+ * mdmx.c: Likewise.
+ * mdmx.igen: Likewise.
+ * mips3d.igen: Likewise.
+ * sb1.igen: Likewise.
+
+2003-04-15 Richard Sandiford <rsandifo@redhat.com>
+
+ * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
+ unsigned operands.
+
+2003-02-27 Andrew Cagney <cagney@redhat.com>
+
+ * interp.c (sim_open): Rename _bfd to bfd.
+ (sim_create_inferior): Ditto.
+
+2003-01-14 Chris Demetriou <cgd@broadcom.com>
+
+ * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
+
+2003-01-14 Chris Demetriou <cgd@broadcom.com>
+
+ * mips.igen (EI, DI): Remove.
+
+2003-01-05 Richard Sandiford <rsandifo@redhat.com>
+
+ * Makefile.in (tmp-run-multi): Fix mips16 filter.
+
+2003-01-04 Richard Sandiford <rsandifo@redhat.com>
+ Andrew Cagney <ac131313@redhat.com>
+ Gavin Romig-Koch <gavin@redhat.com>
+ Graydon Hoare <graydon@redhat.com>
+ Aldy Hernandez <aldyh@redhat.com>
+ Dave Brolley <brolley@redhat.com>
+ Chris Demetriou <cgd@broadcom.com>
+
+ * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
+ (sim_mach_default): New variable.
+ (mips64vr-*-*, mips64vrel-*-*): New configurations.
+ Add a new simulator generator, MULTI.
+ * configure: Regenerate.
+ * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
+ (multi-run.o): New dependency.
+ (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
+ (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
+ (tmp-multi): Combine them.
+ (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
+ (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
+ (distclean-extra): New rule.
+ * sim-main.h: Include bfd.h.
+ (MIPS_MACH): New macro.
+ * mips.igen (vr4120, vr5400, vr5500): New models.
+ (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
+ * vr.igen: Replace with new version.
+
+2003-01-04 Chris Demetriou <cgd@broadcom.com>
+
+ * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
+ * configure: Regenerate.
+
+2002-12-31 Chris Demetriou <cgd@broadcom.com>
+
+ * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
+ * mips.igen: Remove all invocations of check_branch_bug and
+ mark_branch_bug.
+
+2002-12-16 Chris Demetriou <cgd@broadcom.com>
+
+ * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
+
+2002-07-30 Chris Demetriou <cgd@broadcom.com>
+
+ * mips.igen (do_load_double, do_store_double): New functions.
+ (LDC1, SDC1): Rename to...
+ (LDC1b, SDC1b): respectively.
+ (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
+
+2002-07-29 Michael Snyder <msnyder@redhat.com>
+
+ * cp1.c (fp_recip2): Modify initialization expression so that
+ GCC will recognize it as constant.
+
+2002-06-18 Chris Demetriou <cgd@broadcom.com>
+
+ * mdmx.c (SD_): Delete.
+ (Unpredictable): Re-define, for now, to directly invoke
+ unpredictable_action().
+ (mdmx_acc_op): Fix error in .ob immediate handling.
+
+2002-06-18 Andrew Cagney <cagney@redhat.com>
+
+ * interp.c (sim_firmware_command): Initialize `address'.
+
+2002-06-16 Andrew Cagney <ac131313@redhat.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+2002-06-14 Chris Demetriou <cgd@broadcom.com>
+ Ed Satterthwaite <ehs@broadcom.com>
+
+ * mips3d.igen: New file which contains MIPS-3D ASE instructions.
+ * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
+ * mips.igen: Include mips3d.igen.
+ (mips3d): New model name for MIPS-3D ASE instructions.
+ (CVT.W.fmt): Don't use this instruction for word (source) format
+ instructions.
+ * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
+ (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
+ (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
+ (NR_FRAC_GUARD, IMPLICIT_1): New macros.
+ * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
+ (RSquareRoot1, RSquareRoot2): New macros.
+ (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
+ (fp_rsqrt2): New functions.
+ * configure.in: Add MIPS-3D support to mipsisa64 simulator.
+ * configure: Regenerate.
+
2002-06-13 Chris Demetriou <cgd@broadcom.com>
+ Ed Satterthwaite <ehs@broadcom.com>
* cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
(value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)