+Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+ * config.in: Ditto.
+
+Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
+
+ * acconfig.h: New file.
+ * configure.in: Reverted change of Apr 24; use sinclude again.
+
+Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+ * config.in: Ditto.
+
+Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
+
+ * configure.in: Don't call sinclude.
+
+Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
+
+ * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
+
+Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * mips.igen (ERET): Implement.
+
+ * interp.c (decode_coproc): Return sign-extended EPC.
+
+ * mips.igen (ANDI, LUI, MFC0): Add tracing code.
+
+ * interp.c (signal_exception): Do not ignore Trap.
+ (signal_exception): On TRAP, restart at exception address.
+ (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
+ (signal_exception): Update.
+ (sim_open): Patch V_COMMON interrupt vector with an abort sequence
+ so that TRAP instructions are caught.
+
+Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * sim-main.h (struct hilo_access, struct hilo_history): Define,
+ contains HI/LO access history.
+ (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
+ (HIACCESS, LOACCESS): Delete, replace with
+ (HIHISTORY, LOHISTORY): New macros.
+ (start-sanitize-r5900):
+ (struct sim_5900_cpu): Make hi1access, lo1access of type
+ hilo_access.
+ (HI1ACCESS, LO1ACCESS): Delete, replace with
+ (HI1HISTORY, LO1HISTORY): New macros.
+ (end-sanitize-r5900):
+ (CHECKHILO): Delete all, moved to mips.igen
+
+ * gencode.c (build_instruction): Do not generate checks for
+ correct HI/LO register usage.
+
+ * interp.c (old_engine_run): Delete checks for correct HI/LO
+ register usage.
+
+ * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
+ check_mf_cycles): New functions.
+ (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
+ do_divu, domultx, do_mult, do_multu): Use.
+
+ * tx.igen ("madd", "maddu"): Use.
+ (start-sanitize-r5900):
+
+ r5900.igen: Update all HI/LO checks.
+ ("mfhi1", "mflo1", "mthi1", "mthi1", "pmfhi", "pmflo", "pmfhl",
+ "pmthi", "pmtlo", "mpthl"): Check MF/MT HI/LO.
+ ("mult1", "div1", "divu1", "multu1", "madd1", "maddu1", "pdivbw",
+ "pdivuw", "pdivw", "phmaddh", "phmsubh", "pmaddh", "madduw",
+ "pmaddw", "pmsubh", "pmsubw", "pmulth", "pmultuw", "pmultw"):
+ Check HI/LO op.
+ (end-sanitize-r5900):
+
+start-sanitize-sky
+Mon Apr 20 18:39:47 1998 Frank Ch. Eigler <fche@cygnus.com>
+
+ * interp.c (decode_coproc): Correct CMFC2/QMTC2
+ GPR access.
+
+ * r5900.igen (LQ,SQ): Use a pair of 64-bit accesses
+ instead of a single 128-bit access.
+
+end-sanitize-sky
+start-sanitize-sky
+Fri Apr 17 14:50:39 1998 Frank Ch. Eigler <fche@cygnus.com>
+
+ * r5900.igen (COP_[LS]Q): Transfer COP2 quadwords.
+ * interp.c (cop_[ls]q): Fixes corresponding to above.
+
+end-sanitize-sky
+start-sanitize-sky
+Thu Apr 16 15:24:14 1998 Frank Ch. Eigler <fche@cygnus.com>
+
+ * interp.c (decode_coproc): Adapt COP2 micro interlock to
+ clarified specs. Reset "M" bit; exit also on "E" bit.
+
+end-sanitize-sky
+start-sanitize-r5900
+Thu Apr 16 10:40:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * r5900.igen (CFC1, CTC1): Implement R5900 specific version.
+ * mips.igen (CFC1, CTC1): R5900 des not use generic version.
+
+ * r5900.igen (r59fp_unpack): New function.
+ (r59fp_op1, r59fp_op2, r59fp_op3, C.cond.S, CVT.S.W, DIV.S,
+ RSQRT.S, SQRT.S): Use.
+ (r59fp_zero): New function.
+ (r59fp_overflow): Generate r5900 specific overflow value.
+ (r59fp_store): Re-write, overflow to MAX_R5900_FP value, underflow
+ to zero.
+ (CVT.S.W, CVT.W.S): Exchange implementations.
+
+ * sim-main.h (R5900_EXPMAX, R5900_EXPMIN, R5900_EXPBIAS): Defile.
+
+end-sanitize-r5900
+start-sanitize-tx19
+Thu Apr 16 09:14:44 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure.in (tx19, sim_use_gen): Switch to igen.
+ * configure: Re-build.
+
+end-sanitize-tx19
+start-sanitize-sky
+Wed Apr 15 12:41:18 1998 Frank Ch. Eigler <fche@cygnus.com>
+
+ * interp.c (decode_coproc): Make COP2 branch code compile after
+ igen signature changes.
+
+end-sanitize-sky
+Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * mips.igen (DSRAV): Use function do_dsrav.
+ (SRAV): Use new function do_srav.
+
+ * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
+ (B): Sign extend 11 bit immediate.
+ (EXT-B*): Shift 16 bit immediate left by 1.
+ (ADDIU*): Don't sign extend immediate value.
+
+Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * m16run.c (sim_engine_run): Restore CIA after handling an event.
+
+start-sanitize-tx19
+ * mips.igen (mtc0): Valid tx19 instruction.
+
+end-sanitize-tx19
+ * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
+ functions.
+
+ * mips.igen (delayslot32, nullify_next_insn): New functions.
+ (m16.igen): Always include.
+ (do_*): Add more tracing.
+
+ * m16.igen (delayslot16): Add NIA argument, could be called by a
+ 32 bit MIPS16 instruction.
+
+ * interp.c (ifetch16): Move function from here.
+ * sim-main.c (ifetch16): To here.
+
+ * sim-main.c (ifetch16, ifetch32): Update to match current
+ implementations of LH, LW.
+ (signal_exception): Don't print out incorrect hex value of illegal
+ instruction.
+
+Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
+ instruction.
+
+ * m16.igen: Implement MIPS16 instructions.
+
+ * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
+ do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
+ do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
+ do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
+ do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
+ bodies of corresponding code from 32 bit insn to these. Also used
+ by MIPS16 versions of functions.
+
+ * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
+ (IMEM16): Drop NR argument from macro.
+
+start-sanitize-sky
+Mon Apr 13 16:28:52 1998 Frank Ch. Eigler <fche@cygnus.com>
+
+ * interp.c (decode_coproc): Add proper 1000000 bit-string at top
+ of VU lower instruction.
+
+end-sanitize-sky
+start-sanitize-sky
+Thu Apr 9 16:38:23 1998 Frank Ch. Eigler <fche@cygnus.com>
+
+ * r5900.igen (LQC,SQC): Adapted code to DOUBLEWORD accesses
+ instead of QUADWORD.
+
+ * sim-main.h: Removed attempt at allowing 128-bit access.
+
+end-sanitize-sky
+start-sanitize-sky
+Wed Apr 8 18:12:13 1998 Frank Ch. Eigler <fche@cygnus.com>
+
+ * Makefile.in (SIM_SKY_OBJS): Added sky-vudis.o.
+
+ * interp.c (decode_coproc): Refer to VU CIA as a "special"
+ register, not as a "misc" register. Aha. Add activity
+ assertions after VCALLMS* instructions.
+
+end-sanitize-sky
+start-sanitize-sky
+Tue Apr 7 18:32:49 1998 Frank Ch. Eigler <fche@cygnus.com>
+
+ * interp.c (decode_coproc): Do not apply superfluous E (end) flag
+ to upper code of generated VU instruction.
+
+end-sanitize-sky
+start-sanitize-sky
+Mon Apr 6 19:55:56 1998 Frank Ch. Eigler <fche@cygnus.com>
+
+ * interp.c (cop_[ls]q): Replaced stub with proper COP2 code.
+
+ * sim-main.h (LOADADDRMASK): Redefine to allow 128-bit accesses
+ for TARGET_SKY.
+
+ * r5900.igen (SQC2): Thinko.
+
+end-sanitize-sky
+start-sanitize-sky
+Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com>
+
+ * interp.c (*): Adapt code to merged VU device & state structs.
+ (decode_coproc): Execute COP2 each macroinstruction without
+ pipelining, by stepping VU to completion state. Adapted to
+ read_vu_*_reg style of register access.
+
+ * mips.igen ([SL]QC2): Removed these COP2 instructions.
+
+ * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here.
+
+ * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards.
+
+end-sanitize-sky
+Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * Makefile.in (SIM_OBJS): Add sim-main.o.
+
+ * sim-main.h (address_translation, load_memory, store_memory,
+ cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
+ as INLINE_SIM_MAIN.
+ (pr_addr, pr_uword64): Declare.
+ (sim-main.c): Include when H_REVEALS_MODULE_P.
+
+ * interp.c (address_translation, load_memory, store_memory,
+ cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
+ from here.
+ * sim-main.c: To here. Fix compilation problems.
+
+ * configure.in: Enable inlining.
+ * configure: Re-config.
+
+Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * mips.igen: Include tx.igen.
+ * Makefile.in (IGEN_INCLUDE): Add tx.igen.
+ * tx.igen: New file, contains MADD and MADDU.
+
+ * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
+ the hardwired constant `7'.
+ (store_memory): Ditto.
+ (LOADDRMASK): Move definition to sim-main.h.
+
+ mips.igen (MTC0): Enable for r3900.
+ (ADDU): Add trace.
+
+ mips.igen (do_load_byte): Delete.
+ (do_load, do_store, do_load_left, do_load_write, do_store_left,
+ do_store_right): New functions.
+ (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
+
+ configure.in: Let the tx39 use igen again.
+ configure: Update.
+
+Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
+ not an address sized quantity. Return zero for cache sizes.
+
+Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * mips.igen (r3900): r3900 does not support 64 bit integer
+ operations.
+
+start-sanitize-sky
+Wed Apr 1 08:20:31 1998 Frank Ch. Eigler <fche@cygnus.com>
+
+ * mips.igen (SQC2/LQC2): Make bodies sky-target-only also.
+
+end-sanitize-sky
+start-sanitize-sky
+Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com>
+
+ * interp.c (decode_coproc): Continuing COP2 work.
+ (cop_[ls]q): Make sky-target-only.
+
+ * sim-main.h (COP_[LS]Q): Make sky-target-only.
+end-sanitize-sky
+Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
+
+ * configure.in (mipstx39*-*-*): Use gencode simulator rather
+ than igen one.
+ * configure : Rebuild.
+
+start-sanitize-sky
+Sun Mar 29 17:50:11 Frank Ch. Eigler <fche@cygnus.com>
+
+ * interp.c (decode_coproc): Added a missing TARGET_SKY check
+ around COP2 implementation skeleton.
+
+end-sanitize-sky
+start-sanitize-sky
+Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com>
+
+ * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o.
+
+ * interp.c (sim_{load,store}_register): Use new vu[01]_device
+ static to access VU registers.
+ (decode_coproc): Added skeleton of sky COP2 (VU) instruction
+ decoding. Work in progress.
+
+ * mips.igen (LDCzz, SDCzz): Removed *5900 case for this
+ overlapping/redundant bit pattern.
+ (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in
+ progress.
+
+ * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for
+ status register.
+
+ * interp.c (cop_lq, cop_sq): New functions for future 128-bit
+ access to coprocessor registers.
+
+ * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above.
+end-sanitize-sky
+Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
* interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
* interp.c (MEM_SIZE): Increased default sky memory size to 16MB.
end-sanitize-sky
-
* configure.in: Added X11 search, just in case.
* configure: Regenerated.
projects / deliverable / binutils-gdb.git / blobdiff