MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
$Revision$
- $Author$
- $Date$
+ $Date$
NOTEs:
-We only need to take account of the target endianness when moving data
-between the simulator and the host. We do not need to worry about the
-endianness of the host, since this sim code and GDB are executing in
-the same process.
-
The IDT monitor (found on the VR4300 board), seems to lie about
register contents. It seems to treat the registers as sign-extended
32-bit values. This cause *REAL* problems when single-stepping 64-bit
*/
-/* The TRACE and PROFILE manifests enable the provision of extra
- features. If they are not defined then a simpler (quicker)
- simulator is constructed without the required run-time checks,
- etc. */
+/* The TRACE manifests enable the provision of extra features. If they
+ are not defined then a simpler (quicker) simulator is constructed
+ without the required run-time checks, etc. */
#if 1 /* 0 to allow user build selection, 1 to force inclusion */
#define TRACE (1)
-#define PROFILE (1)
#endif
+#include "bfd.h"
+#include "sim-main.h"
+#include "sim-utils.h"
+#include "sim-options.h"
+#include "sim-assert.h"
+
+/* start-sanitize-sky */
+#ifdef TARGET_SKY
+#include "sky-vu.h"
+#include "sky-vpe.h"
+#include "sky-libvpe.h"
+#include "sky-pke.h"
+#include "sky-gpuif.h"
+#include "idecode.h"
+#include "support.h"
+#undef SD
+#endif
+/* end-sanitize-sky */
+
+#include "config.h"
+
#include <stdio.h>
#include <stdarg.h>
#include <ansidecl.h>
-#include <signal.h>
#include <ctype.h>
#include <limits.h>
#include <math.h>
+#ifdef HAVE_STDLIB_H
+#include <stdlib.h>
+#endif
+#ifdef HAVE_STRING_H
+#include <string.h>
+#else
+#ifdef HAVE_STRINGS_H
+#include <strings.h>
+#endif
+#endif
#include "getopt.h"
#include "libiberty.h"
-
-#include "remote-sim.h" /* GDB simulator interface */
+#include "bfd.h"
#include "callback.h" /* GDB simulator callback interface */
+#include "remote-sim.h" /* GDB simulator interface */
+
+#include "sysdep.h"
+
+#ifndef PARAMS
+#define PARAMS(x)
+#endif
+
+char* pr_addr PARAMS ((SIM_ADDR addr));
+char* pr_uword64 PARAMS ((uword64 addr));
-#include "support.h" /* internal support manifests */
/* Get the simulator engine description, without including the code: */
+#if !(WITH_IGEN)
#define SIM_MANIFESTS
-#include "engine.c"
+#include "oengine.c"
#undef SIM_MANIFESTS
+#endif
+
+/* Within interp.c we refer to the sim_state and sim_cpu directly. */
+#define CPU cpu
+#define SD sd
+
/* The following reserved instruction value is used when a simulator
trap is required. NOTE: Care must be taken, since this value may be
used in later revisions of the MIPS ISA. */
-#define RSVD_INSTRUCTION (0x7C000000)
-#define RSVD_INSTRUCTION_AMASK (0x03FFFFFF)
-
-/* NOTE: These numbers depend on the processor architecture being
- simulated: */
-#define Interrupt (0)
-#define TLBModification (1)
-#define TLBLoad (2)
-#define TLBStore (3)
-#define AddressLoad (4)
-#define AddressStore (5)
-#define InstructionFetch (6)
-#define DataReference (7)
-#define SystemCall (8)
-#define BreakPoint (9)
-#define ReservedInstruction (10)
-#define CoProcessorUnusable (11)
-#define IntegerOverflow (12) /* Arithmetic overflow (IDT monitor raises SIGFPE) */
-#define Trap (13)
-#define FPE (15)
-#define Watch (23)
-
-/* The following exception code is actually private to the simulator
- world. It is *NOT* a processor feature, and is used to signal
- run-time errors in the simulator. */
-#define SimulatorFault (0xFFFFFFFF)
-
-/* The following are generic to all versions of the MIPS architecture
- to date: */
-/* Memory Access Types (for CCA): */
-#define Uncached (0)
-#define CachedNoncoherent (1)
-#define CachedCoherent (2)
-#define Cached (3)
-
-#define isINSTRUCTION (1 == 0) /* FALSE */
-#define isDATA (1 == 1) /* TRUE */
-
-#define isLOAD (1 == 0) /* FALSE */
-#define isSTORE (1 == 1) /* TRUE */
-
-#define isREAL (1 == 0) /* FALSE */
-#define isRAW (1 == 1) /* TRUE */
-
-#define isTARGET (1 == 0) /* FALSE */
-#define isHOST (1 == 1) /* TRUE */
-
-/* The "AccessLength" specifications for Loads and Stores. NOTE: This
- is the number of bytes minus 1. */
-#define AccessLength_BYTE (0)
-#define AccessLength_HALFWORD (1)
-#define AccessLength_TRIPLEBYTE (2)
-#define AccessLength_WORD (3)
-#define AccessLength_QUINTIBYTE (4)
-#define AccessLength_SEXTIBYTE (5)
-#define AccessLength_SEPTIBYTE (6)
-#define AccessLength_DOUBLEWORD (7)
-
-#if defined(HASFPU)
-/* FPU registers must be one of the following types. All other values
- are reserved (and undefined). */
-typedef enum {
- fmt_single = 0,
- fmt_double = 1,
- fmt_word = 4,
- fmt_long = 5,
- /* The following are well outside the normal acceptable format
- range, and are used in the register status vector. */
- fmt_unknown = 0x10000000,
- fmt_uninterpreted = 0x20000000,
-} FP_formats;
-#endif /* HASFPU */
-
-/* NOTE: We cannot avoid globals, since the GDB "sim_" interface does
- not allow a private variable to be passed around. This means that
- simulators under GDB can only be single-threaded. However, it would
- be possible for the simulators to be multi-threaded if GDB allowed
- for a private pointer to be maintained. i.e. a general "void **ptr"
- variable that GDB passed around in the argument list to all of
- sim_xxx() routines. It could be initialised to NULL by GDB, and
- then updated by sim_open() and used by the other sim_xxx() support
- functions. This would allow new features in the simulator world,
- like storing a context - continuing execution to gather a result,
- and then going back to the point where the context was saved and
- changing some state before continuing. i.e. the ability to perform
- UNDOs on simulations. It would also allow the simulation of
- shared-memory multi-processor systems. */
-
-static host_callback *callback = NULL; /* handle onto the current callback structure */
-
-/* The warning system should be improved, to allow more information to
- be passed about the cause: */
-#define WARNING(m) { callback->printf_filtered(callback,"SIM Warning: %s\n",(m)); }
-
-/* This is nasty, since we have to rely on matching the register
- numbers used by GDB. Unfortunately, depending on the MIPS target
- GDB uses different register numbers. We cannot just include the
- relevant "gdb/tm.h" link, since GDB may not be configured before
- the sim world, and also the GDB header file requires too much other
- state. */
-/* TODO: Sort out a scheme for *KNOWING* the mapping between real
- registers, and the numbers that GDB uses. At the moment due to the
- order that the tools are built, we cannot rely on a configured GDB
- world whilst constructing the simulator. This means we have to
- assume the GDB register number mapping. */
-#define LAST_EMBED_REGNUM (89)
-
-/* To keep this default simulator simple, and fast, we use a direct
- vector of registers. The internal simulator engine then uses
- manifests to access the correct slot. */
-ut_reg registers[LAST_EMBED_REGNUM + 1];
-int register_widths[LAST_EMBED_REGNUM + 1];
-
-#define GPR (®isters[0])
-#if defined(HASFPU)
-#define FGRIDX (38)
-#define FGR (®isters[FGRIDX])
-#endif /* HASFPU */
-#define LO (registers[33])
-#define HI (registers[34])
-#define PC (registers[37])
-#define CAUSE (registers[36])
-#define SRIDX (32)
-#define SR (registers[SRIDX]) /* CPU status register */
-#define FCR0IDX (71)
-#define FCR0 (registers[FCR0IDX]) /* really a 32bit register */
-#define FCR31IDX (70)
-#define FCR31 (registers[FCR31IDX]) /* really a 32bit register */
-#define FCSR (FCR31)
-#define COCIDX (LAST_EMBED_REGNUM + 2) /* special case : outside the normal range */
-
-/* The following are pseudonyms for standard registers */
-#define ZERO (registers[0])
-#define V0 (registers[2])
-#define A0 (registers[4])
-#define A1 (registers[5])
-#define A2 (registers[6])
-#define A3 (registers[7])
-#define SP (registers[29])
-#define RA (registers[31])
-
-ut_reg EPC = 0; /* Exception PC */
-
-#if defined(HASFPU)
-/* Keep the current format state for each register: */
-FP_formats fpr_state[32];
-#endif /* HASFPU */
-
-/* VR4300 CP0 configuration register: */
-unsigned int CONFIG = 0;
-
-/* The following are internal simulator state variables: */
-ut_reg IPC = 0; /* internal Instruction PC */
-ut_reg DSPC = 0; /* delay-slot PC */
-
-
-/* TODO : these should be the bitmasks for these bits within the
- status register. At the moment the following are VR4300
- bit-positions: */
-#define status_KSU_mask (0x3) /* mask for KSU bits */
-#define status_KSU_shift (3) /* shift for field */
-#define ksu_kernel (0x0)
-#define ksu_supervisor (0x1)
-#define ksu_user (0x2)
-#define ksu_unknown (0x3)
-
-#define status_RE (1 << 25) /* Reverse Endian in user mode */
-#define status_FR (1 << 26) /* enables MIPS III additional FP registers */
-#define status_SR (1 << 20) /* soft reset or NMI */
-#define status_BEV (1 << 22) /* Location of general exception vectors */
-#define status_TS (1 << 21) /* TLB shutdown has occurred */
-#define status_ERL (1 << 2) /* Error level */
-#define status_RP (1 << 27) /* Reduced Power mode */
-
-#define config_EP_mask (0xF)
-#define config_EP_shift (27)
-#define config_EP_D (0x0)
-#define config_EP_DxxDxx (0x6)
-
-#define config_BE (1 << 15)
-
-#define cause_BD ((unsigned)1 << 31) /* Exception in branch delay slot */
-
-#if defined(HASFPU)
-/* Macro to update FPSR condition-code field. This is complicated by
- the fact that there is a hole in the index range of the bits within
- the FCSR register. Also, the number of bits visible depends on the
- MIPS ISA version being supported. */
-#define SETFCC(cc,v) {\
- int bit = ((cc == 0) ? 23 : (24 + (cc)));\
- FCSR = ((FCSR & ~(1 << bit)) | ((v) << bit));\
- }
-#define GETFCC(cc) (((((cc) == 0) ? (FCSR & (1 << 23)) : (FCSR & (1 << (24 + (cc))))) != 0) ? 1 : 0)
-
-/* This should be the COC1 value at the start of the preceding
- instruction: */
-#define PREVCOC1() ((state & simPCOC1) ? 1 : 0)
-#endif /* HASFPU */
-
-/* Standard FCRS bits: */
-#define IR (0) /* Inexact Result */
-#define UF (1) /* UnderFlow */
-#define OF (2) /* OverFlow */
-#define DZ (3) /* Division by Zero */
-#define IO (4) /* Invalid Operation */
-#define UO (5) /* Unimplemented Operation */
-
-/* Get masks for individual flags: */
-#if 1 /* SAFE version */
-#define FP_FLAGS(b) (((unsigned)(b) < 5) ? (1 << ((b) + 2)) : 0)
-#define FP_ENABLE(b) (((unsigned)(b) < 5) ? (1 << ((b) + 7)) : 0)
-#define FP_CAUSE(b) (((unsigned)(b) < 6) ? (1 << ((b) + 12)) : 0)
-#else
-#define FP_FLAGS(b) (1 << ((b) + 2))
-#define FP_ENABLE(b) (1 << ((b) + 7))
-#define FP_CAUSE(b) (1 << ((b) + 12))
-#endif
-#define FP_FS (1 << 24) /* MIPS III onwards : Flush to Zero */
-
-#define FP_MASK_RM (0x3)
-#define FP_SH_RM (0)
-#define FP_RM_NEAREST (0) /* Round to nearest (Round) */
-#define FP_RM_TOZERO (1) /* Round to zero (Trunc) */
-#define FP_RM_TOPINF (2) /* Round to Plus infinity (Ceil) */
-#define FP_RM_TOMINF (3) /* Round to Minus infinity (Floor) */
-#define GETRM() (int)((FCSR >> FP_SH_RM) & FP_MASK_RM)
-
-/* Slots for delayed register updates. For the moment we just have a
- fixed number of slots (rather than a more generic, dynamic
- system). This keeps the simulator fast. However, we only allow for
- the register update to be delayed for a single instruction
- cycle. */
-#define PSLOTS (5) /* Maximum number of instruction cycles */
-int pending_in;
-int pending_out;
-int pending_total;
-int pending_slot_count[PSLOTS];
-int pending_slot_reg[PSLOTS];
-ut_reg pending_slot_value[PSLOTS];
-
-/* The following are not used for MIPS IV onwards: */
-#define PENDING_FILL(r,v) {\
-printf("DBG: FILL BEFORE pending_in = %d, pending_out = %d, pending_total = %d\n",pending_in,pending_out,pending_total);\
- if (pending_slot_reg[pending_in] != (LAST_EMBED_REGNUM + 1))\
- callback->printf_filtered(callback,"SIM Warning: Attempt to over-write pending value\n");\
- pending_slot_count[pending_in] = 2;\
- pending_slot_reg[pending_in] = (r);\
- pending_slot_value[pending_in] = (uword64)(v);\
-printf("DBG: FILL reg %d value = 0x%08X%08X\n",(r),WORD64HI(v),WORD64LO(v));\
- pending_total++;\
- pending_in++;\
- if (pending_in == PSLOTS)\
- pending_in = 0;\
-printf("DBG: FILL AFTER pending_in = %d, pending_out = %d, pending_total = %d\n",pending_in,pending_out,pending_total);\
- }
+#define RSVD_INSTRUCTION (0x00000005)
+#define RSVD_INSTRUCTION_MASK (0xFC00003F)
-int LLBIT = 0;
-/* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
- read-write instructions. It is set when a linked load occurs. It is
- tested and cleared by the conditional store. It is cleared (during
- other CPU operations) when a store to the location would no longer
- be atomic. In particular, it is cleared by exception return
- instructions. */
-
-int HIACCESS = 0;
-int LOACCESS = 0;
-/* The HIACCESS and LOACCESS counts are used to ensure that
- corruptions caused by using the HI or LO register to close to a
- following operation are spotted. */
-
-/* If either of the preceding two instructions have accessed the HI or
- LO registers, then the values they see should be
- undefined. However, to keep the simulator world simple, we just let
- them use the value read and raise a warning to notify the user: */
-#define CHECKHILO(s) {\
- if ((HIACCESS != 0) || (LOACCESS != 0))\
- callback->printf_filtered(callback,"SIM Warning: %s over-writing HI and LO registers values\n",(s));\
- /* Set the access counts, since we are about\
- to update the HI and LO registers: */\
- HIACCESS = LOACCESS = 3; /* 3rd instruction will be safe */\
- }
+#define RSVD_INSTRUCTION_ARG_SHIFT 6
+#define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
+
+
+/* The following reserved instruction value is used when a simulator
+ halt is required. NOTE: Care must be taken, since this value may
+ be used in later revisions of the MIPS ISA. */
+#define HALT_INSTRUCTION (0x03ff000d)
+#define HALT_INSTRUCTION_MASK (0x03FFFFC0)
+
+
+/* Bits in the Debug register */
+#define Debug_DBD 0x80000000 /* Debug Branch Delay */
+#define Debug_DM 0x40000000 /* Debug Mode */
+#define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
+
+
+
+
+
+/*---------------------------------------------------------------------------*/
+/*-- GDB simulator interface ------------------------------------------------*/
+/*---------------------------------------------------------------------------*/
+
+static void ColdReset PARAMS((SIM_DESC sd));
+
+/*---------------------------------------------------------------------------*/
-/* NOTE: We keep the following status flags as bit values (1 for true,
- 0 for false). This allows them to be used in binary boolean
- operations without worrying about what exactly the non-zero true
- value is. */
-
-/* UserMode */
-#define UserMode ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0)
-
-/* BigEndianMem */
-/* Hardware configuration. Affects endianness of LoadMemory and
- StoreMemory and the endianness of Kernel and Supervisor mode
- execution. The value is 0 for little-endian; 1 for big-endian. */
-#define BigEndianMem ((CONFIG & config_BE) ? 1 : 0)
-/* NOTE: Problems will occur if the simulator memory model does not
- match the host program expectation. i.e. if the host is writing
- big-endian values to a little-endian memory model. */
-
-/* ReverseEndian */
-/* This mode is selected if in User mode with the RE bit being set in
- SR (Status Register). It reverses the endianness of load and store
- instructions. */
-#define ReverseEndian (((SR & status_RE) && UserMode) ? 1 : 0)
-
-/* BigEndianCPU */
-/* The endianness for load and store instructions (0=little;1=big). In
- User mode this endianness may be switched by setting the state_RE
- bit in the SR register. Thus, BigEndianCPU may be computed as
- (BigEndienMem EOR ReverseEndian). */
-#define BigEndianCPU (BigEndianMem ^ ReverseEndian) /* Already bits */
-
-#if !defined(FASTSIM) || defined(PROFILE)
-/* At the moment these values will be the same, since we do not have
- access to the pipeline cycle count information from the simulator
- engine. */
-unsigned int instruction_fetches = 0;
-unsigned int instruction_fetch_overflow = 0;
-unsigned int pipeline_ticks = 0;
-#endif
-/* Flags in the "state" variable: */
-#define simSTOP (1 << 0) /* 0 = execute; 1 = stop simulation */
-#define simSTEP (1 << 1) /* 0 = run; 1 = single-step */
-#define simHALTEX (1 << 2) /* 0 = run; 1 = halt on exception */
-#define simHALTIN (1 << 3) /* 0 = run; 1 = halt on interrupt */
-#define simTRACE (1 << 8) /* 0 = do nothing; 1 = trace address activity */
-#define simPROFILE (1 << 9) /* 0 = do nothing; 1 = gather profiling samples */
-#define simHOSTBE (1 << 10) /* 0 = little-endian; 1 = big-endian (host endianness) */
-/* Whilst simSTOP is not set, the simulator control loop should just
- keep simulating instructions. The simSTEP flag is used to force
- single-step execution. */
-#define simBE (1 << 16) /* 0 = little-endian; 1 = big-endian (target endianness) */
-#define simPCOC0 (1 << 17) /* COC[1] from current */
-#define simPCOC1 (1 << 18) /* COC[1] from previous */
-#define simDELAYSLOT (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
-#define simSKIPNEXT (1 << 25) /* 0 = do nothing; 1 = skip instruction */
-#define simEXCEPTION (1 << 26) /* 0 = no exception; 1 = exception has occurred */
-#define simEXIT (1 << 27) /* 0 = do nothing; 1 = run-time exit() processing */
-
-unsigned int state = (0 | simBE); /* big-endian simulator by default */
-unsigned int rcexit = 0; /* _exit() reason code holder */
#define DELAYSLOT() {\
- if (state & simDELAYSLOT) callback->printf_filtered(callback,"SIM Warning: Delay slot already activated (branch in delay slot?)\n");\
- state |= simDELAYSLOT;\
+ if (STATE & simDELAYSLOT)\
+ sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\
+ STATE |= simDELAYSLOT;\
}
+#define JALDELAYSLOT() {\
+ DELAYSLOT ();\
+ STATE |= simJALDELAYSLOT;\
+ }
+
#define NULLIFY() {\
- state &= ~simDELAYSLOT;\
- state |= simSKIPNEXT;\
+ STATE &= ~simDELAYSLOT;\
+ STATE |= simSKIPNEXT;\
}
+#define CANCELDELAYSLOT() {\
+ DSSTATE = 0;\
+ STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\
+ }
+
+#define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0)
+#define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
+
#define K0BASE (0x80000000)
#define K0SIZE (0x20000000)
#define K1BASE (0xA0000000)
#define K1SIZE (0x20000000)
+#define MONITOR_BASE (0xBFC00000)
+#define MONITOR_SIZE (1 << 11)
+#define MEM_SIZE (2 << 20)
+
+/* start-sanitize-sky */
+#ifdef TARGET_SKY
+#undef MEM_SIZE
+#define MEM_SIZE (16 << 20) /* 16 MB */
+#endif
+/* end-sanitize-sky */
+
+#if defined(TRACE)
+static char *tracefile = "trace.din"; /* default filename for trace log */
+FILE *tracefh = NULL;
+static void open_trace PARAMS((SIM_DESC sd));
+#endif /* TRACE */
-/* Very simple memory model to start with: */
-unsigned char *membank = NULL;
-ut_reg membank_base = K1BASE;
-unsigned membank_size = (1 << 20); /* (16 << 20); */ /* power-of-2 */
+static DECLARE_OPTION_HANDLER (mips_option_handler);
-/* Simple run-time monitor support */
-unsigned char *monitor = NULL;
-ut_reg monitor_base = 0xBFC00000;
-unsigned monitor_size = (1 << 11); /* power-of-2 */
+enum {
+ OPTION_DINERO_TRACE = OPTION_START,
+ OPTION_DINERO_FILE
+/* start-sanitize-sky */
+#ifdef TARGET_SKY
+#ifdef SKY_FUNIT
+ ,OPTION_FLOAT_TYPE
+#endif
+ ,OPTION_GS_ENABLE
+ ,OPTION_GS_REFRESH1
+ ,OPTION_GS_REFRESH2
+#endif
+/* end-sanitize-sky */
+};
+static SIM_RC
+mips_option_handler (sd, cpu, opt, arg, is_command)
+ SIM_DESC sd;
+ sim_cpu *cpu;
+ int opt;
+ char *arg;
+ int is_command;
+{
+ int cpu_nr;
+ switch (opt)
+ {
+ case OPTION_DINERO_TRACE: /* ??? */
#if defined(TRACE)
-char *tracefile = "trace.din"; /* default filename for trace log */
-FILE *tracefh = NULL;
+ /* Eventually the simTRACE flag could be treated as a toggle, to
+ allow external control of the program points being traced
+ (i.e. only from main onwards, excluding the run-time setup,
+ etc.). */
+ for (cpu_nr = 0; cpu_nr < MAX_NR_PROCESSORS; cpu_nr++)
+ {
+ sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
+ if (arg == NULL)
+ STATE |= simTRACE;
+ else if (strcmp (arg, "yes") == 0)
+ STATE |= simTRACE;
+ else if (strcmp (arg, "no") == 0)
+ STATE &= ~simTRACE;
+ else if (strcmp (arg, "on") == 0)
+ STATE |= simTRACE;
+ else if (strcmp (arg, "off") == 0)
+ STATE &= ~simTRACE;
+ else
+ {
+ fprintf (stderr, "Unrecognized dinero-trace option `%s'\n", arg);
+ return SIM_RC_FAIL;
+ }
+ }
+ return SIM_RC_OK;
+#else /* !TRACE */
+ fprintf(stderr,"\
+Simulator constructed without dinero tracing support (for performance).\n\
+Re-compile simulator with \"-DTRACE\" to enable this option.\n");
+ return SIM_RC_FAIL;
+#endif /* !TRACE */
+
+ case OPTION_DINERO_FILE:
+#if defined(TRACE)
+ if (optarg != NULL) {
+ char *tmp;
+ tmp = (char *)malloc(strlen(optarg) + 1);
+ if (tmp == NULL)
+ {
+ sim_io_printf(sd,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg);
+ return SIM_RC_FAIL;
+ }
+ else {
+ strcpy(tmp,optarg);
+ tracefile = tmp;
+ sim_io_printf(sd,"Placing trace information into file \"%s\"\n",tracefile);
+ }
+ }
#endif /* TRACE */
+ return SIM_RC_OK;
+
+/* start-sanitize-sky */
+#ifdef TARGET_SKY
+#ifdef SKY_FUNIT
+ case OPTION_FLOAT_TYPE:
+ /* Use host (fast) or target (accurate) floating point implementation. */
+ if (arg && strcmp (arg, "host") == 0)
+ STATE_FP_TYPE_OPT (sd) &= ~STATE_FP_TYPE_OPT_TARGET;
+ else if (arg && strcmp (arg, "target") == 0)
+ STATE_FP_TYPE_OPT (sd) |= STATE_FP_TYPE_OPT_TARGET;
+ else
+ {
+ fprintf (stderr, "Unrecognized float-type option `%s'\n", arg);
+ return SIM_RC_FAIL;
+ }
+ /*printf ("float-type=0x%08x\n", STATE_FP_TYPE_OPT (sd));*/
+ return SIM_RC_OK;
+#endif
+
+ case OPTION_GS_ENABLE:
+ /* Enable GS libraries. */
+ if ( arg && strcmp (arg, "on") == 0 )
+ gif_options (&gif_full,GIF_OPT_GS_ENABLE,1,0,0);
+ else if ( arg && strcmp (arg, "off") == 0 )
+ gif_options (&gif_full,GIF_OPT_GS_ENABLE,0,0,0);
+ else
+ {
+ fprintf (stderr, "Unrecognized enable-gs option `%s'\n", arg);
+ return SIM_RC_FAIL;
+ }
+ return SIM_RC_OK;
+
+ case OPTION_GS_REFRESH1:
+ case OPTION_GS_REFRESH2:
+ {
+ /* The GS has defineable register and register values. */
+ unsigned_4 address[2];
+ long long value[2];
+ char c[3];
+
+ if ( arg && strlen (arg) == 59 && arg[10] == '=' &&
+ arg[29] == ':' && arg[40] == '=' &&
+ ( sscanf (arg,"%lx%c%Lx%c%lx%c%Lx", &address[0],&c[0],&value[0],
+ &c[1],&address[1],&c[2],&value[1]) == 7 ))
+ {
+ gif_options (&gif_full, ( opt == OPTION_GS_REFRESH1 ) ?
+ GIF_OPT_GS_REFRESH1:GIF_OPT_GS_REFRESH2,
+ 0,&address[0],&value[0]);
+ }
+ else
+ {
+ fprintf (stderr, "Unrecognized gs-refresh option `%s'\n", arg);
+ return SIM_RC_FAIL;
+ }
+ }
+ return SIM_RC_OK;
+
+#endif
+/* end-sanitize-sky */
+ }
+
+ return SIM_RC_OK;
+}
+
+static const OPTION mips_options[] =
+{
+ { {"dinero-trace", optional_argument, NULL, OPTION_DINERO_TRACE},
+ '\0', "on|off", "Enable dinero tracing",
+ mips_option_handler },
+ { {"dinero-file", required_argument, NULL, OPTION_DINERO_FILE},
+ '\0', "FILE", "Write dinero trace to FILE",
+ mips_option_handler },
+/* start-sanitize-sky */
+#ifdef TARGET_SKY
+#ifdef SKY_FUNIT
+ { {"float-type", required_argument, NULL, OPTION_FLOAT_TYPE},
+ '\0', "host|target", "Use host (fast) or target (accurate) floating point",
+ mips_option_handler },
+#endif
+ { {"enable-gs", required_argument, NULL, OPTION_GS_ENABLE},
+ '\0', "on|off", "Enable GS library routines",
+ mips_option_handler },
+ { {"gs-refresh1", required_argument, NULL, OPTION_GS_REFRESH1},
+ '\0', "0xaddress0=0xvalue0:0xaddress1=0xvalue1", "GS refresh buffer 1 addresses and values",
+ mips_option_handler },
+ { {"gs-refresh2", required_argument, NULL, OPTION_GS_REFRESH2},
+ '\0', "0xaddress0=0xvalue0:0xaddress1=0xvalue1", "GS refresh buffer 2 addresses and values",
+ mips_option_handler },
+#endif
+/* end-sanitize-sky */
+ { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL }
+};
+
+
+int interrupt_pending;
+
+static void
+interrupt_event (SIM_DESC sd, void *data)
+{
+ sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
+ if (SR & status_IE)
+ {
+ interrupt_pending = 0;
+ SignalExceptionInterrupt ();
+ }
+ else if (!interrupt_pending)
+ sim_events_schedule (sd, 1, interrupt_event, data);
+}
-#if defined(PROFILE)
-unsigned profile_frequency = 256;
-unsigned profile_nsamples = (128 << 10);
-unsigned short *profile_hist = NULL;
-ut_reg profile_minpc;
-ut_reg profile_maxpc;
-int profile_shift = 0; /* address shift amount */
-#endif /* PROFILE */
/*---------------------------------------------------------------------------*/
-/*-- GDB simulator interface ------------------------------------------------*/
+/*-- Device registration hook -----------------------------------------------*/
/*---------------------------------------------------------------------------*/
+static void device_init(SIM_DESC sd) {
+#ifdef DEVICE_INIT
+ extern void register_devices(SIM_DESC);
+ register_devices(sd);
+#endif
+}
-static void dotrace PARAMS((FILE *tracefh,int type,unsigned int address,int width,char *comment,...));
-extern void sim_error PARAMS((char *fmt,...));
-static void ColdReset PARAMS((void));
-static int AddressTranslation PARAMS((uword64 vAddr,int IorD,int LorS,uword64 *pAddr,int *CCA,int host,int raw));
-static void StoreMemory PARAMS((int CCA,int AccessLength,uword64 MemElem,uword64 pAddr,uword64 vAddr,int raw));
-static uword64 LoadMemory PARAMS((int CCA,int AccessLength,uword64 pAddr,uword64 vAddr,int IorD,int raw));
-static void SignalException PARAMS((int exception,...));
-static void simulate PARAMS((void));
-static long getnum(char *value);
-extern void sim_size(unsigned int newsize);
-extern void sim_set_profile(int frequency);
-static unsigned int power2(unsigned int value);
+/*---------------------------------------------------------------------------*/
+/*-- GDB simulator interface ------------------------------------------------*/
+/*---------------------------------------------------------------------------*/
-void
-sim_open (args)
- char *args;
+SIM_DESC
+sim_open (kind, cb, abfd, argv)
+ SIM_OPEN_KIND kind;
+ host_callback *cb;
+ struct _bfd *abfd;
+ char **argv;
{
- if (callback == NULL) {
- fprintf(stderr,"SIM Error: sim_open() called without callbacks attached\n");
- return;
- }
+ SIM_DESC sd = sim_state_alloc (kind, cb);
+ sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
- /* The following ensures that the standard file handles for stdin,
- stdout and stderr are initialised: */
- callback->init(callback);
+ SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
+/* start-sanitize-sky */
- state = 0;
- CHECKSIM();
- if (state & simEXCEPTION) {
- fprintf(stderr,"This simulator is not suitable for this host configuration\n");
- exit(1);
- }
+#if defined(TARGET_SKY) && defined(SKY_FUNIT)
+ /* Set "--float-type host" as the default. */
+ STATE_FP_TYPE_OPT (sd) &= ~STATE_FP_TYPE_OPT_TARGET;
+#endif
+/* end-sanitize-sky */
+
+ /* FIXME: watchpoints code shouldn't need this */
+ STATE_WATCHPOINTS (sd)->pc = &(PC);
+ STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
+ STATE_WATCHPOINTS (sd)->interrupt_handler = interrupt_event;
+
+ STATE = 0;
+
+ if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
+ return 0;
+ sim_add_option_table (sd, NULL, mips_options);
+
+ /* Allocate core managed memory */
+
+ /* the monitor */
+ sim_do_commandf (sd, "memory region 0x%lx,0x%lx", MONITOR_BASE, MONITOR_SIZE);
+ /* For compatibility with the old code - under this (at level one)
+ are the kernel spaces K0 & K1. Both of these map to a single
+ smaller sub region */
+ sim_do_command(sd," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
+/* start-sanitize-sky */
+#ifndef TARGET_SKY
+/* end-sanitize-sky */
+ sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
+ K1BASE, K0SIZE,
+ MEM_SIZE, /* actual size */
+ K0BASE);
+/* start-sanitize-sky */
+#else
+ sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x,0x%0x",
+ K1BASE, K0SIZE,
+ MEM_SIZE, /* actual size */
+ K0BASE,
+ 0); /* add alias at 0x0000 */
+#endif
+/* end-sanitize-sky */
- {
- int data = 0x12;
- if (*((char *)&data) != 0x12)
- state |= simHOSTBE; /* big-endian host */
- }
+ device_init(sd);
-#if defined(HASFPU)
- /* Check that the host FPU conforms to IEEE 754-1985 for the SINGLE
- and DOUBLE binary formats. This is a bit nasty, requiring that we
- trust the explicit manifests held in the source: */
- {
- unsigned int s[2];
- s[state & simHOSTBE ? 0 : 1] = 0x40805A5A;
- s[state & simHOSTBE ? 1 : 0] = 0x00000000;
-
- /* TODO: We need to cope with the simulated target and the host
- not having the same endianness. This will require the high and
- low words of a (double) to be swapped when converting between
- the host and the simulated target. */
-
- if (((float)4.01102924346923828125 != *(float *)(s + ((state & simHOSTBE) ? 0 : 1))) || ((double)523.2939453125 != *(double *)s)) {
- fprintf(stderr,"The host executing the simulator does not seem to have IEEE 754-1985 std FP\n");
- fprintf(stderr,"*(float *)s = %.20f (4.01102924346923828125)\n",*(float *)s);
- fprintf(stderr,"*(double *)s = %.20f (523.2939453125)\n",*(double *)s);
- exit(1);
+ /* getopt will print the error message so we just have to exit if this fails.
+ FIXME: Hmmm... in the case of gdb we need getopt to call
+ print_filtered. */
+ if (sim_parse_args (sd, argv) != SIM_RC_OK)
+ {
+ /* Uninstall the modules to avoid memory leaks,
+ file descriptor leaks, etc. */
+ sim_module_uninstall (sd);
+ return 0;
}
- }
-#endif /* HASFPU */
- /* This is NASTY, in that we are assuming the size of specific
- registers: */
- {
- int rn;
- for (rn = 0; (rn < (LAST_EMBED_REGNUM + 1)); rn++) {
- if (rn < 32)
- register_widths[rn] = GPRLEN;
- else if ((rn >= FGRIDX) && (rn < (FGRIDX + 32)))
- register_widths[rn] = GPRLEN;
- else if ((rn >= 33) && (rn <= 37))
- register_widths[rn] = GPRLEN;
- else if ((rn == SRIDX) || (rn == FCR0IDX) || (rn == FCR31IDX) || ((rn >= 72) && (rn <= 89)))
- register_widths[rn] = 32;
- else
- register_widths[rn] = 0;
+ /* check for/establish the a reference program image */
+ if (sim_analyze_program (sd,
+ (STATE_PROG_ARGV (sd) != NULL
+ ? *STATE_PROG_ARGV (sd)
+ : NULL),
+ abfd) != SIM_RC_OK)
+ {
+ sim_module_uninstall (sd);
+ return 0;
}
- }
- /* It would be good if we could select particular named MIPS
- architecture simulators. However, having a pre-built, fixed
- engine would mean including multiple engines. If the simulator is
- changed to a run-time conditional version, then the ability to
- select a particular architecture would be straightforward. */
- if (args != NULL) {
- int c;
- char *cline;
- char **argv;
- int argc;
- static struct option cmdline[] = {
- {"help", 0,0,'h'},
- {"name", 1,0,'n'},
- {"profile", 0,0,'p'},
- {"size", 1,0,'s'},
- {"trace", 0,0,'t'},
- {"tracefile",1,0,'z'},
- {"frequency",1,0,'y'},
- {"samples", 1,0,'x'},
- {0, 0,0,0}
- };
-
- /* Unfortunately, getopt_long() is designed to be used with
- vectors, where the first option is normally program name (and
- ignored). We cheat by creating a dummy first argument, so that
- we can use the standard argument processing. */
-#define DUMMYARG "simulator "
- cline = (char *)malloc(strlen(args) + strlen(DUMMYARG) + 1);
- if (cline == NULL) {
- fprintf(stderr,"Failed to allocate memory for command line buffer\n");
- exit(1);
+ /* Configure/verify the target byte order and other runtime
+ configuration options */
+ if (sim_config (sd) != SIM_RC_OK)
+ {
+ sim_module_uninstall (sd);
+ return 0;
}
- sprintf(cline,"%s%s",DUMMYARG,args);
- argv = buildargv(cline);
- for (argc = 0; argv[argc]; argc++);
- /* Unfortunately, getopt_long() assumes that it is ignoring the
- first argument (normally the program name). This means it
- ignores the first option on our "args" line. */
- optind = 0; /* Force reset of argument processing */
- while (1) {
- int option_index = 0;
+ if (sim_post_argv_init (sd) != SIM_RC_OK)
+ {
+ /* Uninstall the modules to avoid memory leaks,
+ file descriptor leaks, etc. */
+ sim_module_uninstall (sd);
+ return 0;
+ }
- c = getopt_long(argc,argv,"hn:s:tp",cmdline,&option_index);
- if (c == -1)
- break;
+ /* verify assumptions the simulator made about the host type system.
+ This macro does not return if there is a problem */
+ SIM_ASSERT (sizeof(int) == (4 * sizeof(char)));
+ SIM_ASSERT (sizeof(word64) == (8 * sizeof(char)));
- switch (c) {
- case 'h':
- callback->printf_filtered(callback,"Usage:\n\t\
-target sim [-h] [--name=<model>] [--size=<amount>]");
-#if defined(TRACE)
- callback->printf_filtered(callback," [-t [--tracefile=<name>]]");
-#endif /* TRACE */
-#if defined(PROFILE)
- callback->printf_filtered(callback," [-p [--frequency=<count>] [--samples=<count>]]");
-#endif /* PROFILE */
- callback->printf_filtered(callback,"\n");
- break;
+ /* This is NASTY, in that we are assuming the size of specific
+ registers: */
+ {
+ int rn;
+ for (rn = 0; (rn < (LAST_EMBED_REGNUM + 1)); rn++)
+ {
+ if (rn < 32)
+ cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
+ else if ((rn >= FGRIDX) && (rn < (FGRIDX + NR_FGR)))
+ cpu->register_widths[rn] = WITH_TARGET_FLOATING_POINT_BITSIZE;
+ else if ((rn >= 33) && (rn <= 37))
+ cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
+ else if ((rn == SRIDX)
+ || (rn == FCR0IDX)
+ || (rn == FCR31IDX)
+ || ((rn >= 72) && (rn <= 89)))
+ cpu->register_widths[rn] = 32;
+ else
+ cpu->register_widths[rn] = 0;
+ }
+ /* start-sanitize-r5900 */
+
+ /* set the 5900 "upper" registers to 64 bits */
+ for( rn = LAST_EMBED_REGNUM+1; rn < NUM_REGS; rn++)
+ cpu->register_widths[rn] = 64;
+ /* end-sanitize-r5900 */
+
+ /* start-sanitize-sky */
+#ifdef TARGET_SKY
+ /* Now the VU registers */
+ for( rn = 0; rn < NUM_VU_INTEGER_REGS; rn++ ) {
+ cpu->register_widths[rn + NUM_R5900_REGS] = 16;
+ cpu->register_widths[rn + NUM_R5900_REGS + NUM_VU_REGS] = 16;
+ }
- case 'n':
- callback->printf_filtered(callback,"Explicit model selection not yet available (Ignoring \"%s\")\n",optarg);
- break;
+ for( rn = NUM_VU_INTEGER_REGS; rn < NUM_VU_REGS; rn++ ) {
+ cpu->register_widths[rn + NUM_R5900_REGS] = 32;
+ cpu->register_widths[rn + NUM_R5900_REGS + NUM_VU_REGS] = 32;
+ }
- case 's':
- membank_size = (unsigned)getnum(optarg);
- break;
+ /* Finally the VIF registers */
+ for( rn = 2*NUM_VU_REGS; rn < 2*NUM_VU_REGS + 2*NUM_VIF_REGS; rn++ )
+ cpu->register_widths[rn + NUM_R5900_REGS] = 32;
- case 't':
-#if defined(TRACE)
- /* Eventually the simTRACE flag could be treated as a toggle, to
- allow external control of the program points being traced
- (i.e. only from main onwards, excluding the run-time setup,
- etc.). */
- state |= simTRACE;
-#else /* !TRACE */
- fprintf(stderr,"\
-Simulator constructed without tracing support (for performance).\n\
-Re-compile simulator with \"-DTRACE\" to enable this option.\n");
-#endif /* !TRACE */
- break;
+ cpu->cur_device = 0;
+#endif
+ /* end-sanitize-sky */
+ }
- case 'z':
#if defined(TRACE)
- if (optarg != NULL) {
- char *tmp;
- tmp = (char *)malloc(strlen(optarg) + 1);
- if (tmp == NULL)
- callback->printf_filtered(callback,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg);
- else {
- strcpy(tmp,optarg);
- tracefile = tmp;
- callback->printf_filtered(callback,"Placing trace information into file \"%s\"\n",tracefile);
- }
- }
+ if (STATE & simTRACE)
+ open_trace(sd);
#endif /* TRACE */
- break;
-
- case 'p':
-#if defined(PROFILE)
- state |= simPROFILE;
-#else /* !PROFILE */
- fprintf(stderr,"\
-Simulator constructed without profiling support (for performance).\n\
-Re-compile simulator with \"-DPROFILE\" to enable this option.\n");
-#endif /* !PROFILE */
- break;
-
- case 'x':
-#if defined(PROFILE)
- profile_nsamples = (unsigned)getnum(optarg);
-#endif /* PROFILE */
- break;
-
- case 'y':
-#if defined(PROFILE)
- sim_set_profile((int)getnum(optarg));
-#endif /* PROFILE */
- break;
-
- default:
- callback->printf_filtered(callback,"Warning: Simulator getopt returned unrecognised code 0x%08X\n",c);
- case '?':
- break;
- }
- }
-
- if (optind < argc) {
- callback->printf_filtered(callback,"Warning: Ignoring spurious non-option arguments ");
- while (optind < argc)
- callback->printf_filtered(callback,"\"%s\" ",argv[optind++]);
- callback->printf_filtered(callback,"\n");
- }
- freeargv(argv);
+ /* Write an abort sequence into the TRAP (common) exception vector
+ addresses. This is to catch code executing a TRAP (et.al.)
+ instruction without installing a trap handler. */
+ {
+ unsigned32 halt[2] = { 0x2404002f /* addiu r4, r0, 47 */,
+ HALT_INSTRUCTION /* BREAK */ };
+ H2T (halt[0]);
+ H2T (halt[1]);
+ sim_write (sd, 0x80000180, (char *) halt, sizeof (halt));
+ sim_write (sd, 0xBFC00380, (char *) halt, sizeof (halt));
}
- /* If the host has "mmap" available we could use it to provide a
- very large virtual address space for the simulator, since memory
- would only be allocated within the "mmap" space as it is
- accessed. This can also be linked to the architecture specific
- support, required to simulate the MMU. */
- sim_size(membank_size);
- /* NOTE: The above will also have enabled any profiling state */
-
- ColdReset();
- /* If we were providing a more complete I/O, co-processor or memory
- simulation, we should perform any "device" initialisation at this
- point. This can include pre-loading memory areas with particular
- patterns (e.g. simulating ROM monitors). */
-
- /* We can start writing to the memory, now that the processor has
- been reset: */
- monitor = (unsigned char *)calloc(1,monitor_size);
- if (!monitor) {
- fprintf(stderr,"Not enough VM for monitor simulation (%d bytes)\n",monitor_size);
- } else {
- int loop;
+
+ /* Write the monitor trap address handlers into the monitor (eeprom)
+ address space. This can only be done once the target endianness
+ has been determined. */
+ {
+ unsigned loop;
/* Entry into the IDT monitor is via fixed address vectors, and
not using machine instructions. To avoid clashing with use of
the MIPS TRAP system, we place our own (simulator specific)
"undefined" instructions into the relevant vector slots. */
- for (loop = 0; (loop < monitor_size); loop += 4) {
- uword64 vaddr = (monitor_base + loop);
- uword64 paddr;
- int cca;
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isRAW))
- StoreMemory(cca,AccessLength_WORD,(RSVD_INSTRUCTION | ((loop >> 2) & RSVD_INSTRUCTION_AMASK)),paddr,vaddr,isRAW);
- }
+ for (loop = 0; (loop < MONITOR_SIZE); loop += 4)
+ {
+ address_word vaddr = (MONITOR_BASE + loop);
+ unsigned32 insn = (RSVD_INSTRUCTION | (((loop >> 2) & RSVD_INSTRUCTION_ARG_MASK) << RSVD_INSTRUCTION_ARG_SHIFT));
+ H2T (insn);
+ sim_write (sd, vaddr, (char *)&insn, sizeof (insn));
+ }
/* The PMON monitor uses the same address space, but rather than
branching into it the address of a routine is loaded. We can
cheat for the moment, and direct the PMON routine to IDT style
entry points.*/
for (loop = 0; (loop < 24); loop++)
{
- uword64 vaddr = (monitor_base + 0x500 + (loop * 4));
- uword64 paddr;
- int cca;
- unsigned int value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */
+ address_word vaddr = (MONITOR_BASE + 0x500 + (loop * 4));
+ unsigned32 value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */
switch (loop)
{
case 0: /* read */
value = 7;
break;
-
case 1: /* write */
value = 8;
break;
-
case 2: /* open */
value = 6;
break;
-
case 3: /* close */
value = 10;
break;
-
case 5: /* printf */
value = ((0x500 - 16) / 8); /* not an IDT reason code */
break;
-
case 8: /* cliexit */
value = 17;
break;
+ case 11: /* flush_cache */
+ value = 28;
+ break;
}
- value = (monitor_base + (value * 8));
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isRAW))
- StoreMemory(cca,AccessLength_WORD,value,paddr,vaddr,isRAW);
- else
- callback->printf_filtered(callback,"Failed to write to monitor space 0x%08X%08X\n",WORD64HI(vaddr),WORD64LO(vaddr));
+ /* FIXME - should monitor_base be SIM_ADDR?? */
+ value = ((unsigned int)MONITOR_BASE + (value * 8));
+ H2T (value);
+ sim_write (sd, vaddr, (char *)&value, sizeof (value));
+
+ /* The LSI MiniRISC PMON has its vectors at 0x200, not 0x500. */
+ vaddr -= 0x300;
+ sim_write (sd, vaddr, (char *)&value, sizeof (value));
}
}
-#if defined(TRACE)
- if (state & simTRACE) {
- tracefh = fopen(tracefile,"wb+");
- if (tracefh == NULL) {
- callback->printf_filtered(callback,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile);
- tracefh = stderr;
- }
- }
-#endif /* TRACE */
-
- return;
-}
-
-/* For the profile writing, we write the data in the host
- endianness. This unfortunately means we are assuming that the
- profile file we create is processed on the same host executing the
- simulator. The gmon.out file format should either have an explicit
- endianness, or a method of encoding the endianness in the file
- header. */
-static int
-writeout32(fh,val)
- FILE *fh;
- unsigned int val;
-{
- char buff[4];
- int res = 1;
-
- if (state & simHOSTBE) {
- buff[3] = ((val >> 0) & 0xFF);
- buff[2] = ((val >> 8) & 0xFF);
- buff[1] = ((val >> 16) & 0xFF);
- buff[0] = ((val >> 24) & 0xFF);
- } else {
- buff[0] = ((val >> 0) & 0xFF);
- buff[1] = ((val >> 8) & 0xFF);
- buff[2] = ((val >> 16) & 0xFF);
- buff[3] = ((val >> 24) & 0xFF);
- }
- if (fwrite(buff,4,1,fh) != 1) {
- callback->printf_filtered(callback,"Failed to write 4bytes to the profile file\n");
- res = 0;
- }
- return(res);
+ return sd;
}
-static int
-writeout16(fh,val)
- FILE *fh;
- unsigned short val;
+#if defined(TRACE)
+static void
+open_trace(sd)
+ SIM_DESC sd;
{
- char buff[2];
- int res = 1;
- if (state & simHOSTBE) {
- buff[1] = ((val >> 0) & 0xFF);
- buff[0] = ((val >> 8) & 0xFF);
- } else {
- buff[0] = ((val >> 0) & 0xFF);
- buff[1] = ((val >> 8) & 0xFF);
- }
- if (fwrite(buff,2,1,fh) != 1) {
- callback->printf_filtered(callback,"Failed to write 2bytes to the profile file\n");
- res = 0;
+ tracefh = fopen(tracefile,"wb+");
+ if (tracefh == NULL)
+ {
+ sim_io_eprintf(sd,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile);
+ tracefh = stderr;
}
- return(res);
}
+#endif /* TRACE */
void
-sim_close (quitting)
+sim_close (sd, quitting)
+ SIM_DESC sd;
int quitting;
{
#ifdef DEBUG
printf("DBG: sim_close: entered (quitting = %d)\n",quitting);
#endif
- /* Cannot assume sim_kill() has been called */
/* "quitting" is non-zero if we cannot hang on errors */
/* Ensure that any resources allocated through the callback
mechanism are released: */
- callback->shutdown(callback);
-
-#if defined(PROFILE)
- if ((state & simPROFILE) && (profile_hist != NULL)) {
- unsigned short *p = profile_hist;
- FILE *pf = fopen("gmon.out","wb");
- int loop;
-
- if (pf == NULL)
- callback->printf_filtered(callback,"Failed to open \"gmon.out\" profile file\n");
- else {
- int ok;
-#ifdef DEBUG
- printf("DBG: minpc = 0x%08X\n",(unsigned int)profile_minpc);
- printf("DBG: maxpc = 0x%08X\n",(unsigned int)profile_maxpc);
-#endif /* DEBUG */
- ok = writeout32(pf,(unsigned int)profile_minpc);
- if (ok)
- ok = writeout32(pf,(unsigned int)profile_maxpc);
- if (ok)
- ok = writeout32(pf,(profile_nsamples * 2) + 12); /* size of sample buffer (+ header) */
-#ifdef DEBUG
- printf("DBG: nsamples = %d (size = 0x%08X)\n",profile_nsamples,((profile_nsamples * 2) + 12));
-#endif /* DEBUG */
- for (loop = 0; (ok && (loop < profile_nsamples)); loop++) {
- ok = writeout16(pf,profile_hist[loop]);
- if (!ok)
- break;
- }
-
- fclose(pf);
- }
-
- free(profile_hist);
- profile_hist = NULL;
- state &= ~simPROFILE;
- }
-#endif /* PROFILE */
+ sim_io_shutdown (sd);
#if defined(TRACE)
- if (tracefh != stderr)
+ if (tracefh != NULL && tracefh != stderr)
fclose(tracefh);
- state &= ~simTRACE;
+ tracefh = NULL;
#endif /* TRACE */
- if (membank)
- free(membank); /* cfree not available on all hosts */
- membank = NULL;
+ /* FIXME - free SD */
return;
}
-void
-sim_resume (step,signal)
- int step, signal;
-{
-#ifdef DEBUG
- printf("DBG: sim_resume entered: step = %d, signal = %d (membank = 0x%08X)\n",step,signal,membank);
-#endif /* DEBUG */
-
- if (step)
- state |= simSTEP; /* execute only a single instruction */
- else
- state &= ~(simSTOP | simSTEP); /* execute until event */
-
- state |= (simHALTEX | simHALTIN); /* treat interrupt event as exception */
-
- /* Start executing instructions from the current state (set
- explicitly by register updates, or by sim_create_inferior): */
-
- simulate();
- return;
-}
int
-sim_write (addr,buffer,size)
+sim_write (sd,addr,buffer,size)
+ SIM_DESC sd;
SIM_ADDR addr;
unsigned char *buffer;
int size;
{
- int index = size;
- uword64 vaddr = (uword64)addr;
+ int index;
+ sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
/* Return the number of bytes written, or zero if error. */
#ifdef DEBUG
- callback->printf_filtered(callback,"sim_write(0x%08X%08X,buffer,%d);\n",WORD64HI(addr),WORD64LO(addr),size);
+ sim_io_printf(sd,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr),size);
#endif
- /* We provide raw read and write routines, since we do not want to
- count the GDB memory accesses in our statistics gathering. */
-
- /* There is a lot of code duplication in the individual blocks
- below, but the variables are declared locally to a block to give
- the optimiser the best chance of improving the code. We have to
- perform slow byte reads from the host memory, to ensure that we
- get the data into the correct endianness for the (simulated)
- target memory world. */
-
- /* Mask count to get odd byte, odd halfword, and odd word out of the
- way. We can then perform doubleword transfers to and from the
- simulator memory for optimum performance. */
- if (index && (index & 1)) {
- uword64 paddr;
- int cca;
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isRAW)) {
- uword64 value = ((uword64)(*buffer++));
- StoreMemory(cca,AccessLength_BYTE,value,paddr,vaddr,isRAW);
- }
- vaddr++;
- index &= ~1; /* logical operations usually quicker than arithmetic on RISC systems */
- }
- if (index && (index & 2)) {
- uword64 paddr;
- int cca;
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isRAW)) {
- uword64 value;
- /* We need to perform the following magic to ensure that that
- bytes are written into same byte positions in the target memory
- world, regardless of the endianness of the host. */
- if (BigEndianMem) {
- value = ((uword64)(*buffer++) << 8);
- value |= ((uword64)(*buffer++) << 0);
- } else {
- value = ((uword64)(*buffer++) << 0);
- value |= ((uword64)(*buffer++) << 8);
- }
- StoreMemory(cca,AccessLength_HALFWORD,value,paddr,vaddr,isRAW);
- }
- vaddr += 2;
- index &= ~2;
- }
- if (index && (index & 4)) {
- uword64 paddr;
- int cca;
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isRAW)) {
- uword64 value;
- if (BigEndianMem) {
- value = ((uword64)(*buffer++) << 24);
- value |= ((uword64)(*buffer++) << 16);
- value |= ((uword64)(*buffer++) << 8);
- value |= ((uword64)(*buffer++) << 0);
- } else {
- value = ((uword64)(*buffer++) << 0);
- value |= ((uword64)(*buffer++) << 8);
- value |= ((uword64)(*buffer++) << 16);
- value |= ((uword64)(*buffer++) << 24);
- }
- StoreMemory(cca,AccessLength_WORD,value,paddr,vaddr,isRAW);
- }
- vaddr += 4;
- index &= ~4;
- }
- for (;index; index -= 8) {
- uword64 paddr;
- int cca;
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isRAW)) {
- uword64 value;
- if (BigEndianMem) {
- value = ((uword64)(*buffer++) << 56);
- value |= ((uword64)(*buffer++) << 48);
- value |= ((uword64)(*buffer++) << 40);
- value |= ((uword64)(*buffer++) << 32);
- value |= ((uword64)(*buffer++) << 24);
- value |= ((uword64)(*buffer++) << 16);
- value |= ((uword64)(*buffer++) << 8);
- value |= ((uword64)(*buffer++) << 0);
- } else {
- value = ((uword64)(*buffer++) << 0);
- value |= ((uword64)(*buffer++) << 8);
- value |= ((uword64)(*buffer++) << 16);
- value |= ((uword64)(*buffer++) << 24);
- value |= ((uword64)(*buffer++) << 32);
- value |= ((uword64)(*buffer++) << 40);
- value |= ((uword64)(*buffer++) << 48);
- value |= ((uword64)(*buffer++) << 56);
- }
- StoreMemory(cca,AccessLength_DOUBLEWORD,value,paddr,vaddr,isRAW);
+ /* We use raw read and write routines, since we do not want to count
+ the GDB memory accesses in our statistics gathering. */
+
+ for (index = 0; index < size; index++)
+ {
+ address_word vaddr = (address_word)addr + index;
+ address_word paddr;
+ int cca;
+ if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isSTORE, &paddr, &cca, isRAW))
+ break;
+ if (sim_core_write_buffer (SD, CPU, read_map, buffer + index, paddr, 1) != 1)
+ break;
}
- vaddr += 8;
- }
- return(size);
+ return(index);
}
int
-sim_read (addr,buffer,size)
+sim_read (sd,addr,buffer,size)
+ SIM_DESC sd;
SIM_ADDR addr;
unsigned char *buffer;
int size;
{
int index;
+ sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
/* Return the number of bytes read, or zero if error. */
#ifdef DEBUG
- callback->printf_filtered(callback,"sim_read(0x%08X%08X,buffer,%d);\n",WORD64HI(addr),WORD64LO(addr),size);
+ sim_io_printf(sd,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr),size);
#endif /* DEBUG */
- /* TODO: Perform same optimisation as the sim_write() code
- above. NOTE: This will require a bit more work since we will need
- to ensure that the source physical address is doubleword aligned
- before, and then deal with trailing bytes. */
- for (index = 0; (index < size); index++) {
- uword64 vaddr,paddr,value;
- int cca;
- vaddr = (uword64)addr + index;
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&cca,isTARGET,isRAW)) {
- value = LoadMemory(cca,AccessLength_BYTE,paddr,vaddr,isDATA,isRAW);
- buffer[index] = (unsigned char)(value&0xFF);
- } else
- break;
- }
+ for (index = 0; (index < size); index++)
+ {
+ address_word vaddr = (address_word)addr + index;
+ address_word paddr;
+ int cca;
+ if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isLOAD, &paddr, &cca, isRAW))
+ break;
+ if (sim_core_read_buffer (SD, CPU, read_map, buffer + index, paddr, 1) != 1)
+ break;
+ }
return(index);
}
-void
-sim_store_register (rn,memory)
+int
+sim_store_register (sd,rn,memory,length)
+ SIM_DESC sd;
int rn;
unsigned char *memory;
+ int length;
{
+ sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
+ /* NOTE: gdb (the client) stores registers in target byte order
+ while the simulator uses host byte order */
#ifdef DEBUG
- callback->printf_filtered(callback,"sim_store_register(%d,*memory=0x%08X%08X);\n",rn,*((unsigned int *)memory),*((unsigned int *)(memory + 4)));
+ sim_io_printf(sd,"sim_store_register(%d,*memory=0x%s);\n",rn,pr_addr(*((SIM_ADDR *)memory)));
#endif /* DEBUG */
/* Unfortunately this suffers from the same problem as the register
numbering one. We need to know what the width of each logical
register number is for the architecture being simulated. */
- if (register_widths[rn] == 0)
- callback->printf_filtered(callback,"Warning: Invalid register width for %d (register store ignored)\n",rn);
- else {
- if (register_widths[rn] == 32)
- registers[rn] = *((unsigned int *)memory);
- else
- registers[rn] = *((uword64 *)memory);
- }
- return;
+ if (cpu->register_widths[rn] == 0)
+ {
+ sim_io_eprintf(sd,"Invalid register width for %d (register store ignored)\n",rn);
+ return 0;
+ }
+
+ /* start-sanitize-r5900 */
+ if (rn >= 90 && rn < 90 + 32)
+ {
+ GPR1[rn - 90] = T2H_8 (*(unsigned64*)memory);
+ return 8;
+ }
+ switch (rn)
+ {
+ case REGISTER_SA:
+ SA = T2H_8(*(unsigned64*)memory);
+ return 8;
+ case 122: /* FIXME */
+ LO1 = T2H_8(*(unsigned64*)memory);
+ return 8;
+ case 123: /* FIXME */
+ HI1 = T2H_8(*(unsigned64*)memory);
+ return 8;
+ }
+ /* end-sanitize-r5900 */
+
+ /* start-sanitize-sky */
+#ifdef TARGET_SKY
+ if (rn >= NUM_R5900_REGS)
+ {
+ rn = rn - NUM_R5900_REGS;
+
+ if( rn < NUM_VU_REGS )
+ {
+ if (rn < NUM_VU_INTEGER_REGS)
+ return write_vu_int_reg (&(vu0_device.regs), rn, memory);
+ else if (rn >= FIRST_VEC_REG)
+ {
+ rn -= FIRST_VEC_REG;
+ return write_vu_vec_reg (&(vu0_device.regs), rn>>2, rn&3,
+ memory);
+ }
+ else switch (rn - NUM_VU_INTEGER_REGS)
+ {
+ case 0:
+ return write_vu_special_reg (&vu0_device, VU_REG_CIA,
+ memory);
+ case 1:
+ return write_vu_misc_reg (&(vu0_device.regs), VU_REG_MR,
+ memory);
+ case 2: /* VU0 has no P register */
+ return 4;
+ case 3:
+ return write_vu_misc_reg (&(vu0_device.regs), VU_REG_MI,
+ memory);
+ case 4:
+ return write_vu_misc_reg (&(vu0_device.regs), VU_REG_MQ,
+ memory);
+ default:
+ return write_vu_acc_reg (&(vu0_device.regs),
+ rn - (NUM_VU_INTEGER_REGS + 5),
+ memory);
+ }
+ }
+
+ rn = rn - NUM_VU_REGS;
+
+ if (rn < NUM_VU_REGS)
+ {
+ if (rn < NUM_VU_INTEGER_REGS)
+ return write_vu_int_reg (&(vu1_device.regs), rn, memory);
+ else if (rn >= FIRST_VEC_REG)
+ {
+ rn -= FIRST_VEC_REG;
+ return write_vu_vec_reg (&(vu1_device.regs),
+ rn >> 2, rn & 3, memory);
+ }
+ else switch (rn - NUM_VU_INTEGER_REGS)
+ {
+ case 0:
+ return write_vu_special_reg (&vu1_device, VU_REG_CIA,
+ memory);
+ case 1:
+ return write_vu_misc_reg (&(vu1_device.regs), VU_REG_MR,
+ memory);
+ case 2:
+ return write_vu_misc_reg (&(vu1_device.regs), VU_REG_MP,
+ memory);
+ case 3:
+ return write_vu_misc_reg (&(vu1_device.regs), VU_REG_MI,
+ memory);
+ case 4:
+ return write_vu_misc_reg (&(vu1_device.regs), VU_REG_MQ,
+ memory);
+ default:
+ return write_vu_acc_reg (&(vu1_device.regs),
+ rn - (NUM_VU_INTEGER_REGS + 5),
+ memory);
+ }
+ }
+
+ rn -= NUM_VU_REGS; /* VIF0 registers are next */
+
+ if (rn < NUM_VIF_REGS)
+ {
+ if (rn < NUM_VIF_REGS-1)
+ return write_pke_reg (&pke0_device, rn, memory);
+ else
+ {
+ sim_io_eprintf( sd, "Can't write vif0_pc (store ignored)\n" );
+ return 0;
+ }
+ }
+
+ rn -= NUM_VIF_REGS; /* VIF1 registers are last */
+
+ if (rn < NUM_VIF_REGS)
+ {
+ if (rn < NUM_VIF_REGS-1)
+ return write_pke_reg (&pke1_device, rn, memory);
+ else
+ {
+ sim_io_eprintf( sd, "Can't write vif1_pc (store ignored)\n" );
+ return 0;
+ }
+ }
+
+ sim_io_eprintf( sd, "Invalid VU register (register store ignored)\n" );
+ return 0;
+ }
+#endif
+ /* end-sanitize-sky */
+
+ if (rn >= FGRIDX && rn < FGRIDX + NR_FGR)
+ {
+ if (cpu->register_widths[rn] == 32)
+ {
+ cpu->fgr[rn - FGRIDX] = T2H_4 (*(unsigned32*)memory);
+ return 4;
+ }
+ else
+ {
+ cpu->fgr[rn - FGRIDX] = T2H_8 (*(unsigned64*)memory);
+ return 8;
+ }
+ }
+
+ if (cpu->register_widths[rn] == 32)
+ {
+ cpu->registers[rn] = T2H_4 (*(unsigned32*)memory);
+ return 4;
+ }
+ else
+ {
+ cpu->registers[rn] = T2H_8 (*(unsigned64*)memory);
+ return 8;
+ }
+
+ return 0;
}
-void
-sim_fetch_register (rn,memory)
+int
+sim_fetch_register (sd,rn,memory,length)
+ SIM_DESC sd;
int rn;
unsigned char *memory;
+ int length;
{
+ sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
+ /* NOTE: gdb (the client) stores registers in target byte order
+ while the simulator uses host byte order */
#ifdef DEBUG
- callback->printf_filtered(callback,"sim_fetch_register(%d=0x%08X%08X,mem) : place simulator registers into memory\n",rn,WORD64HI(registers[rn]),WORD64LO(registers[rn]));
+ sim_io_printf(sd,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn,pr_addr(registers[rn]));
#endif /* DEBUG */
- if (register_widths[rn] == 0)
- callback->printf_filtered(callback,"Warning: Invalid register width for %d (register fetch ignored)\n",rn);
- else {
- if (register_widths[rn] == 32)
- *((unsigned int *)memory) = (registers[rn] & 0xFFFFFFFF);
- else /* 64bit register */
- *((uword64 *)memory) = registers[rn];
- }
- return;
-}
-
-void
-sim_stop_reason (reason,sigrc)
- enum sim_stop *reason;
- int *sigrc;
-{
-/* We can have "*reason = {sim_exited, sim_stopped, sim_signalled}", so
- sim_exited *sigrc = argument to exit()
- sim_stopped *sigrc = exception number
- sim_signalled *sigrc = signal number
-*/
- if (state & simEXCEPTION) {
- /* If "sim_signalled" is used, GDB expects normal SIGNAL numbers,
- and not the MIPS specific exception codes. */
-#if 1
- /* For some reason, sending GDB a sim_signalled reason cause it to
- terminate out. */
- *reason = sim_stopped;
-#else
- *reason = sim_signalled;
-#endif
- switch ((CAUSE >> 2) & 0x1F) {
- case Interrupt:
- *sigrc = SIGINT; /* wrong type of interrupt, but it will do for the moment */
- break;
-
- case TLBModification:
- case TLBLoad:
- case TLBStore:
- case AddressLoad:
- case AddressStore:
- case InstructionFetch:
- case DataReference:
- *sigrc = SIGBUS;
- break;
-
- case ReservedInstruction:
- case CoProcessorUnusable:
- *sigrc = SIGILL;
- break;
-
- case IntegerOverflow:
- case FPE:
- *sigrc = SIGFPE;
- break;
-
- case Trap:
- case Watch:
- case SystemCall:
- case BreakPoint:
- *sigrc = SIGTRAP;
- break;
-
- default : /* Unknown internal exception */
- *sigrc = SIGQUIT;
- break;
+ if (cpu->register_widths[rn] == 0)
+ {
+ sim_io_eprintf (sd, "Invalid register width for %d (register fetch ignored)\n",rn);
+ return 0;
}
- } else if (state & simEXIT) {
- printf("DBG: simEXIT (%d)\n",rcexit);
- *reason = sim_exited;
- *sigrc = rcexit;
- } else { /* assume single-stepping */
- *reason = sim_stopped;
- *sigrc = SIGTRAP;
- }
- state &= ~(simEXCEPTION | simEXIT);
- return;
-}
-void
-sim_info (verbose)
- int verbose;
-{
- /* Accessed from the GDB "info files" command: */
-
- callback->printf_filtered(callback,"MIPS %d-bit simulator\n",(PROCESSOR_64BIT ? 64 : 32));
+ /* start-sanitize-r5900 */
+ if (rn >= 90 && rn < 90 + 32)
+ {
+ *(unsigned64*)memory = GPR1[rn - 90];
+ return 8;
+ }
+ switch (rn)
+ {
+ case REGISTER_SA:
+ *((unsigned64*)memory) = H2T_8(SA);
+ return 8;
+ case 122: /* FIXME */
+ *((unsigned64*)memory) = H2T_8(LO1);
+ return 8;
+ case 123: /* FIXME */
+ *((unsigned64*)memory) = H2T_8(HI1);
+ return 8;
+ }
+ /* end-sanitize-r5900 */
- callback->printf_filtered(callback,"%s endian memory model\n",(BigEndianMem ? "Big" : "Little"));
+ /* start-sanitize-sky */
+#ifdef TARGET_SKY
+ if (rn >= NUM_R5900_REGS)
+ {
+ rn = rn - NUM_R5900_REGS;
+
+ if (rn < NUM_VU_REGS)
+ {
+ if (rn < NUM_VU_INTEGER_REGS)
+ return read_vu_int_reg (&(vu0_device.regs), rn, memory);
+ else if (rn >= FIRST_VEC_REG)
+ {
+ rn -= FIRST_VEC_REG;
+ return read_vu_vec_reg (&(vu0_device.regs), rn>>2, rn & 3,
+ memory);
+ }
+ else switch (rn - NUM_VU_INTEGER_REGS)
+ {
+ case 0:
+ return read_vu_special_reg(&vu0_device, VU_REG_CIA, memory);
+ case 1:
+ return read_vu_misc_reg (&(vu0_device.regs), VU_REG_MR,
+ memory);
+ case 2: /* VU0 has no P register */
+ *((int *) memory) = 0;
+ return 4;
+ case 3:
+ return read_vu_misc_reg (&(vu0_device.regs), VU_REG_MI,
+ memory);
+ case 4:
+ return read_vu_misc_reg (&(vu0_device.regs), VU_REG_MQ,
+ memory);
+ default:
+ return read_vu_acc_reg (&(vu0_device.regs),
+ rn - (NUM_VU_INTEGER_REGS + 5),
+ memory);
+ }
+ }
+
+ rn -= NUM_VU_REGS; /* VU1 registers are next */
+
+ if (rn < NUM_VU_REGS)
+ {
+ if (rn < NUM_VU_INTEGER_REGS)
+ return read_vu_int_reg (&(vu1_device.regs), rn, memory);
+ else if (rn >= FIRST_VEC_REG)
+ {
+ rn -= FIRST_VEC_REG;
+ return read_vu_vec_reg (&(vu1_device.regs),
+ rn >> 2, rn & 3, memory);
+ }
+ else switch (rn - NUM_VU_INTEGER_REGS)
+ {
+ case 0:
+ return read_vu_special_reg(&vu1_device, VU_REG_CIA, memory);
+ case 1:
+ return read_vu_misc_reg (&(vu1_device.regs),
+ VU_REG_MR, memory);
+ case 2:
+ return read_vu_misc_reg (&(vu1_device.regs),
+ VU_REG_MP, memory);
+ case 3:
+ return read_vu_misc_reg (&(vu1_device.regs),
+ VU_REG_MI, memory);
+ case 4:
+ return read_vu_misc_reg (&(vu1_device.regs),
+ VU_REG_MQ, memory);
+ default:
+ return read_vu_acc_reg (&(vu1_device.regs),
+ rn - (NUM_VU_INTEGER_REGS + 5),
+ memory);
+ }
+ }
+
+ rn -= NUM_VU_REGS; /* VIF0 registers are next */
+
+ if (rn < NUM_VIF_REGS)
+ {
+ if (rn < NUM_VIF_REGS-1)
+ return read_pke_reg (&pke0_device, rn, memory);
+ else
+ return read_pke_pc (&pke0_device, memory);
+ }
+
+ rn -= NUM_VIF_REGS; /* VIF1 registers are last */
+
+ if (rn < NUM_VIF_REGS)
+ {
+ if (rn < NUM_VIF_REGS-1)
+ return read_pke_reg (&pke1_device, rn, memory);
+ else
+ return read_pke_pc (&pke1_device, memory);
+ }
+
+ sim_io_eprintf( sd, "Invalid VU register (register fetch ignored)\n" );
+ }
+#endif
+ /* end-sanitize-sky */
- callback->printf_filtered(callback,"0x%08X bytes of memory at 0x%08X%08X\n",(unsigned int)membank_size,WORD64HI(membank_base),WORD64LO(membank_base));
+ /* Any floating point register */
+ if (rn >= FGRIDX && rn < FGRIDX + NR_FGR)
+ {
+ if (cpu->register_widths[rn] == 32)
+ {
+ *(unsigned32*)memory = H2T_4 (cpu->fgr[rn - FGRIDX]);
+ return 4;
+ }
+ else
+ {
+ *(unsigned64*)memory = H2T_8 (cpu->fgr[rn - FGRIDX]);
+ return 8;
+ }
+ }
-#if !defined(FASTSIM)
- if (instruction_fetch_overflow != 0)
- callback->printf_filtered(callback,"Instruction fetches = 0x%08X%08X\n",instruction_fetch_overflow,instruction_fetches);
+ if (cpu->register_widths[rn] == 32)
+ {
+ *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn]));
+ return 4;
+ }
else
- callback->printf_filtered(callback,"Instruction fetches = %d\n",instruction_fetches);
- callback->printf_filtered(callback,"Pipeline ticks = %d\n",pipeline_ticks);
- /* It would be a useful feature, if when performing multi-cycle
- simulations (rather than single-stepping) we keep the start and
- end times of the execution, so that we can give a performance
- figure for the simulator. */
-#endif /* !FASTSIM */
-
- /* print information pertaining to MIPS ISA and architecture being simulated */
- /* things that may be interesting */
- /* instructions executed - if available */
- /* cycles executed - if available */
- /* pipeline stalls - if available */
- /* virtual time taken */
- /* profiling size */
- /* profiling frequency */
- /* profile minpc */
- /* profile maxpc */
+ {
+ *(unsigned64*)memory = H2T_8 ((unsigned64)(cpu->registers[rn]));
+ return 8;
+ }
- return;
+ return 0;
}
-int
-sim_load (prog,from_tty)
- char *prog;
- int from_tty;
-{
- /* Return non-zero if the caller should handle the load. Zero if
- we have loaded the image. */
- return(-1);
-}
-void
-sim_create_inferior (start_address,argv,env)
- SIM_ADDR start_address;
+SIM_RC
+sim_create_inferior (sd, abfd, argv,env)
+ SIM_DESC sd;
+ struct _bfd *abfd;
char **argv;
char **env;
{
+
#ifdef DEBUG
- printf("DBG: sim_create_inferior entered: start_address = 0x%08X\n",start_address);
+ printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
+ pr_addr(PC));
#endif /* DEBUG */
- /* Prepare to execute the program to be simulated */
- /* argv and env are NULL terminated lists of pointers */
+ ColdReset(sd);
-#if 1
- PC = (uword64)start_address;
-#else
- /* TODO: Sort this properly. SIM_ADDR may already be a 64bit value: */
- PC = SIGNEXTEND(start_address,32);
-#endif
- /* NOTE: GDB normally sets the PC explicitly. However, this call is
- used by other clients of the simulator. */
+ if (abfd != NULL)
+ {
+ /* override PC value set by ColdReset () */
+ int cpu_nr;
+ for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
+ {
+ sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
+ CIA_SET (cpu, (unsigned64) bfd_get_start_address (abfd));
+ }
+ }
- if (argv || env) {
- callback->printf_filtered(callback,"sim_create_inferior() : passed arguments ignored\n");
-#if 1 /* def DEBUG */
+#if 0 /* def DEBUG */
+ if (argv || env)
{
- char **cptr;
- for (cptr = argv; (cptr && *cptr); cptr++)
- printf("DBG: arg \"%s\"\n",*cptr);
+ /* We should really place the argv slot values into the argument
+ registers, and onto the stack as required. However, this
+ assumes that we have a stack defined, which is not
+ necessarily true at the moment. */
+ char **cptr;
+ sim_io_printf(sd,"sim_create_inferior() : passed arguments ignored\n");
+ for (cptr = argv; (cptr && *cptr); cptr++)
+ printf("DBG: arg \"%s\"\n",*cptr);
}
#endif /* DEBUG */
- /* We should really place the argv slot values into the argument
- registers, and onto the stack as required. However, this
- assumes that we have a stack defined, which is not necessarily
- true at the moment. */
- }
-
- return;
-}
-
-void
-sim_kill ()
-{
-#if 1
- /* This routine should be for terminating any existing simulation
- thread. Since we are single-threaded only at the moment, this is
- not an issue. It should *NOT* be used to terminate the
- simulator. */
-#else /* do *NOT* call sim_close */
- sim_close(1); /* Do not hang on errors */
- /* This would also be the point where any memory mapped areas used
- by the simulator should be released. */
-#endif
- return;
-}
-int
-sim_get_quit_code ()
-{
- /* The standard MIPS PCS (Procedure Calling Standard) uses V0(r2) as
- the function return value. However, it may be more correct for
- this to return the argument to the exit() function (if
- called). */
- return(V0);
+ return SIM_RC_OK;
}
void
-sim_set_callbacks (p)
- host_callback *p;
-{
- callback = p;
- return;
-}
-
-typedef enum {e_terminate,e_help,e_setmemsize,e_reset} e_cmds;
-
-static struct t_sim_command {
- e_cmds id;
- const char *name;
- const char *help;
-} sim_commands[] = {
- {e_help, "help", ": Show MIPS simulator private commands"},
- {e_setmemsize,"set-memory-size","<n> : Specify amount of memory simulated"},
- {e_reset, "reset-system", ": Reset the simulated processor"},
- {e_terminate, NULL}
-};
-
-void
-sim_do_command (cmd)
+sim_do_command (sd,cmd)
+ SIM_DESC sd;
char *cmd;
{
- struct t_sim_command *cptr;
-
- if (callback == NULL) {
- fprintf(stderr,"Simulator not enabled: \"target sim\" should be used to activate\n");
- return;
- }
-
- if (!(cmd && *cmd != '\0'))
- cmd = "help";
-
- /* NOTE: Accessed from the GDB "sim" commmand: */
- for (cptr = sim_commands; cptr && cptr->name; cptr++)
- if (strncmp(cmd,cptr->name,strlen(cptr->name)) == 0) {
- cmd += strlen(cptr->name);
- switch (cptr->id) {
- case e_help: /* no arguments */
- { /* no arguments */
- struct t_sim_command *lptr;
- callback->printf_filtered(callback,"List of MIPS simulator commands:\n");
- for (lptr = sim_commands; lptr->name; lptr++)
- callback->printf_filtered(callback,"%s %s\n",lptr->name,lptr->help);
- }
- break;
-
- case e_setmemsize: /* memory size argument */
- {
- unsigned int newsize = (unsigned int)getnum(cmd);
- sim_size(newsize);
- }
- break;
-
- case e_reset: /* no arguments */
- ColdReset();
- /* NOTE: See the comments in sim_open() relating to device
- initialisation. */
- break;
-
- default:
- callback->printf_filtered(callback,"FATAL: Matched \"%s\", but failed to match command id %d.\n",cmd,cptr->id);
- break;
- }
- break;
- }
-
- if (!(cptr->name))
- callback->printf_filtered(callback,"Error: \"%s\" is not a valid MIPS simulator command.\n",cmd);
-
- return;
+ if (sim_args_command (sd, cmd) != SIM_RC_OK)
+ sim_io_printf (sd, "Error: \"%s\" is not a valid MIPS simulator command.\n",
+ cmd);
}
/*---------------------------------------------------------------------------*/
-/* NOTE: The following routines do not seem to be used by GDB at the
- moment. However, they may be useful to the standalone simulator
- world. */
-
-
-/* The profiling format is described in the "gmon_out.h" header file */
-void
-sim_set_profile (n)
- int n;
-{
-#if defined(PROFILE)
- profile_frequency = n;
- state |= simPROFILE;
-#endif /* PROFILE */
- return;
-}
-
-void
-sim_set_profile_size (n)
- int n;
-{
-#if defined(PROFILE)
- if (state & simPROFILE) {
- int bsize;
-
- /* Since we KNOW that the memory banks are a power-of-2 in size: */
- profile_nsamples = power2(n);
- profile_minpc = membank_base;
- profile_maxpc = (membank_base + membank_size);
-
- /* Just in-case we are sampling every address: NOTE: The shift
- right of 2 is because we only have word-aligned PC addresses. */
- if (profile_nsamples > (membank_size >> 2))
- profile_nsamples = (membank_size >> 2);
-
- /* Since we are dealing with power-of-2 values: */
- profile_shift = (((membank_size >> 2) / profile_nsamples) - 1);
-
- bsize = (profile_nsamples * sizeof(unsigned short));
- if (profile_hist == NULL)
- profile_hist = (unsigned short *)calloc(64,(bsize / 64));
- else
- profile_hist = (unsigned short *)realloc(profile_hist,bsize);
- if (profile_hist == NULL) {
- callback->printf_filtered(callback,"Failed to allocate VM for profiling buffer (0x%08X bytes)\n",bsize);
- state &= ~simPROFILE;
- }
- }
-#endif /* PROFILE */
-
- return;
-}
-
-void
-sim_size(newsize)
- unsigned int newsize;
-{
- char *new;
- /* Used by "run", and internally, to set the simulated memory size */
- newsize = power2(newsize);
- if (membank == NULL)
- new = (char *)calloc(64,(membank_size / 64));
- else
- new = (char *)realloc(membank,newsize);
- if (new == NULL) {
- if (membank == NULL)
- callback->printf_filtered(callback,"Not enough VM for simulation memory of 0x%08X bytes\n",membank_size);
- else
- callback->printf_filtered(callback,"Failed to resize memory (still 0x%08X bytes)\n",membank_size);
- } else {
- membank_size = (unsigned)newsize;
- membank = new;
- callback->printf_filtered(callback,"Memory size now 0x%08X bytes\n",membank_size);
-#if defined(PROFILE)
- /* Ensure that we sample across the new memory range */
- sim_set_profile_size(profile_nsamples);
-#endif /* PROFILE */
- }
-
- return;
-}
+/*-- Private simulator support interface ------------------------------------*/
+/*---------------------------------------------------------------------------*/
-int
-sim_trace()
+/* Read a null terminated string from memory, return in a buffer */
+static char *
+fetch_str (sd, addr)
+ SIM_DESC sd;
+ address_word addr;
{
- /* This routine is called by the "run" program, when detailed
- execution information is required. Rather than executing a single
- instruction, and looping around externally... we just start
- simulating, returning TRUE when the simulator stops (for whatever
- reason). */
-
-#if defined(TRACE)
- /* Ensure tracing is enabled, if available */
- if (tracefh != NULL)
- state |= simTRACE;
-#endif /* TRACE */
-
- state &= ~(simSTOP | simSTEP); /* execute until event */
- state |= (simHALTEX | simHALTIN); /* treat interrupt event as exception */
- /* Start executing instructions from the current state (set
- explicitly by register updates, or by sim_create_inferior): */
- simulate();
-
- return(1);
+ char *buf;
+ int nr = 0;
+ char null;
+ while (sim_read (sd, addr + nr, &null, 1) == 1 && null != 0)
+ nr++;
+ buf = NZALLOC (char, nr + 1);
+ sim_read (sd, addr, buf, nr);
+ return buf;
}
-/*---------------------------------------------------------------------------*/
-/*-- Private simulator support interface ------------------------------------*/
-/*---------------------------------------------------------------------------*/
-
/* Simple monitor interface (currently setup for the IDT and PMON monitors) */
static void
-sim_monitor(reason)
- unsigned int reason;
+sim_monitor (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ unsigned int reason)
{
+#ifdef DEBUG
+ printf("DBG: sim_monitor: entered (reason = %d)\n",reason);
+#endif /* DEBUG */
+
/* The IDT monitor actually allows two instructions per vector
slot. However, the simulator currently causes a trap on each
individual instruction. We cheat, and lose the bottom bit. */
/* The following callback functions are available, however the
monitor we are simulating does not make use of them: get_errno,
isatty, lseek, rename, system, time and unlink */
- switch (reason) {
+ switch (reason)
+ {
+
case 6: /* int open(char *path,int flags) */
{
- const char *ptr;
- uword64 paddr;
- int cca;
- if (AddressTranslation(A0,isDATA,isLOAD,&paddr,&cca,isHOST,isREAL))
- V0 = callback->open(callback,(char *)((int)paddr),(int)A1);
- else
- callback->printf_filtered(callback,"WARNING: Attempt to pass pointer that does not reference simulated memory\n");
+ char *path = fetch_str (sd, A0);
+ V0 = sim_io_open (sd, path, (int)A1);
+ zfree (path);
+ break;
}
- break;
case 7: /* int read(int file,char *ptr,int len) */
{
- const char *ptr;
- uword64 paddr;
- int cca;
- if (AddressTranslation(A1,isDATA,isLOAD,&paddr,&cca,isHOST,isREAL))
- V0 = callback->read(callback,(int)A0,(char *)((int)paddr),(int)A2);
- else
- callback->printf_filtered(callback,"WARNING: Attempt to pass pointer that does not reference simulated memory\n");
+ int fd = A0;
+ int nr = A2;
+ char *buf = zalloc (nr);
+ V0 = sim_io_read (sd, fd, buf, nr);
+ sim_write (sd, A1, buf, nr);
+ zfree (buf);
}
break;
case 8: /* int write(int file,char *ptr,int len) */
{
- const char *ptr;
- uword64 paddr;
- int cca;
- if (AddressTranslation(A1,isDATA,isLOAD,&paddr,&cca,isHOST,isREAL))
- V0 = callback->write(callback,(int)A0,(const char *)((int)paddr),(int)A2);
- else
- callback->printf_filtered(callback,"WARNING: Attempt to pass pointer that does not reference simulated memory\n");
+ int fd = A0;
+ int nr = A2;
+ char *buf = zalloc (nr);
+ sim_read (sd, A1, buf, nr);
+ V0 = sim_io_write (sd, fd, buf, nr);
+ zfree (buf);
+ break;
}
- break;
case 10: /* int close(int file) */
- V0 = callback->close(callback,(int)A0);
- break;
+ {
+ V0 = sim_io_close (sd, (int)A0);
+ break;
+ }
+
+ case 2: /* Densan monitor: char inbyte(int waitflag) */
+ {
+ if (A0 == 0) /* waitflag == NOWAIT */
+ V0 = (unsigned_word)-1;
+ }
+ /* Drop through to case 11 */
case 11: /* char inbyte(void) */
{
char tmp;
- if (callback->read_stdin(callback,&tmp,sizeof(char)) != sizeof(char)) {
- callback->printf_filtered(callback,"WARNING: Invalid return from character read\n");
- V0 = -1;
- }
+ if (sim_io_read_stdin (sd, &tmp, sizeof(char)) != sizeof(char))
+ {
+ sim_io_error(sd,"Invalid return from character read");
+ V0 = (unsigned_word)-1;
+ }
else
- V0 = tmp;
+ V0 = (unsigned_word)tmp;
+ break;
}
- break;
+ case 3: /* Densan monitor: void co(char chr) */
case 12: /* void outbyte(char chr) : write a byte to "stdout" */
{
char tmp = (char)(A0 & 0xFF);
- callback->write_stdout(callback,&tmp,sizeof(char));
+ sim_io_write_stdout (sd, &tmp, sizeof(char));
+ break;
}
- break;
case 17: /* void _exit() */
- callback->printf_filtered(callback,"sim_monitor(17): _exit(int reason) to be coded\n");
- state |= (simSTOP | simEXIT); /* stop executing code */
- rcexit = (unsigned int)(A0 & 0xFFFFFFFF);
+ {
+ sim_io_eprintf (sd, "sim_monitor(17): _exit(int reason) to be coded\n");
+ sim_engine_halt (SD, CPU, NULL, NULL_CIA, sim_exited,
+ (unsigned int)(A0 & 0xFFFFFFFF));
+ break;
+ }
+
+ case 28 : /* PMON flush_cache */
break;
case 55: /* void get_mem_info(unsigned int *ptr) */
/* [A0 + 4] = instruction cache size */
/* [A0 + 8] = data cache size */
{
- uword64 vaddr = A0;
- uword64 paddr, value;
- int cca;
- int failed = 0;
-
- /* NOTE: We use RAW memory writes here, but since we are not
- gathering statistics for the monitor calls we are simulating,
- it is not an issue. */
-
- /* Memory size */
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isREAL)) {
- value = (uword64)membank_size;
- StoreMemory(cca,AccessLength_WORD,value,paddr,vaddr,isRAW);
- /* We re-do the address translations, in-case the block
- overlaps a memory boundary: */
- value = 0;
- vaddr += (AccessLength_WORD + 1);
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isREAL)) {
- StoreMemory(cca,AccessLength_WORD,value,paddr,vaddr,isRAW);
- vaddr += (AccessLength_WORD + 1);
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&cca,isTARGET,isREAL))
- StoreMemory(cca,AccessLength_WORD,value,paddr,vaddr,isRAW);
- else
- failed = -1;
- } else
- failed = -1;
- } else
- failed = -1;
-
- if (failed)
- callback->printf_filtered(callback,"WARNING: Invalid pointer passed into monitor call\n");
+ unsigned_4 value = MEM_SIZE /* FIXME STATE_MEM_SIZE (sd) */;
+ unsigned_4 zero = 0;
+ H2T (value);
+ sim_write (sd, A0 + 0, (char *)&value, 4);
+ sim_write (sd, A0 + 4, (char *)&zero, 4);
+ sim_write (sd, A0 + 8, (char *)&zero, 4);
+ /* sim_io_eprintf (sd, "sim: get_mem_info() depreciated\n"); */
+ break;
}
- break;
-
+
case 158 : /* PMON printf */
/* in: A0 = pointer to format string */
/* A1 = optional argument 1 */
/* A2 = optional argument 2 */
/* A3 = optional argument 3 */
/* out: void */
+ /* The following is based on the PMON printf source */
{
- uword64 paddr;
- int cca;
- if (AddressTranslation(A0,isDATA,isLOAD,&paddr,&cca,isHOST,isREAL))
- callback->printf_filtered(callback,(char *)((int)paddr),(int)A1,(int)A2,(int)A2);
- else
- callback->printf_filtered(callback,"WARNING: Attempt to pass pointer that does not reference simulated memory\n");
+ address_word s = A0;
+ char c;
+ signed_word *ap = &A1; /* 1st argument */
+ /* This isn't the quickest way, since we call the host print
+ routine for every character almost. But it does avoid
+ having to allocate and manage a temporary string buffer. */
+ /* TODO: Include check that we only use three arguments (A1,
+ A2 and A3) */
+ while (sim_read (sd, s++, &c, 1) && c != '\0')
+ {
+ if (c == '%')
+ {
+ char tmp[40];
+ enum {FMT_RJUST, FMT_LJUST, FMT_RJUST0, FMT_CENTER} fmt = FMT_RJUST;
+ int width = 0, trunc = 0, haddot = 0, longlong = 0;
+ while (sim_read (sd, s++, &c, 1) && c != '\0')
+ {
+ if (strchr ("dobxXulscefg%", s))
+ break;
+ else if (c == '-')
+ fmt = FMT_LJUST;
+ else if (c == '0')
+ fmt = FMT_RJUST0;
+ else if (c == '~')
+ fmt = FMT_CENTER;
+ else if (c == '*')
+ {
+ if (haddot)
+ trunc = (int)*ap++;
+ else
+ width = (int)*ap++;
+ }
+ else if (c >= '1' && c <= '9')
+ {
+ address_word t = s;
+ unsigned int n;
+ while (sim_read (sd, s++, &c, 1) == 1 && isdigit (c))
+ tmp[s - t] = c;
+ tmp[s - t] = '\0';
+ n = (unsigned int)strtol(tmp,NULL,10);
+ if (haddot)
+ trunc = n;
+ else
+ width = n;
+ s--;
+ }
+ else if (c == '.')
+ haddot = 1;
+ }
+ switch (c)
+ {
+ case '%':
+ sim_io_printf (sd, "%%");
+ break;
+ case 's':
+ if ((int)*ap != 0)
+ {
+ address_word p = *ap++;
+ char ch;
+ while (sim_read (sd, p++, &ch, 1) == 1 && ch != '\0')
+ sim_io_printf(sd, "%c", ch);
+ }
+ else
+ sim_io_printf(sd,"(null)");
+ break;
+ case 'c':
+ sim_io_printf (sd, "%c", (int)*ap++);
+ break;
+ default:
+ if (c == 'l')
+ {
+ sim_read (sd, s++, &c, 1);
+ if (c == 'l')
+ {
+ longlong = 1;
+ sim_read (sd, s++, &c, 1);
+ }
+ }
+ if (strchr ("dobxXu", c))
+ {
+ word64 lv = (word64) *ap++;
+ if (c == 'b')
+ sim_io_printf(sd,"<binary not supported>");
+ else
+ {
+ sprintf (tmp, "%%%s%c", longlong ? "ll" : "", c);
+ if (longlong)
+ sim_io_printf(sd, tmp, lv);
+ else
+ sim_io_printf(sd, tmp, (int)lv);
+ }
+ }
+ else if (strchr ("eEfgG", c))
+ {
+ double dbl = *(double*)(ap++);
+ sprintf (tmp, "%%%d.%d%c", width, trunc, c);
+ sim_io_printf (sd, tmp, dbl);
+ trunc = 0;
+ }
+ }
+ }
+ else
+ sim_io_printf(sd, "%c", c);
+ }
+ break;
}
- break;
default:
- callback->printf_filtered(callback,"TODO: sim_monitor(%d) : PC = 0x%08X%08X\n",reason,WORD64HI(IPC),WORD64LO(IPC));
- callback->printf_filtered(callback,"(Arguments : A0 = 0x%08X%08X : A1 = 0x%08X%08X : A2 = 0x%08X%08X : A3 = 0x%08X%08X)\n",WORD64HI(A0),WORD64LO(A0),WORD64HI(A1),WORD64LO(A1),WORD64HI(A2),WORD64LO(A2),WORD64HI(A3),WORD64LO(A3));
+ sim_io_error (sd, "TODO: sim_monitor(%d) : PC = 0x%s\n",
+ reason, pr_addr(cia));
break;
}
return;
}
-void
-sim_error(fmt)
- char *fmt;
+/* Store a word into memory. */
+
+static void
+store_word (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ uword64 vaddr,
+ signed_word val)
{
- va_list ap;
- va_start(ap,fmt);
- callback->printf_filtered(callback,"SIM Error: ");
- callback->printf_filtered(callback,fmt,ap);
- va_end(ap);
- SignalException(SimulatorFault,"");
- return;
+ address_word paddr;
+ int uncached;
+
+ if ((vaddr & 3) != 0)
+ SignalExceptionAddressStore ();
+ else
+ {
+ if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached,
+ isTARGET, isREAL))
+ {
+ const uword64 mask = 7;
+ uword64 memval;
+ unsigned int byte;
+
+ paddr = (paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2));
+ byte = (vaddr & mask) ^ (BigEndianCPU << 2);
+ memval = ((uword64) val) << (8 * byte);
+ StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
+ isREAL);
+ }
+ }
}
-static unsigned int
-power2(value)
- unsigned int value;
-{
- int loop,tmp;
+/* Load a word from memory. */
- /* Round *UP* to the nearest power-of-2 if not already one */
- if (value != (value & ~(value - 1))) {
- for (tmp = value, loop = 0; (tmp != 0); loop++)
- tmp >>= 1;
- value = (1 << loop);
- }
+static signed_word
+load_word (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ uword64 vaddr)
+{
+ if ((vaddr & 3) != 0)
+ SignalExceptionAddressLoad ();
+ else
+ {
+ address_word paddr;
+ int uncached;
+
+ if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached,
+ isTARGET, isREAL))
+ {
+ const uword64 mask = 0x7;
+ const unsigned int reverse = ReverseEndian ? 1 : 0;
+ const unsigned int bigend = BigEndianCPU ? 1 : 0;
+ uword64 memval;
+ unsigned int byte;
+
+ paddr = (paddr & ~mask) | ((paddr & mask) ^ (reverse << 2));
+ LoadMemory (&memval,NULL,uncached, AccessLength_WORD, paddr, vaddr,
+ isDATA, isREAL);
+ byte = (vaddr & mask) ^ (bigend << 2);
+ return SIGNEXTEND (((memval >> (8 * byte)) & 0xffffffff), 32);
+ }
+ }
- return(value);
+ return 0;
}
-static long
-getnum(value)
- char *value;
+/* Simulate the mips16 entry and exit pseudo-instructions. These
+ would normally be handled by the reserved instruction exception
+ code, but for ease of simulation we just handle them directly. */
+
+static void
+mips16_entry (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ unsigned int insn)
{
- long num;
- char *end;
-
- num = strtol(value,&end,10);
- if (end == value)
- callback->printf_filtered(callback,"Warning: Invalid number \"%s\" ignored, using zero\n",value);
- else {
- if (*end && ((tolower(*end) == 'k') || (tolower(*end) == 'm'))) {
- if (tolower(*end) == 'k')
- num *= (1 << 10);
- else
- num *= (1 << 20);
- end++;
- }
- if (*end)
- callback->printf_filtered(callback,"Warning: Spurious characters \"%s\" at end of number ignored\n",end);
- }
+ int aregs, sregs, rreg;
+
+#ifdef DEBUG
+ printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn);
+#endif /* DEBUG */
+
+ aregs = (insn & 0x700) >> 8;
+ sregs = (insn & 0x0c0) >> 6;
+ rreg = (insn & 0x020) >> 5;
+
+ /* This should be checked by the caller. */
+ if (sregs == 3)
+ abort ();
+
+ if (aregs < 5)
+ {
+ int i;
+ signed_word tsp;
+
+ /* This is the entry pseudo-instruction. */
+
+ for (i = 0; i < aregs; i++)
+ store_word (SD, CPU, cia, (uword64) (SP + 4 * i), GPR[i + 4]);
- return(num);
+ tsp = SP;
+ SP -= 32;
+
+ if (rreg)
+ {
+ tsp -= 4;
+ store_word (SD, CPU, cia, (uword64) tsp, RA);
+ }
+
+ for (i = 0; i < sregs; i++)
+ {
+ tsp -= 4;
+ store_word (SD, CPU, cia, (uword64) tsp, GPR[16 + i]);
+ }
+ }
+ else
+ {
+ int i;
+ signed_word tsp;
+
+ /* This is the exit pseudo-instruction. */
+
+ tsp = SP + 32;
+
+ if (rreg)
+ {
+ tsp -= 4;
+ RA = load_word (SD, CPU, cia, (uword64) tsp);
+ }
+
+ for (i = 0; i < sregs; i++)
+ {
+ tsp -= 4;
+ GPR[i + 16] = load_word (SD, CPU, cia, (uword64) tsp);
+ }
+
+ SP += 32;
+
+ if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
+ {
+ if (aregs == 5)
+ {
+ FGR[0] = WORD64LO (GPR[4]);
+ FPR_STATE[0] = fmt_uninterpreted;
+ }
+ else if (aregs == 6)
+ {
+ FGR[0] = WORD64LO (GPR[5]);
+ FGR[1] = WORD64LO (GPR[4]);
+ FPR_STATE[0] = fmt_uninterpreted;
+ FPR_STATE[1] = fmt_uninterpreted;
+ }
+ }
+
+ PC = RA;
+ }
+
}
/*-- trace support ----------------------------------------------------------*/
1 write data
2 instruction fetch
3 escape record (treated as unknown access type)
- 4 escape record (causes cache flush)
-
- The address field is a 32bit (lower-case) hexadecimal address
- value. The address should *NOT* be preceded by "0x".
-
- The size of the memory transfer is not important when dealing with
- cache lines (as long as no more than a cache line can be
- transferred in a single operation :-), however more information
- could be given following the dineroIII requirement to allow more
- complete memory and cache simulators to provide better
- results. i.e. the University of Pisa has a cache simulator that can
- also take bus size and speed as (variable) inputs to calculate
- complete system performance (a much more useful ability when trying
- to construct an end product, rather than a processor). They
- currently have an ARM version of their tool called ChARM. */
-
-static
-void dotrace(tracefh,type,address,width,comment)
- FILE *tracefh;
- int type;
- unsigned int address;
- int width;
- char *comment;
-{
- if (state & simTRACE) {
- va_list ap;
- fprintf(tracefh,"%d %08x ; width %d ; ",type,address,width);
- va_start(ap,comment);
- fprintf(tracefh,comment,ap);
- va_end(ap);
- fprintf(tracefh,"\n");
- }
- /* NOTE: Since the "din" format will only accept 32bit addresses, and
- we may be generating 64bit ones, we should put the hi-32bits of the
- address into the comment field. */
-
- /* TODO: Provide a buffer for the trace lines. We can then avoid
- performing writes until the buffer is filled, or the file is
- being closed. */
-
- /* NOTE: We could consider adding a comment field to the "din" file
- produced using type 3 markers (unknown access). This would then
- allow information about the program that the "din" is for, and
- the MIPs world that was being simulated, to be placed into the
- trace file. */
-
- return;
-}
-#endif /* TRACE */
-
-/*---------------------------------------------------------------------------*/
-/*-- simulator engine -------------------------------------------------------*/
-/*---------------------------------------------------------------------------*/
-
-static void
-ColdReset()
-{
- /* RESET: Fixed PC address: */
- PC = (((uword64)0xFFFFFFFF<<32) | 0xBFC00000);
- /* The reset vector address is in the unmapped, uncached memory space. */
-
- SR &= ~(status_SR | status_TS | status_RP);
- SR |= (status_ERL | status_BEV);
- /* VR4300 starts in Big-Endian mode */
- CONFIG &= ~(config_EP_mask << config_EP_shift);
- CONFIG |= ((config_EP_D << config_EP_shift) | config_BE);
- /* TODO: The VR4300 CONFIG register is not modelled fully at the moment */
-
-#if defined(HASFPU) && (GPRLEN == (64))
- /* Cheat and allow access to the complete register set immediately: */
- SR |= status_FR; /* 64bit registers */
-#endif /* HASFPU and 64bit FP registers */
-
- /* Ensure that any instructions with pending register updates are
- cleared: */
- {
- int loop;
- for (loop = 0; (loop < PSLOTS); loop++)
- pending_slot_reg[loop] = (LAST_EMBED_REGNUM + 1);
- pending_in = pending_out = pending_total = 0;
- }
-
-#if defined(HASFPU)
- /* Initialise the FPU registers to the unknown state */
- {
- int rn;
- for (rn = 0; (rn < 32); rn++)
- fpr_state[rn] = fmt_uninterpreted;
- }
-#endif /* HASFPU */
-
- return;
-}
-
-/* Description from page A-22 of the "MIPS IV Instruction Set" manual (revision 3.1) */
-/* Translate a virtual address to a physical address and cache
- coherence algorithm describing the mechanism used to resolve the
- memory reference. Given the virtual address vAddr, and whether the
- reference is to Instructions ot Data (IorD), find the corresponding
- physical address (pAddr) and the cache coherence algorithm (CCA)
- used to resolve the reference. If the virtual address is in one of
- the unmapped address spaces the physical address and the CCA are
- determined directly by the virtual address. If the virtual address
- is in one of the mapped address spaces then the TLB is used to
- determine the physical address and access type; if the required
- translation is not present in the TLB or the desired access is not
- permitted the function fails and an exception is taken.
-
- NOTE: This function is extended to return an exception state. This,
- along with the exception generation is used to notify whether a
- valid address translation occured */
-
-static int
-AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw)
- uword64 vAddr;
- int IorD;
- int LorS;
- uword64 *pAddr;
- int *CCA;
- int host;
- int raw;
-{
- int res = -1; /* TRUE : Assume good return */
-
-#ifdef DEBUG
- callback->printf_filtered(callback,"AddressTranslation(0x%08X%08X,%s,%s,...);\n",WORD64HI(vAddr),WORD64LO(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"),(LorS ? "iSTORE" : "isLOAD"));
-#endif
-
- /* Check that the address is valid for this memory model */
-
- /* For a simple (flat) memory model, we simply pass virtual
- addressess through (mostly) unchanged. */
- vAddr &= 0xFFFFFFFF;
-
- /* Treat the kernel memory spaces identically for the moment: */
- if ((membank_base == K1BASE) && (vAddr >= K0BASE) && (vAddr < (K0BASE + K0SIZE)))
- vAddr += (K1BASE - K0BASE);
-
- /* Also assume that the K1BASE memory wraps. This is required to
- allow the PMON run-time __sizemem() routine to function (without
- having to provide exception simulation). NOTE: A kludge to work
- around the fact that the monitor memory is currently held in the
- K1BASE space. */
- if (((vAddr < monitor_base) || (vAddr >= (monitor_base + monitor_size))) && (vAddr >= K1BASE && vAddr < (K1BASE + K1SIZE)))
- vAddr = (K1BASE | (vAddr & (membank_size - 1)));
-
- *pAddr = vAddr; /* default for isTARGET */
- *CCA = Uncached; /* not used for isHOST */
-
- /* NOTE: This is a duplicate of the code that appears in the
- LoadMemory and StoreMemory functions. They should be merged into
- a single function (that can be in-lined if required). */
- if ((vAddr >= membank_base) && (vAddr < (membank_base + membank_size))) {
- if (host)
- *pAddr = (int)&membank[((unsigned int)(vAddr - membank_base) & (membank_size - 1))];
- } else if ((vAddr >= monitor_base) && (vAddr < (monitor_base + monitor_size))) {
- if (host)
- *pAddr = (int)&monitor[((unsigned int)(vAddr - monitor_base) & (monitor_size - 1))];
- } else {
-#if 1 /* def DEBUG */
- callback->printf_filtered(callback,"Failed: AddressTranslation(0x%08X%08X,%s,%s,...) IPC = 0x%08X%08X\n",WORD64HI(vAddr),WORD64LO(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"),(LorS ? "isSTORE" : "isLOAD"),WORD64HI(IPC),WORD64LO(IPC));
-#endif /* DEBUG */
- res = 0; /* AddressTranslation has failed */
- *pAddr = -1;
- if (!raw) /* only generate exceptions on real memory transfers */
- SignalException((LorS == isSTORE) ? AddressStore : AddressLoad);
- else
- callback->printf_filtered(callback,"AddressTranslation for %s %s from 0x%08X%08X failed\n",(IorD ? "data" : "instruction"),(LorS ? "store" : "load"),WORD64HI(vAddr),WORD64LO(vAddr));
- }
-
- return(res);
-}
-
-/* Description from page A-23 of the "MIPS IV Instruction Set" manual (revision 3.1) */
-/* Prefetch data from memory. Prefetch is an advisory instruction for
- which an implementation specific action is taken. The action taken
- may increase performance, but must not change the meaning of the
- program, or alter architecturally-visible state. */
-static void
-Prefetch(CCA,pAddr,vAddr,DATA,hint)
- int CCA;
- uword64 pAddr;
- uword64 vAddr;
- int DATA;
- int hint;
-{
-#ifdef DEBUG
- callback->printf_filtered(callback,"Prefetch(%d,0x%08X%08X,0x%08X%08X,%d,%d);\n",CCA,WORD64HI(pAddr),WORD64LO(pAddr),WORD64HI(vAddr),WORD64LO(vAddr),DATA,hint);
-#endif /* DEBUG */
-
- /* For our simple memory model we do nothing */
- return;
-}
-
-/* Description from page A-22 of the "MIPS IV Instruction Set" manual (revision 3.1) */
-/* Load a value from memory. Use the cache and main memory as
- specified in the Cache Coherence Algorithm (CCA) and the sort of
- access (IorD) to find the contents of AccessLength memory bytes
- starting at physical location pAddr. The data is returned in the
- fixed width naturally-aligned memory element (MemElem). The
- low-order two (or three) bits of the address and the AccessLength
- indicate which of the bytes within MemElem needs to be given to the
- processor. If the memory access type of the reference is uncached
- then only the referenced bytes are read from memory and valid
- within the memory element. If the access type is cached, and the
- data is not present in cache, an implementation specific size and
- alignment block of memory is read and loaded into the cache to
- satisfy a load reference. At a minimum, the block is the entire
- memory element. */
-static uword64
-LoadMemory(CCA,AccessLength,pAddr,vAddr,IorD,raw)
- int CCA;
- int AccessLength;
- uword64 pAddr;
- uword64 vAddr;
- int IorD;
- int raw;
-{
- uword64 value;
-
-#ifdef DEBUG
- if (membank == NULL)
- callback->printf_filtered(callback,"DBG: LoadMemory(%d,%d,0x%08X%08X,0x%08X%08X,%s,%s)\n",CCA,AccessLength,WORD64HI(pAddr),WORD64LO(pAddr),WORD64HI(vAddr),WORD64LO(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"),(raw ? "isRAW" : "isREAL"));
-#endif /* DEBUG */
-
-#if defined(WARN_MEM)
- if (CCA != uncached)
- callback->printf_filtered(callback,"SIM Warning: LoadMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA);
-
- if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK) {
- /* In reality this should be a Bus Error */
- sim_error("AccessLength of %d would extend over 64bit aligned boundary for physical address 0x%08X%08X\n",AccessLength,WORD64HI(pAddr),WORD64LO(pAddr));
- }
-#endif /* WARN_MEM */
-
- /* Decide which physical memory locations are being dealt with. At
- this point we should be able to split the pAddr bits into the
- relevant address map being simulated. If the "raw" variable is
- set, the memory read being performed should *NOT* update any I/O
- state or affect the CPU state. This also includes avoiding
- affecting statistics gathering. */
-
- /* If instruction fetch then we need to check that the two lo-order
- bits are zero, otherwise raise a InstructionFetch exception: */
- if ((IorD == isINSTRUCTION) && ((pAddr & 0x3) != 0))
- SignalException(InstructionFetch);
- else {
- unsigned int index;
- unsigned char *mem = NULL;
-
-#if defined(TRACE)
- if (!raw)
- dotrace(tracefh,((IorD == isDATA) ? 0 : 2),(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"load%s",((IorD == isDATA) ? "" : " instruction"));
-#endif /* TRACE */
-
- /* NOTE: Quicker methods of decoding the address space can be used
- when a real memory map is being simulated (i.e. using hi-order
- address bits to select device). */
- if ((pAddr >= membank_base) && (pAddr < (membank_base + membank_size))) {
- index = ((unsigned int)(pAddr - membank_base) & (membank_size - 1));
- mem = membank;
- } else if ((pAddr >= monitor_base) && (pAddr < (monitor_base + monitor_size))) {
- index = ((unsigned int)(pAddr - monitor_base) & (monitor_size - 1));
- mem = monitor;
- }
- if (mem == NULL)
- sim_error("Simulator memory not found for physical address 0x%08X%08X\n",WORD64HI(pAddr),WORD64LO(pAddr));
- else {
- /* If we obtained the endianness of the host, and it is the same
- as the target memory system we can optimise the memory
- accesses. However, without that information we must perform
- slow transfer, and hope that the compiler optimisation will
- merge successive loads. */
- value = 0; /* no data loaded yet */
-
- /* In reality we should always be loading a doubleword value (or
- word value in 32bit memory worlds). The external code then
- extracts the required bytes. However, to keep performance
- high we only load the required bytes into the relevant
- slots. */
- if (BigEndianMem)
- switch (AccessLength) { /* big-endian memory */
- case AccessLength_DOUBLEWORD :
- value |= ((uword64)mem[index++] << 56);
- case AccessLength_SEPTIBYTE :
- value |= ((uword64)mem[index++] << 48);
- case AccessLength_SEXTIBYTE :
- value |= ((uword64)mem[index++] << 40);
- case AccessLength_QUINTIBYTE :
- value |= ((uword64)mem[index++] << 32);
- case AccessLength_WORD :
- value |= ((unsigned int)mem[index++] << 24);
- case AccessLength_TRIPLEBYTE :
- value |= ((unsigned int)mem[index++] << 16);
- case AccessLength_HALFWORD :
- value |= ((unsigned int)mem[index++] << 8);
- case AccessLength_BYTE :
- value |= mem[index];
- break;
- }
- else {
- index += (AccessLength + 1);
- switch (AccessLength) { /* little-endian memory */
- case AccessLength_DOUBLEWORD :
- value |= ((uword64)mem[--index] << 56);
- case AccessLength_SEPTIBYTE :
- value |= ((uword64)mem[--index] << 48);
- case AccessLength_SEXTIBYTE :
- value |= ((uword64)mem[--index] << 40);
- case AccessLength_QUINTIBYTE :
- value |= ((uword64)mem[--index] << 32);
- case AccessLength_WORD :
- value |= ((uword64)mem[--index] << 24);
- case AccessLength_TRIPLEBYTE :
- value |= ((uword64)mem[--index] << 16);
- case AccessLength_HALFWORD :
- value |= ((uword64)mem[--index] << 8);
- case AccessLength_BYTE :
- value |= ((uword64)mem[--index] << 0);
- break;
- }
- }
-
-#ifdef DEBUG
- printf("DBG: LoadMemory() : (offset %d) : value = 0x%08X%08X\n",(int)(pAddr & LOADDRMASK),WORD64HI(value),WORD64LO(value));
-#endif /* DEBUG */
-
- /* TODO: We could try and avoid the shifts when dealing with raw
- memory accesses. This would mean updating the LoadMemory and
- StoreMemory routines to avoid shifting the data before
- returning or using it. */
- if (!raw) { /* do nothing for raw accessess */
- if (BigEndianMem)
- value <<= (((7 - (pAddr & LOADDRMASK)) - AccessLength) * 8);
- else /* little-endian only needs to be shifted up to the correct byte offset */
- value <<= ((pAddr & LOADDRMASK) * 8);
- }
-
-#ifdef DEBUG
- printf("DBG: LoadMemory() : shifted value = 0x%08X%08X\n",WORD64HI(value),WORD64LO(value));
-#endif /* DEBUG */
- }
- }
-
- return(value);
-}
-
-/* Description from page A-23 of the "MIPS IV Instruction Set" manual (revision 3.1) */
-/* Store a value to memory. The specified data is stored into the
- physical location pAddr using the memory hierarchy (data caches and
- main memory) as specified by the Cache Coherence Algorithm
- (CCA). The MemElem contains the data for an aligned, fixed-width
- memory element (word for 32-bit processors, doubleword for 64-bit
- processors), though only the bytes that will actually be stored to
- memory need to be valid. The low-order two (or three) bits of pAddr
- and the AccessLength field indicates which of the bytes within the
- MemElem data should actually be stored; only these bytes in memory
- will be changed. */
-static void
-StoreMemory(CCA,AccessLength,MemElem,pAddr,vAddr,raw)
- int CCA;
- int AccessLength;
- uword64 MemElem;
- uword64 pAddr;
- uword64 vAddr;
- int raw;
-{
-#ifdef DEBUG
- callback->printf_filtered(callback,"DBG: StoreMemory(%d,%d,0x%08X%08X,0x%08X%08X,0x%08X%08X,%s)\n",CCA,AccessLength,WORD64HI(MemElem),WORD64LO(MemElem),WORD64HI(pAddr),WORD64LO(pAddr),WORD64HI(vAddr),WORD64LO(vAddr),(raw ? "isRAW" : "isREAL"));
-#endif /* DEBUG */
-
-#if defined(WARN_MEM)
- if (CCA != uncached)
- callback->printf_filtered(callback,"SIM Warning: StoreMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA);
-
- if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK)
- sim_error("AccessLength of %d would extend over 64bit aligned boundary for physical address 0x%08X%08X\n",AccessLength,WORD64HI(pAddr),WORD64LO(pAddr));
-#endif /* WARN_MEM */
-
-#if defined(TRACE)
- if (!raw)
- dotrace(tracefh,1,(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"store");
-#endif /* TRACE */
-
- /* See the comments in the LoadMemory routine about optimising
- memory accesses. Also if we wanted to make the simulator smaller,
- we could merge a lot of this code with the LoadMemory
- routine. However, this would slow the simulator down with
- run-time conditionals. */
- {
- unsigned int index;
- unsigned char *mem = NULL;
+ 4 escape record (causes cache flush)
- if ((pAddr >= membank_base) && (pAddr < (membank_base + membank_size))) {
- index = ((unsigned int)(pAddr - membank_base) & (membank_size - 1));
- mem = membank;
- } else if ((pAddr >= monitor_base) && (pAddr < (monitor_base + monitor_size))) {
- index = ((unsigned int)(pAddr - monitor_base) & (monitor_size - 1));
- mem = monitor;
- }
+ The address field is a 32bit (lower-case) hexadecimal address
+ value. The address should *NOT* be preceded by "0x".
- if (mem == NULL)
- sim_error("Simulator memory not found for physical address 0x%08X%08X\n",WORD64HI(pAddr),WORD64LO(pAddr));
- else {
- int shift = 0;
+ The size of the memory transfer is not important when dealing with
+ cache lines (as long as no more than a cache line can be
+ transferred in a single operation :-), however more information
+ could be given following the dineroIII requirement to allow more
+ complete memory and cache simulators to provide better
+ results. i.e. the University of Pisa has a cache simulator that can
+ also take bus size and speed as (variable) inputs to calculate
+ complete system performance (a much more useful ability when trying
+ to construct an end product, rather than a processor). They
+ currently have an ARM version of their tool called ChARM. */
-#ifdef DEBUG
- printf("DBG: StoreMemory: offset = %d MemElem = 0x%08X%08X\n",(unsigned int)(pAddr & LOADDRMASK),WORD64HI(MemElem),WORD64LO(MemElem));
-#endif /* DEBUG */
- if (BigEndianMem) {
- if (raw)
- shift = ((7 - AccessLength) * 8);
- else /* real memory access */
- shift = ((pAddr & LOADDRMASK) * 8);
- MemElem <<= shift;
- } else {
- /* no need to shift raw little-endian data */
- if (!raw)
- MemElem >>= ((pAddr & LOADDRMASK) * 8);
- }
+void
+dotrace (SIM_DESC sd,
+ sim_cpu *cpu,
+ FILE *tracefh,
+ int type,
+ SIM_ADDR address,
+ int width,
+ char *comment,...)
+{
+ if (STATE & simTRACE) {
+ va_list ap;
+ fprintf(tracefh,"%d %s ; width %d ; ",
+ type,
+ pr_addr(address),
+ width);
+ va_start(ap,comment);
+ vfprintf(tracefh,comment,ap);
+ va_end(ap);
+ fprintf(tracefh,"\n");
+ }
+ /* NOTE: Since the "din" format will only accept 32bit addresses, and
+ we may be generating 64bit ones, we should put the hi-32bits of the
+ address into the comment field. */
-#ifdef DEBUG
- printf("DBG: StoreMemory: shift = %d MemElem = 0x%08X%08X\n",shift,WORD64HI(MemElem),WORD64LO(MemElem));
-#endif /* DEBUG */
+ /* TODO: Provide a buffer for the trace lines. We can then avoid
+ performing writes until the buffer is filled, or the file is
+ being closed. */
- if (BigEndianMem) {
- switch (AccessLength) { /* big-endian memory */
- case AccessLength_DOUBLEWORD :
- mem[index++] = (unsigned char)(MemElem >> 56);
- MemElem <<= 8;
- case AccessLength_SEPTIBYTE :
- mem[index++] = (unsigned char)(MemElem >> 56);
- MemElem <<= 8;
- case AccessLength_SEXTIBYTE :
- mem[index++] = (unsigned char)(MemElem >> 56);
- MemElem <<= 8;
- case AccessLength_QUINTIBYTE :
- mem[index++] = (unsigned char)(MemElem >> 56);
- MemElem <<= 8;
- case AccessLength_WORD :
- mem[index++] = (unsigned char)(MemElem >> 56);
- MemElem <<= 8;
- case AccessLength_TRIPLEBYTE :
- mem[index++] = (unsigned char)(MemElem >> 56);
- MemElem <<= 8;
- case AccessLength_HALFWORD :
- mem[index++] = (unsigned char)(MemElem >> 56);
- MemElem <<= 8;
- case AccessLength_BYTE :
- mem[index++] = (unsigned char)(MemElem >> 56);
- break;
- }
- } else {
- index += (AccessLength + 1);
- switch (AccessLength) { /* little-endian memory */
- case AccessLength_DOUBLEWORD :
- mem[--index] = (unsigned char)(MemElem >> 56);
- case AccessLength_SEPTIBYTE :
- mem[--index] = (unsigned char)(MemElem >> 48);
- case AccessLength_SEXTIBYTE :
- mem[--index] = (unsigned char)(MemElem >> 40);
- case AccessLength_QUINTIBYTE :
- mem[--index] = (unsigned char)(MemElem >> 32);
- case AccessLength_WORD :
- mem[--index] = (unsigned char)(MemElem >> 24);
- case AccessLength_TRIPLEBYTE :
- mem[--index] = (unsigned char)(MemElem >> 16);
- case AccessLength_HALFWORD :
- mem[--index] = (unsigned char)(MemElem >> 8);
- case AccessLength_BYTE :
- mem[--index] = (unsigned char)(MemElem >> 0);
- break;
- }
- }
- }
- }
+ /* NOTE: We could consider adding a comment field to the "din" file
+ produced using type 3 markers (unknown access). This would then
+ allow information about the program that the "din" is for, and
+ the MIPs world that was being simulated, to be placed into the
+ trace file. */
return;
}
+#endif /* TRACE */
+
+/*---------------------------------------------------------------------------*/
+/*-- simulator engine -------------------------------------------------------*/
+/*---------------------------------------------------------------------------*/
-/* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
-/* Order loads and stores to synchronise shared memory. Perform the
- action necessary to make the effects of groups of synchronizable
- loads and stores indicated by stype occur in the same order for all
- processors. */
static void
-SyncOperation(stype)
- int stype;
+ColdReset (SIM_DESC sd)
{
-#ifdef DEBUG
- callback->printf_filtered(callback,"SyncOperation(%d) : TODO\n",stype);
-#endif /* DEBUG */
- return;
+ int cpu_nr;
+ for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
+ {
+ sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
+ /* RESET: Fixed PC address: */
+ PC = UNSIGNED64 (0xFFFFFFFFBFC00000);
+ /* The reset vector address is in the unmapped, uncached memory space. */
+
+ SR &= ~(status_SR | status_TS | status_RP);
+ SR |= (status_ERL | status_BEV);
+
+ /* Cheat and allow access to the complete register set immediately */
+ if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT
+ && WITH_TARGET_WORD_BITSIZE == 64)
+ SR |= status_FR; /* 64bit registers */
+
+ /* Ensure that any instructions with pending register updates are
+ cleared: */
+ PENDING_INVALIDATE();
+
+ /* Initialise the FPU registers to the unknown state */
+ if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
+ {
+ int rn;
+ for (rn = 0; (rn < 32); rn++)
+ FPR_STATE[rn] = fmt_uninterpreted;
+ }
+
+ }
}
/* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
/* Signal an exception condition. This will result in an exception
that aborts the instruction. The instruction operation pseudocode
will never see a return from this function call. */
-static void
-SignalException(exception)
- int exception;
+
+void
+signal_exception (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ int exception,...)
{
+ int vector;
+
+#ifdef DEBUG
+ sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia));
+#endif /* DEBUG */
+
/* Ensure that any active atomic read/modify/write operation will fail: */
LLBIT = 0;
switch (exception) {
- /* TODO: For testing purposes I have been ignoring TRAPs. In
- reality we should either simulate them, or allow the user to
- ignore them at run-time. */
- case Trap :
- callback->printf_filtered(callback,"Ignoring instruction TRAP (PC 0x%08X%08X)\n",WORD64HI(IPC),WORD64LO(IPC));
+
+ case SystemCall :
+ {
+ va_list ap;
+ unsigned int instruction;
+ unsigned int code;
+
+ va_start(ap,exception);
+ instruction = va_arg(ap,unsigned int);
+ va_end(ap);
+
+ code = (instruction >> 6) & 0xFFFFF;
+
+ sim_io_eprintf(sd,"Ignoring instruction `syscall %d' (PC 0x%s)\n",
+ code, pr_addr(cia));
+ }
break;
+ case DebugBreakPoint :
+ if (! (Debug & Debug_DM))
+ {
+ if (INDELAYSLOT())
+ {
+ CANCELDELAYSLOT();
+
+ Debug |= Debug_DBD; /* signaled from within in delay slot */
+ DEPC = cia - 4; /* reference the branch instruction */
+ }
+ else
+ {
+ Debug &= ~Debug_DBD; /* not signaled from within a delay slot */
+ DEPC = cia;
+ }
+
+ Debug |= Debug_DM; /* in debugging mode */
+ Debug |= Debug_DBp; /* raising a DBp exception */
+ PC = 0xBFC00200;
+ sim_engine_restart (SD, CPU, NULL, NULL_CIA);
+ }
+ break;
+
case ReservedInstruction :
{
va_list ap;
space with suitable instruction values. For systems were
actual trap instructions are used, we would not need to
perform this magic. */
- if ((instruction & ~RSVD_INSTRUCTION_AMASK) == RSVD_INSTRUCTION) {
- sim_monitor(instruction & RSVD_INSTRUCTION_AMASK);
- PC = RA; /* simulate the return from the vector entry */
- /* NOTE: This assumes that a branch-and-link style
- instruction was used to enter the vector (which is the
- case with the current IDT monitor). */
- break; /* out of the switch statement */
- } /* else fall through to normal exception processing */
- callback->printf_filtered(callback,"DBG: ReservedInstruction 0x%08X at IPC = 0x%08X%08X\n",instruction,WORD64HI(IPC),WORD64LO(IPC));
+ if ((instruction & RSVD_INSTRUCTION_MASK) == RSVD_INSTRUCTION)
+ {
+ sim_monitor (SD, CPU, cia, ((instruction >> RSVD_INSTRUCTION_ARG_SHIFT) & RSVD_INSTRUCTION_ARG_MASK) );
+ /* NOTE: This assumes that a branch-and-link style
+ instruction was used to enter the vector (which is the
+ case with the current IDT monitor). */
+ sim_engine_restart (SD, CPU, NULL, RA);
+ }
+ /* Look for the mips16 entry and exit instructions, and
+ simulate a handler for them. */
+ else if ((cia & 1) != 0
+ && (instruction & 0xf81f) == 0xe809
+ && (instruction & 0x0c0) != 0x0c0)
+ {
+ mips16_entry (SD, CPU, cia, instruction);
+ sim_engine_restart (sd, NULL, NULL, NULL_CIA);
+ }
+ /* else fall through to normal exception processing */
+ sim_io_eprintf(sd,"ReservedInstruction at PC = 0x%s\n", pr_addr (cia));
}
- default:
-#if 1 /* def DEBUG */
- callback->printf_filtered(callback,"DBG: SignalException(%d) IPC = 0x%08X%08X\n",exception,WORD64HI(IPC),WORD64LO(IPC));
+ case BreakPoint:
+#ifdef DEBUG
+ sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia));
#endif /* DEBUG */
+ /* Keep a copy of the current A0 in-case this is the program exit
+ breakpoint: */
+ {
+ va_list ap;
+ unsigned int instruction;
+ va_start(ap, exception);
+ instruction = va_arg(ap,unsigned int);
+ va_end(ap);
+ /* Check for our special terminating BREAK: */
+ if ((instruction & HALT_INSTRUCTION_MASK)
+ == (HALT_INSTRUCTION & HALT_INSTRUCTION_MASK))
+ {
+ sim_engine_halt (SD, CPU, NULL, cia,
+ sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
+ }
+ }
+ if (STATE & simDELAYSLOT)
+ PC = cia - 4; /* reference the branch instruction */
+ else
+ PC = cia;
+ sim_engine_halt (SD, CPU, NULL, cia,
+ sim_stopped, SIM_SIGTRAP);
+
+ default:
/* Store exception code into current exception id variable (used
by exit code): */
/* TODO: If not simulating exceptions then stop the simulator
execution. At the moment we always stop the simulation. */
- state |= (simSTOP | simEXCEPTION);
- CAUSE = (exception << 2);
- if (state & simDELAYSLOT) {
- CAUSE |= cause_BD;
- EPC = (IPC - 4); /* reference the branch instruction */
- } else
- EPC = IPC;
- /* The following is so that the simulator will continue from the
- exception address on breakpoint operations. */
- PC = EPC;
- break;
+
+ /* See figure 5-17 for an outline of the code below */
+ if (! (SR & status_EXL))
+ {
+ CAUSE = (exception << 2);
+ if (STATE & simDELAYSLOT)
+ {
+ STATE &= ~simDELAYSLOT;
+ CAUSE |= cause_BD;
+ EPC = (cia - 4); /* reference the branch instruction */
+ }
+ else
+ EPC = cia;
+ /* FIXME: TLB et.al. */
+ vector = 0x180;
+ }
+ else
+ {
+ CAUSE = (exception << 2);
+ vector = 0x180;
+ }
+ SR |= status_EXL;
+ /* Store exception code into current exception id variable (used
+ by exit code): */
+ if (SR & status_BEV)
+ PC = (signed)0xBFC00200 + 0x180;
+ else
+ PC = (signed)0x80000000 + 0x180;
+
+ switch ((CAUSE >> 2) & 0x1F)
+ {
+ case Interrupt:
+ /* Interrupts arrive during event processing, no need to
+ restart */
+ return;
+
+ case TLBModification:
+ case TLBLoad:
+ case TLBStore:
+ case AddressLoad:
+ case AddressStore:
+ case InstructionFetch:
+ case DataReference:
+ /* The following is so that the simulator will continue from the
+ exception address on breakpoint operations. */
+ PC = EPC;
+ sim_engine_halt (SD, CPU, NULL, NULL_CIA,
+ sim_stopped, SIM_SIGBUS);
+
+ case ReservedInstruction:
+ case CoProcessorUnusable:
+ PC = EPC;
+ sim_engine_halt (SD, CPU, NULL, NULL_CIA,
+ sim_stopped, SIM_SIGILL);
+
+ case IntegerOverflow:
+ case FPE:
+ sim_engine_halt (SD, CPU, NULL, NULL_CIA,
+ sim_stopped, SIM_SIGFPE);
+
+ case Trap:
+ sim_engine_restart (SD, CPU, NULL, PC);
+ break;
+
+ case Watch:
+ case SystemCall:
+ PC = EPC;
+ sim_engine_halt (SD, CPU, NULL, NULL_CIA,
+ sim_stopped, SIM_SIGTRAP);
+
+ case BreakPoint:
+ PC = EPC;
+ sim_engine_abort (SD, CPU, NULL_CIA,
+ "FATAL: Should not encounter a breakpoint\n");
+
+ default : /* Unknown internal exception */
+ PC = EPC;
+ sim_engine_halt (SD, CPU, NULL, NULL_CIA,
+ sim_stopped, SIM_SIGABRT);
+
+ }
case SimulatorFault:
{
char *msg;
va_start(ap,exception);
msg = va_arg(ap,char *);
- fprintf(stderr,"FATAL: Simulator error \"%s\"\n",msg);
va_end(ap);
+ sim_engine_abort (SD, CPU, NULL_CIA,
+ "FATAL: Simulator error \"%s\"\n",msg);
}
- exit(1);
}
return;
simple, we just don't bother updating the destination register, so
the overall result will be undefined. If desired we can stop the
simulator by raising a pseudo-exception. */
+#define UndefinedResult() undefined_result (sd,cia)
static void
-UndefinedResult()
+undefined_result(sd,cia)
+ SIM_DESC sd;
+ address_word cia;
{
- callback->printf_filtered(callback,"UndefinedResult: IPC = 0x%08X%08X\n",WORD64HI(IPC),WORD64LO(IPC));
+ sim_io_eprintf(sd,"UndefinedResult: PC = 0x%s\n",pr_addr(cia));
#if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */
state |= simSTOP;
#endif
}
#endif /* WARN_RESULT */
-static void
-CacheOp(op,pAddr,vAddr,instruction)
- int op;
- uword64 pAddr;
- uword64 vAddr;
- unsigned int instruction;
-{
- static int icache_warning = 0;
- static int dcache_warning = 0;
-
- /* If CP0 is not useable (User or Supervisor mode) and the CP0
- enable bit in the Status Register is clear - a coprocessor
- unusable exception is taken. */
-#if 0
- callback->printf_filtered(callback,"TODO: Cache availability checking (PC = 0x%08X%08X)\n",WORD64HI(IPC),WORD64LO(IPC));
-#endif
-
- switch (op & 0x3) {
- case 0: /* instruction cache */
- switch (op >> 2) {
- case 0: /* Index Invalidate */
- case 1: /* Index Load Tag */
- case 2: /* Index Store Tag */
- case 4: /* Hit Invalidate */
- case 5: /* Fill */
- case 6: /* Hit Writeback */
- if (!icache_warning)
- {
- callback->printf_filtered(callback,"SIM Warning: Instruction CACHE operation %d to be coded\n",(op >> 2));
- icache_warning = 1;
- }
- break;
-
- default:
- SignalException(ReservedInstruction,instruction);
- break;
- }
- break;
-
- case 1: /* data cache */
- switch (op >> 2) {
- case 0: /* Index Writeback Invalidate */
- case 1: /* Index Load Tag */
- case 2: /* Index Store Tag */
- case 3: /* Create Dirty */
- case 4: /* Hit Invalidate */
- case 5: /* Hit Writeback Invalidate */
- case 6: /* Hit Writeback */
- if (!dcache_warning)
- {
- callback->printf_filtered(callback,"SIM Warning: Data CACHE operation %d to be coded\n",(op >> 2));
- dcache_warning = 1;
- }
- break;
-
- default:
- SignalException(ReservedInstruction,instruction);
- break;
- }
- break;
-
- default: /* unrecognised cache ID */
- SignalException(ReservedInstruction,instruction);
- break;
- }
-
- return;
-}
-
/*-- FPU support routines ---------------------------------------------------*/
-#if defined(HASFPU) /* Only needed when building FPU aware simulators */
-
-#if 1
-#define SizeFGR() (GPRLEN)
-#else
-/* They depend on the CPU being simulated */
-#define SizeFGR() ((PROCESSOR_64BIT && ((SR & status_FR) == 1)) ? 64 : 32)
-#endif
-
/* Numbers are held in normalized form. The SINGLE and DOUBLE binary
formats conform to ANSI/IEEE Std 754-1985. */
/* SINGLE precision floating:
#define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : "<format error>"))))))
#endif /* DEBUG */
-static uword64
-ValueFPR(fpr,fmt)
- int fpr;
- FP_formats fmt;
+uword64
+value_fpr (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ int fpr,
+ FP_formats fmt)
{
- uword64 value;
+ uword64 value = 0;
int err = 0;
/* Treat unused register values, as fixed-point 64bit values: */
#if 1
/* If request to read data as "uninterpreted", then use the current
encoding: */
- fmt = fpr_state[fpr];
+ fmt = FPR_STATE[fpr];
#else
fmt = fmt_long;
#endif
/* For values not yet accessed, set to the desired format: */
- if (fpr_state[fpr] == fmt_uninterpreted) {
- fpr_state[fpr] = fmt;
+ if (FPR_STATE[fpr] == fmt_uninterpreted) {
+ FPR_STATE[fpr] = fmt;
#ifdef DEBUG
printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr,DOFMT(fmt));
#endif /* DEBUG */
}
- if (fmt != fpr_state[fpr]) {
- callback->printf_filtered(callback,"Warning: FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%08X%08X)\n",fpr,DOFMT(fpr_state[fpr]),DOFMT(fmt),WORD64HI(IPC),WORD64LO(IPC));
- fpr_state[fpr] = fmt_unknown;
+ if (fmt != FPR_STATE[fpr]) {
+ sim_io_eprintf(sd,"FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",fpr,DOFMT(FPR_STATE[fpr]),DOFMT(fmt),pr_addr(cia));
+ FPR_STATE[fpr] = fmt_unknown;
}
- if (fpr_state[fpr] == fmt_unknown) {
+ if (FPR_STATE[fpr] == fmt_unknown) {
/* Set QNaN value: */
switch (fmt) {
case fmt_single:
err = -1;
break;
}
- } else if ((fpr & 1) == 0) { /* even registers only */
+ } else {
switch (fmt) {
case fmt_single:
case fmt_word:
case fmt_uninterpreted:
case fmt_double:
case fmt_long:
- value = ((FGR[fpr+1] << 32) | (FGR[fpr] & 0xFFFFFFFF));
+ if ((fpr & 1) == 0) { /* even registers only */
+ value = ((((uword64)FGR[fpr+1]) << 32) | (FGR[fpr] & 0xFFFFFFFF));
+ } else {
+ SignalException(ReservedInstruction,0);
+ }
break;
default :
}
if (err)
- SignalException(SimulatorFault,"Unrecognised FP format in ValueFPR()");
+ SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR()");
#ifdef DEBUG
- printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%08X%08X : PC = 0x%08X%08X : SizeFGR() = %d\n",fpr,DOFMT(fmt),WORD64HI(value),WORD64LO(value),WORD64HI(IPC),WORD64LO(IPC),SizeFGR());
+ printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(cia),SizeFGR());
#endif /* DEBUG */
return(value);
}
-static void
-StoreFPR(fpr,fmt,value)
- int fpr;
- FP_formats fmt;
- uword64 value;
+void
+store_fpr (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ int fpr,
+ FP_formats fmt,
+ uword64 value)
{
int err = 0;
#ifdef DEBUG
- printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%08X%08X : PC = 0x%08X%08X : SizeFGR() = %d\n",fpr,DOFMT(fmt),WORD64HI(value),WORD64LO(value),WORD64HI(IPC),WORD64LO(IPC),SizeFGR());
+ printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(cia),SizeFGR());
#endif /* DEBUG */
if (SizeFGR() == 64) {
switch (fmt) {
+ case fmt_uninterpreted_32:
+ fmt = fmt_uninterpreted;
case fmt_single :
case fmt_word :
FGR[fpr] = (((uword64)0xDEADC0DE << 32) | (value & 0xFFFFFFFF));
- fpr_state[fpr] = fmt;
+ FPR_STATE[fpr] = fmt;
break;
+ case fmt_uninterpreted_64:
+ fmt = fmt_uninterpreted;
case fmt_uninterpreted:
case fmt_double :
case fmt_long :
FGR[fpr] = value;
- fpr_state[fpr] = fmt;
+ FPR_STATE[fpr] = fmt;
break;
default :
- fpr_state[fpr] = fmt_unknown;
+ FPR_STATE[fpr] = fmt_unknown;
err = -1;
break;
}
- } else if ((fpr & 1) == 0) { /* even register number only */
+ } else {
switch (fmt) {
+ case fmt_uninterpreted_32:
+ fmt = fmt_uninterpreted;
case fmt_single :
case fmt_word :
- FGR[fpr+1] = 0xDEADC0DE;
FGR[fpr] = (value & 0xFFFFFFFF);
- fpr_state[fpr + 1] = fmt;
- fpr_state[fpr] = fmt;
+ FPR_STATE[fpr] = fmt;
break;
+ case fmt_uninterpreted_64:
+ fmt = fmt_uninterpreted;
case fmt_uninterpreted:
case fmt_double :
case fmt_long :
- FGR[fpr+1] = (value >> 32);
- FGR[fpr] = (value & 0xFFFFFFFF);
- fpr_state[fpr + 1] = fmt;
- fpr_state[fpr] = fmt;
+ if ((fpr & 1) == 0) { /* even register number only */
+ FGR[fpr+1] = (value >> 32);
+ FGR[fpr] = (value & 0xFFFFFFFF);
+ FPR_STATE[fpr + 1] = fmt;
+ FPR_STATE[fpr] = fmt;
+ } else {
+ FPR_STATE[fpr] = fmt_unknown;
+ FPR_STATE[fpr + 1] = fmt_unknown;
+ SignalException(ReservedInstruction,0);
+ }
break;
default :
- fpr_state[fpr] = fmt_unknown;
+ FPR_STATE[fpr] = fmt_unknown;
err = -1;
break;
}
#endif /* WARN_RESULT */
if (err)
- SignalException(SimulatorFault,"Unrecognised FP format in StoreFPR()");
+ SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR()");
#ifdef DEBUG
- printf("DBG: StoreFPR: fpr[%d] = 0x%08X%08X (format %s)\n",fpr,WORD64HI(FGR[fpr]),WORD64LO(FGR[fpr]),DOFMT(fmt));
+ printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr,pr_addr(FGR[fpr]),DOFMT(fmt));
#endif /* DEBUG */
return;
}
-static int
+int
NaN(op,fmt)
uword64 op;
FP_formats fmt;
{
int boolean = 0;
-
- /* Check if (((E - bias) == (E_max + 1)) && (fraction != 0)). We
- know that the exponent field is biased... we we cheat and avoid
- removing the bias value. */
switch (fmt) {
case fmt_single:
- boolean = ((FP_S_be(op) == 0xFF) && (FP_S_f(op) != 0));
- /* We could use "FP_S_fb(1,op)" to ascertain whether we are
- dealing with a SNaN or QNaN */
- break;
- case fmt_double:
- boolean = ((FP_D_be(op) == 0x7FF) && (FP_D_f(op) != 0));
- /* We could use "FP_S_fb(1,op)" to ascertain whether we are
- dealing with a SNaN or QNaN */
- break;
case fmt_word:
- boolean = (op == FPQNaN_WORD);
- break;
+ {
+ sim_fpu wop;
+ sim_fpu_32to (&wop, op);
+ boolean = sim_fpu_is_nan (&wop);
+ break;
+ }
+ case fmt_double:
case fmt_long:
- boolean = (op == FPQNaN_LONG);
- break;
+ {
+ sim_fpu wop;
+ sim_fpu_64to (&wop, op);
+ boolean = sim_fpu_is_nan (&wop);
+ break;
+ }
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
}
#ifdef DEBUG
-printf("DBG: NaN: returning %d for 0x%08X%08X (format = %s)\n",boolean,WORD64HI(op),WORD64LO(op),DOFMT(fmt));
+printf("DBG: NaN: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt));
#endif /* DEBUG */
return(boolean);
}
-static int
+int
Infinity(op,fmt)
uword64 op;
FP_formats fmt;
int boolean = 0;
#ifdef DEBUG
- printf("DBG: Infinity: format %s 0x%08X%08X (PC = 0x%08X%08X)\n",DOFMT(fmt),WORD64HI(op),WORD64LO(op),WORD64HI(IPC),WORD64LO(IPC));
+ printf("DBG: Infinity: format %s 0x%s\n",DOFMT(fmt),pr_addr(op));
#endif /* DEBUG */
- /* Check if (((E - bias) == (E_max + 1)) && (fraction == 0)). We
- know that the exponent field is biased... we we cheat and avoid
- removing the bias value. */
switch (fmt) {
case fmt_single:
- boolean = ((FP_S_be(op) == 0xFF) && (FP_S_f(op) == 0));
- break;
+ {
+ sim_fpu wop;
+ sim_fpu_32to (&wop, op);
+ boolean = sim_fpu_is_infinity (&wop);
+ break;
+ }
case fmt_double:
- boolean = ((FP_D_be(op) == 0x7FF) && (FP_D_f(op) == 0));
- break;
+ {
+ sim_fpu wop;
+ sim_fpu_64to (&wop, op);
+ boolean = sim_fpu_is_infinity (&wop);
+ break;
+ }
default:
printf("DBG: TODO: unrecognised format (%s) for Infinity check\n",DOFMT(fmt));
break;
}
#ifdef DEBUG
- printf("DBG: Infinity: returning %d for 0x%08X%08X (format = %s)\n",boolean,WORD64HI(op),WORD64LO(op),DOFMT(fmt));
+ printf("DBG: Infinity: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt));
#endif /* DEBUG */
return(boolean);
}
-static int
+int
Less(op1,op2,fmt)
uword64 op1;
uword64 op2;
/* Argument checking already performed by the FPCOMPARE code */
#ifdef DEBUG
- printf("DBG: Less: %s: op1 = 0x%08X%08X : op2 = 0x%08X%08X\n",DOFMT(fmt),WORD64HI(op1),WORD64LO(op1),WORD64HI(op2),WORD64LO(op2));
+ printf("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
#endif /* DEBUG */
/* The format type should already have been checked: */
switch (fmt) {
case fmt_single:
{
- unsigned int wop1 = (unsigned int)op1;
- unsigned int wop2 = (unsigned int)op2;
- boolean = (*(float *)&wop1 < *(float *)&wop2);
+ sim_fpu wop1;
+ sim_fpu wop2;
+ sim_fpu_32to (&wop1, op1);
+ sim_fpu_32to (&wop2, op2);
+ boolean = sim_fpu_is_lt (&wop1, &wop2);
+ break;
}
- break;
case fmt_double:
- boolean = (*(double *)&op1 < *(double *)&op2);
- break;
+ {
+ sim_fpu wop1;
+ sim_fpu wop2;
+ sim_fpu_64to (&wop1, op1);
+ sim_fpu_64to (&wop2, op2);
+ boolean = sim_fpu_is_lt (&wop1, &wop2);
+ break;
+ }
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
}
#ifdef DEBUG
return(boolean);
}
-static int
+int
Equal(op1,op2,fmt)
uword64 op1;
uword64 op2;
/* Argument checking already performed by the FPCOMPARE code */
#ifdef DEBUG
- printf("DBG: Equal: %s: op1 = 0x%08X%08X : op2 = 0x%08X%08X\n",DOFMT(fmt),WORD64HI(op1),WORD64LO(op1),WORD64HI(op2),WORD64LO(op2));
+ printf("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
#endif /* DEBUG */
/* The format type should already have been checked: */
switch (fmt) {
case fmt_single:
- boolean = ((op1 & 0xFFFFFFFF) == (op2 & 0xFFFFFFFF));
- break;
+ {
+ sim_fpu wop1;
+ sim_fpu wop2;
+ sim_fpu_32to (&wop1, op1);
+ sim_fpu_32to (&wop2, op2);
+ boolean = sim_fpu_is_eq (&wop1, &wop2);
+ break;
+ }
case fmt_double:
- boolean = (op1 == op2);
- break;
+ {
+ sim_fpu wop1;
+ sim_fpu wop2;
+ sim_fpu_64to (&wop1, op1);
+ sim_fpu_64to (&wop2, op2);
+ boolean = sim_fpu_is_eq (&wop1, &wop2);
+ break;
+ }
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
}
#ifdef DEBUG
return(boolean);
}
-static uword64
+uword64
AbsoluteValue(op,fmt)
uword64 op;
FP_formats fmt;
{
- uword64 result;
+ uword64 result = 0;
#ifdef DEBUG
- printf("DBG: AbsoluteValue: %s: op = 0x%08X%08X\n",DOFMT(fmt),WORD64HI(op),WORD64LO(op));
+ printf("DBG: AbsoluteValue: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
#endif /* DEBUG */
/* The format type should already have been checked: */
switch (fmt) {
case fmt_single:
{
- unsigned int wop = (unsigned int)op;
- float tmp = ((float)fabs((double)*(float *)&wop));
- result = (uword64)*(unsigned int *)&tmp;
+ sim_fpu wop;
+ unsigned32 ans;
+ sim_fpu_32to (&wop, op);
+ sim_fpu_abs (&wop, &wop);
+ sim_fpu_to32 (&ans, &wop);
+ result = ans;
+ break;
}
- break;
case fmt_double:
{
- double tmp = (fabs(*(double *)&op));
- result = *(uword64 *)&tmp;
+ sim_fpu wop;
+ unsigned64 ans;
+ sim_fpu_64to (&wop, op);
+ sim_fpu_abs (&wop, &wop);
+ sim_fpu_to64 (&ans, &wop);
+ result = ans;
+ break;
}
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
}
return(result);
}
-static uword64
+uword64
Negate(op,fmt)
uword64 op;
FP_formats fmt;
{
- uword64 result;
+ uword64 result = 0;
#ifdef DEBUG
- printf("DBG: Negate: %s: op = 0x%08X%08X\n",DOFMT(fmt),WORD64HI(op),WORD64LO(op));
+ printf("DBG: Negate: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
#endif /* DEBUG */
/* The format type should already have been checked: */
switch (fmt) {
case fmt_single:
{
- unsigned int wop = (unsigned int)op;
- float tmp = ((float)0.0 - *(float *)&wop);
- result = (uword64)*(unsigned int *)&tmp;
+ sim_fpu wop;
+ unsigned32 ans;
+ sim_fpu_32to (&wop, op);
+ sim_fpu_neg (&wop, &wop);
+ sim_fpu_to32 (&ans, &wop);
+ result = ans;
+ break;
}
- break;
case fmt_double:
{
- double tmp = ((double)0.0 - *(double *)&op);
- result = *(uword64 *)&tmp;
+ sim_fpu wop;
+ unsigned64 ans;
+ sim_fpu_64to (&wop, op);
+ sim_fpu_neg (&wop, &wop);
+ sim_fpu_to64 (&ans, &wop);
+ result = ans;
+ break;
}
- break;
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
}
return(result);
}
-static uword64
+uword64
Add(op1,op2,fmt)
uword64 op1;
uword64 op2;
FP_formats fmt;
{
- uword64 result;
+ uword64 result = 0;
#ifdef DEBUG
- printf("DBG: Add: %s: op1 = 0x%08X%08X : op2 = 0x%08X%08X\n",DOFMT(fmt),WORD64HI(op1),WORD64LO(op1),WORD64HI(op2),WORD64LO(op2));
+ printf("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
#endif /* DEBUG */
/* The registers must specify FPRs valid for operands of type
switch (fmt) {
case fmt_single:
{
- unsigned int wop1 = (unsigned int)op1;
- unsigned int wop2 = (unsigned int)op2;
- float tmp = (*(float *)&wop1 + *(float *)&wop2);
- result = (uword64)*(unsigned int *)&tmp;
+ sim_fpu wop1;
+ sim_fpu wop2;
+ sim_fpu ans;
+ unsigned32 res;
+ sim_fpu_32to (&wop1, op1);
+ sim_fpu_32to (&wop2, op2);
+ sim_fpu_add (&ans, &wop1, &wop2);
+ sim_fpu_to32 (&res, &ans);
+ result = res;
+ break;
}
- break;
case fmt_double:
{
- double tmp = (*(double *)&op1 + *(double *)&op2);
- result = *(uword64 *)&tmp;
+ sim_fpu wop1;
+ sim_fpu wop2;
+ sim_fpu ans;
+ unsigned64 res;
+ sim_fpu_64to (&wop1, op1);
+ sim_fpu_64to (&wop2, op2);
+ sim_fpu_add (&ans, &wop1, &wop2);
+ sim_fpu_to64 (&res, &ans);
+ result = res;
+ break;
}
- break;
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
}
#ifdef DEBUG
- printf("DBG: Add: returning 0x%08X%08X (format = %s)\n",WORD64HI(result),WORD64LO(result),DOFMT(fmt));
+ printf("DBG: Add: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
#endif /* DEBUG */
return(result);
}
-static uword64
+uword64
Sub(op1,op2,fmt)
uword64 op1;
uword64 op2;
FP_formats fmt;
{
- uword64 result;
+ uword64 result = 0;
#ifdef DEBUG
- printf("DBG: Sub: %s: op1 = 0x%08X%08X : op2 = 0x%08X%08X\n",DOFMT(fmt),WORD64HI(op1),WORD64LO(op1),WORD64HI(op2),WORD64LO(op2));
+ printf("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
#endif /* DEBUG */
/* The registers must specify FPRs valid for operands of type
switch (fmt) {
case fmt_single:
{
- unsigned int wop1 = (unsigned int)op1;
- unsigned int wop2 = (unsigned int)op2;
- float tmp = (*(float *)&wop1 - *(float *)&wop2);
- result = (uword64)*(unsigned int *)&tmp;
+ sim_fpu wop1;
+ sim_fpu wop2;
+ sim_fpu ans;
+ unsigned32 res;
+ sim_fpu_32to (&wop1, op1);
+ sim_fpu_32to (&wop2, op2);
+ sim_fpu_sub (&ans, &wop1, &wop2);
+ sim_fpu_to32 (&res, &ans);
+ result = res;
}
break;
case fmt_double:
{
- double tmp = (*(double *)&op1 - *(double *)&op2);
- result = *(uword64 *)&tmp;
+ sim_fpu wop1;
+ sim_fpu wop2;
+ sim_fpu ans;
+ unsigned64 res;
+ sim_fpu_64to (&wop1, op1);
+ sim_fpu_64to (&wop2, op2);
+ sim_fpu_sub (&ans, &wop1, &wop2);
+ sim_fpu_to64 (&res, &ans);
+ result = res;
}
break;
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
}
#ifdef DEBUG
- printf("DBG: Sub: returning 0x%08X%08X (format = %s)\n",WORD64HI(result),WORD64LO(result),DOFMT(fmt));
+ printf("DBG: Sub: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
#endif /* DEBUG */
return(result);
}
-static uword64
+uword64
Multiply(op1,op2,fmt)
uword64 op1;
uword64 op2;
FP_formats fmt;
{
- uword64 result;
+ uword64 result = 0;
#ifdef DEBUG
- printf("DBG: Multiply: %s: op1 = 0x%08X%08X : op2 = 0x%08X%08X\n",DOFMT(fmt),WORD64HI(op1),WORD64LO(op1),WORD64HI(op2),WORD64LO(op2));
+ printf("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
#endif /* DEBUG */
/* The registers must specify FPRs valid for operands of type
switch (fmt) {
case fmt_single:
{
- unsigned int wop1 = (unsigned int)op1;
- unsigned int wop2 = (unsigned int)op2;
- float tmp = (*(float *)&wop1 * *(float *)&wop2);
- result = (uword64)*(unsigned int *)&tmp;
+ sim_fpu wop1;
+ sim_fpu wop2;
+ sim_fpu ans;
+ unsigned32 res;
+ sim_fpu_32to (&wop1, op1);
+ sim_fpu_32to (&wop2, op2);
+ sim_fpu_mul (&ans, &wop1, &wop2);
+ sim_fpu_to32 (&res, &ans);
+ result = res;
+ break;
}
- break;
case fmt_double:
{
- double tmp = (*(double *)&op1 * *(double *)&op2);
- result = *(uword64 *)&tmp;
+ sim_fpu wop1;
+ sim_fpu wop2;
+ sim_fpu ans;
+ unsigned64 res;
+ sim_fpu_64to (&wop1, op1);
+ sim_fpu_64to (&wop2, op2);
+ sim_fpu_mul (&ans, &wop1, &wop2);
+ sim_fpu_to64 (&res, &ans);
+ result = res;
+ break;
}
- break;
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
}
#ifdef DEBUG
- printf("DBG: Multiply: returning 0x%08X%08X (format = %s)\n",WORD64HI(result),WORD64LO(result),DOFMT(fmt));
+ printf("DBG: Multiply: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
#endif /* DEBUG */
return(result);
}
-static uword64
+uword64
Divide(op1,op2,fmt)
uword64 op1;
uword64 op2;
FP_formats fmt;
{
- uword64 result;
+ uword64 result = 0;
#ifdef DEBUG
- printf("DBG: Divide: %s: op1 = 0x%08X%08X : op2 = 0x%08X%08X\n",DOFMT(fmt),WORD64HI(op1),WORD64LO(op1),WORD64HI(op2),WORD64LO(op2));
+ printf("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
#endif /* DEBUG */
/* The registers must specify FPRs valid for operands of type
switch (fmt) {
case fmt_single:
{
- unsigned int wop1 = (unsigned int)op1;
- unsigned int wop2 = (unsigned int)op2;
- float tmp = (*(float *)&wop1 / *(float *)&wop2);
- result = (uword64)*(unsigned int *)&tmp;
+ sim_fpu wop1;
+ sim_fpu wop2;
+ sim_fpu ans;
+ unsigned32 res;
+ sim_fpu_32to (&wop1, op1);
+ sim_fpu_32to (&wop2, op2);
+ sim_fpu_div (&ans, &wop1, &wop2);
+ sim_fpu_to32 (&res, &ans);
+ result = res;
+ break;
}
- break;
case fmt_double:
{
- double tmp = (*(double *)&op1 / *(double *)&op2);
- result = *(uword64 *)&tmp;
+ sim_fpu wop1;
+ sim_fpu wop2;
+ sim_fpu ans;
+ unsigned64 res;
+ sim_fpu_64to (&wop1, op1);
+ sim_fpu_64to (&wop2, op2);
+ sim_fpu_div (&ans, &wop1, &wop2);
+ sim_fpu_to64 (&res, &ans);
+ result = res;
+ break;
}
- break;
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
}
#ifdef DEBUG
- printf("DBG: Divide: returning 0x%08X%08X (format = %s)\n",WORD64HI(result),WORD64LO(result),DOFMT(fmt));
+ printf("DBG: Divide: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
#endif /* DEBUG */
return(result);
}
-static uword64
+uword64 UNUSED
Recip(op,fmt)
uword64 op;
FP_formats fmt;
{
- uword64 result;
+ uword64 result = 0;
#ifdef DEBUG
- printf("DBG: Recip: %s: op = 0x%08X%08X\n",DOFMT(fmt),WORD64HI(op),WORD64LO(op));
+ printf("DBG: Recip: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
#endif /* DEBUG */
/* The registers must specify FPRs valid for operands of type
switch (fmt) {
case fmt_single:
{
- unsigned int wop = (unsigned int)op;
- float tmp = ((float)1.0 / *(float *)&wop);
- result = (uword64)*(unsigned int *)&tmp;
+ sim_fpu wop;
+ sim_fpu ans;
+ unsigned32 res;
+ sim_fpu_32to (&wop, op);
+ sim_fpu_inv (&ans, &wop);
+ sim_fpu_to32 (&res, &ans);
+ result = res;
+ break;
}
- break;
case fmt_double:
{
- double tmp = ((double)1.0 / *(double *)&op);
- result = *(uword64 *)&tmp;
+ sim_fpu wop;
+ sim_fpu ans;
+ unsigned64 res;
+ sim_fpu_64to (&wop, op);
+ sim_fpu_inv (&ans, &wop);
+ sim_fpu_to64 (&res, &ans);
+ result = res;
+ break;
}
- break;
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
}
#ifdef DEBUG
- printf("DBG: Recip: returning 0x%08X%08X (format = %s)\n",WORD64HI(result),WORD64LO(result),DOFMT(fmt));
+ printf("DBG: Recip: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
#endif /* DEBUG */
return(result);
}
-static uword64
+uword64
SquareRoot(op,fmt)
uword64 op;
FP_formats fmt;
{
- uword64 result;
+ uword64 result = 0;
+
+#ifdef DEBUG
+ printf("DBG: SquareRoot: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
+#endif /* DEBUG */
+
+ /* The registers must specify FPRs valid for operands of type
+ "fmt". If they are not valid, the result is undefined. */
+
+ /* The format type should already have been checked: */
+ switch (fmt) {
+ case fmt_single:
+ {
+ sim_fpu wop;
+ sim_fpu ans;
+ unsigned32 res;
+ sim_fpu_32to (&wop, op);
+ sim_fpu_sqrt (&ans, &wop);
+ sim_fpu_to32 (&res, &ans);
+ result = res;
+ break;
+ }
+ case fmt_double:
+ {
+ sim_fpu wop;
+ sim_fpu ans;
+ unsigned64 res;
+ sim_fpu_64to (&wop, op);
+ sim_fpu_sqrt (&ans, &wop);
+ sim_fpu_to64 (&res, &ans);
+ result = res;
+ break;
+ }
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
+ }
+
+#ifdef DEBUG
+ printf("DBG: SquareRoot: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
+#endif /* DEBUG */
+
+ return(result);
+}
+
+#if 0
+uword64
+Max (uword64 op1,
+ uword64 op2,
+ FP_formats fmt)
+{
+ int cmp;
+ unsigned64 result;
+
+#ifdef DEBUG
+ printf("DBG: Max: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
+#endif /* DEBUG */
+
+ /* The registers must specify FPRs valid for operands of type
+ "fmt". If they are not valid, the result is undefined. */
+
+ /* The format type should already have been checked: */
+ switch (fmt)
+ {
+ case fmt_single:
+ {
+ sim_fpu wop1;
+ sim_fpu wop2;
+ sim_fpu_32to (&wop1, op1);
+ sim_fpu_32to (&wop2, op2);
+ cmp = sim_fpu_cmp (&wop1, &wop2);
+ break;
+ }
+ case fmt_double:
+ {
+ sim_fpu wop1;
+ sim_fpu wop2;
+ sim_fpu_64to (&wop1, op1);
+ sim_fpu_64to (&wop2, op2);
+ cmp = sim_fpu_cmp (&wop1, &wop2);
+ break;
+ }
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
+ }
+
+ switch (cmp)
+ {
+ case SIM_FPU_IS_SNAN:
+ case SIM_FPU_IS_QNAN:
+ result = op1;
+ case SIM_FPU_IS_NINF:
+ case SIM_FPU_IS_NNUMBER:
+ case SIM_FPU_IS_NDENORM:
+ case SIM_FPU_IS_NZERO:
+ result = op2; /* op1 - op2 < 0 */
+ case SIM_FPU_IS_PINF:
+ case SIM_FPU_IS_PNUMBER:
+ case SIM_FPU_IS_PDENORM:
+ case SIM_FPU_IS_PZERO:
+ result = op1; /* op1 - op2 > 0 */
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
+ }
+
+#ifdef DEBUG
+ printf("DBG: Max: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
+#endif /* DEBUG */
+
+ return(result);
+}
+#endif
+
+#if 0
+uword64
+Min (uword64 op1,
+ uword64 op2,
+ FP_formats fmt)
+{
+ int cmp;
+ unsigned64 result;
#ifdef DEBUG
- printf("DBG: SquareRoot: %s: op = 0x%08X%08X\n",DOFMT(fmt),WORD64HI(op),WORD64LO(op));
+ printf("DBG: Min: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
#endif /* DEBUG */
/* The registers must specify FPRs valid for operands of type
"fmt". If they are not valid, the result is undefined. */
/* The format type should already have been checked: */
- switch (fmt) {
- case fmt_single:
+ switch (fmt)
{
- unsigned int wop = (unsigned int)op;
- float tmp = ((float)sqrt((double)*(float *)&wop));
- result = (uword64)*(unsigned int *)&tmp;
+ case fmt_single:
+ {
+ sim_fpu wop1;
+ sim_fpu wop2;
+ sim_fpu_32to (&wop1, op1);
+ sim_fpu_32to (&wop2, op2);
+ cmp = sim_fpu_cmp (&wop1, &wop2);
+ break;
+ }
+ case fmt_double:
+ {
+ sim_fpu wop1;
+ sim_fpu wop2;
+ sim_fpu_64to (&wop1, op1);
+ sim_fpu_64to (&wop2, op2);
+ cmp = sim_fpu_cmp (&wop1, &wop2);
+ break;
+ }
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
}
- break;
- case fmt_double:
+
+ switch (cmp)
{
- double tmp = (sqrt(*(double *)&op));
- result = *(uword64 *)&tmp;
+ case SIM_FPU_IS_SNAN:
+ case SIM_FPU_IS_QNAN:
+ result = op1;
+ case SIM_FPU_IS_NINF:
+ case SIM_FPU_IS_NNUMBER:
+ case SIM_FPU_IS_NDENORM:
+ case SIM_FPU_IS_NZERO:
+ result = op1; /* op1 - op2 < 0 */
+ case SIM_FPU_IS_PINF:
+ case SIM_FPU_IS_PNUMBER:
+ case SIM_FPU_IS_PDENORM:
+ case SIM_FPU_IS_PZERO:
+ result = op2; /* op1 - op2 > 0 */
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
}
- break;
- }
#ifdef DEBUG
- printf("DBG: SquareRoot: returning 0x%08X%08X (format = %s)\n",WORD64HI(result),WORD64LO(result),DOFMT(fmt));
+ printf("DBG: Min: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
#endif /* DEBUG */
return(result);
}
+#endif
-static uword64
-Convert(rm,op,from,to)
- int rm;
- uword64 op;
- FP_formats from;
- FP_formats to;
+uword64
+convert (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ int rm,
+ uword64 op,
+ FP_formats from,
+ FP_formats to)
{
- uword64 result;
+ sim_fpu wop;
+ sim_fpu_round round;
+ unsigned32 result32;
+ unsigned64 result64;
#ifdef DEBUG
- printf("DBG: Convert: mode %s : op 0x%08X%08X : from %s : to %s : (PC = 0x%08X%08X)\n",RMMODE(rm),WORD64HI(op),WORD64LO(op),DOFMT(from),DOFMT(to),WORD64HI(IPC),WORD64LO(IPC));
+ printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm),pr_addr(op),DOFMT(from),DOFMT(to),pr_addr(IPC));
#endif /* DEBUG */
- /* The value "op" is converted to the destination format, rounding
- using mode "rm". When the destination is a fixed-point format,
- then a source value of Infinity, NaN or one which would round to
- an integer outside the fixed point range then an IEEE Invalid
- Operation condition is raised. */
- switch (to) {
- case fmt_single:
+ switch (rm)
{
- float tmp;
- switch (from) {
- case fmt_double:
- tmp = (float)(*(double *)&op);
- break;
-
- case fmt_word:
- tmp = (float)((int)(op & 0xFFFFFFFF));
- break;
-
- case fmt_long:
- tmp = (float)((int)op);
- break;
- }
-
- switch (rm) {
- case FP_RM_NEAREST:
- /* Round result to nearest representable value. When two
- representable values are equally near, round to the value
- that has a least significant bit of zero (i.e. is even). */
-#if defined(sun)
- tmp = (float)anint((double)tmp);
-#else
- /* TODO: Provide round-to-nearest */
-#endif
- break;
-
- case FP_RM_TOZERO:
- /* Round result to the value closest to, and not greater in
- magnitude than, the result. */
-#if defined(sun)
- tmp = (float)aint((double)tmp);
-#else
- /* TODO: Provide round-to-zero */
-#endif
- break;
-
- case FP_RM_TOPINF:
- /* Round result to the value closest to, and not less than,
- the result. */
- tmp = (float)ceil((double)tmp);
- break;
-
- case FP_RM_TOMINF:
- /* Round result to the value closest to, and not greater than,
- the result. */
- tmp = (float)floor((double)tmp);
- break;
- }
- result = (uword64)*(unsigned int *)&tmp;
+ case FP_RM_NEAREST:
+ /* Round result to nearest representable value. When two
+ representable values are equally near, round to the value
+ that has a least significant bit of zero (i.e. is even). */
+ round = sim_fpu_round_near;
+ break;
+ case FP_RM_TOZERO:
+ /* Round result to the value closest to, and not greater in
+ magnitude than, the result. */
+ round = sim_fpu_round_zero;
+ break;
+ case FP_RM_TOPINF:
+ /* Round result to the value closest to, and not less than,
+ the result. */
+ round = sim_fpu_round_up;
+ break;
+
+ case FP_RM_TOMINF:
+ /* Round result to the value closest to, and not greater than,
+ the result. */
+ round = sim_fpu_round_down;
+ break;
+ default:
+ round = 0;
+ fprintf (stderr, "Bad switch\n");
+ abort ();
}
- break;
-
- case fmt_double:
+
+ /* Convert the input to sim_fpu internal format */
+ switch (from)
{
- double tmp;
-
- switch (from) {
- case fmt_single:
- {
- unsigned int wop = (unsigned int)op;
- tmp = (double)(*(float *)&wop);
- }
- break;
-
- case fmt_word:
- tmp = (double)((word64)SIGNEXTEND((op & 0xFFFFFFFF),32));
- break;
-
- case fmt_long:
- tmp = (double)((word64)op);
- break;
- }
-
- switch (rm) {
- case FP_RM_NEAREST:
-#if defined(sun)
- tmp = anint(*(double *)&tmp);
-#else
- /* TODO: Provide round-to-nearest */
-#endif
- break;
-
- case FP_RM_TOZERO:
-#if defined(sun)
- tmp = aint(*(double *)&tmp);
-#else
- /* TODO: Provide round-to-zero */
-#endif
- break;
-
- case FP_RM_TOPINF:
- tmp = ceil(*(double *)&tmp);
- break;
-
- case FP_RM_TOMINF:
- tmp = floor(*(double *)&tmp);
- break;
- }
- result = *(uword64 *)&tmp;
+ case fmt_double:
+ sim_fpu_64to (&wop, op);
+ break;
+ case fmt_single:
+ sim_fpu_32to (&wop, op);
+ break;
+ case fmt_word:
+ sim_fpu_i32to (&wop, op, round);
+ break;
+ case fmt_long:
+ sim_fpu_i64to (&wop, op, round);
+ break;
+ default:
+ fprintf (stderr, "Bad switch\n");
+ abort ();
}
- break;
- case fmt_word:
- case fmt_long:
- if (Infinity(op,from) || NaN(op,from) || (1 == 0/*TODO: check range */)) {
- printf("DBG: TODO: update FCSR\n");
- SignalException(FPE);
- } else {
- if (to == fmt_word) {
- unsigned int tmp;
- switch (from) {
- case fmt_single:
- {
- unsigned int wop = (unsigned int)op;
- tmp = (unsigned int)*((float *)&wop);
- }
- break;
- case fmt_double:
- tmp = (unsigned int)*((double *)&op);
-#ifdef DEBUG
- printf("DBG: from double %.30f (0x%08X%08X) to word: 0x%08X\n",*((double *)&op),WORD64HI(op),WORD64LO(op),tmp);
-#endif /* DEBUG */
- break;
- }
- result = (uword64)tmp;
- } else { /* fmt_long */
- switch (from) {
- case fmt_single:
- {
- unsigned int wop = (unsigned int)op;
- result = (uword64)*((float *)&wop);
- }
- break;
- case fmt_double:
- result = (uword64)*((double *)&op);
- break;
- }
- }
+ /* Convert sim_fpu format into the output */
+ /* The value WOP is converted to the destination format, rounding
+ using mode RM. When the destination is a fixed-point format, then
+ a source value of Infinity, NaN or one which would round to an
+ integer outside the fixed point range then an IEEE Invalid
+ Operation condition is raised. */
+ switch (to)
+ {
+ case fmt_single:
+ sim_fpu_round_32 (&wop, round, 0);
+ sim_fpu_to32 (&result32, &wop);
+ result64 = result32;
+ break;
+ case fmt_double:
+ sim_fpu_round_64 (&wop, round, 0);
+ sim_fpu_to64 (&result64, &wop);
+ break;
+ case fmt_word:
+ sim_fpu_to32i (&result32, &wop, round);
+ result64 = result32;
+ break;
+ case fmt_long:
+ sim_fpu_to64i (&result64, &wop, round);
+ break;
+ default:
+ result64 = 0;
+ fprintf (stderr, "Bad switch\n");
+ abort ();
}
- break;
- }
-
+
#ifdef DEBUG
- printf("DBG: Convert: returning 0x%08X%08X (to format = %s)\n",WORD64HI(result),WORD64LO(result),DOFMT(to));
+ printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result64),DOFMT(to));
#endif /* DEBUG */
- return(result);
+ return(result64);
}
-#endif /* HASFPU */
+
/*-- co-processor support routines ------------------------------------------*/
-static int
+static int UNUSED
CoProcPresent(coproc_number)
unsigned int coproc_number;
{
return(0);
}
-static void
-COP_LW(coproc_num,coproc_reg,memword)
- int coproc_num, coproc_reg;
- unsigned int memword;
+void
+cop_lw (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ int coproc_num,
+ int coproc_reg,
+ unsigned int memword)
{
- switch (coproc_num) {
-#if defined(HASFPU)
+ switch (coproc_num)
+ {
case 1:
+ if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
+ {
#ifdef DEBUG
- printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%08X%08X\n",memword,WORD64HI(memword),WORD64LO(memword));
+ printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword,pr_addr(memword));
#endif
- StoreFPR(coproc_reg,fmt_uninterpreted,(uword64)memword);
- break;
-#endif /* HASFPU */
+ StoreFPR(coproc_reg,fmt_word,(uword64)memword);
+ FPR_STATE[coproc_reg] = fmt_uninterpreted;
+ break;
+ }
default:
- callback->printf_filtered(callback,"COP_LW(%d,%d,0x%08X) at IPC = 0x%08X%08X : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,WORD64HI(IPC),WORD64LO(IPC));
- break;
- }
+#if 0 /* this should be controlled by a configuration option */
+ sim_io_printf(sd,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,pr_addr(cia));
+#endif
+ break;
+ }
return;
}
-static void
-COP_LD(coproc_num,coproc_reg,memword)
- int coproc_num, coproc_reg;
- uword64 memword;
+void
+cop_ld (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ int coproc_num,
+ int coproc_reg,
+ uword64 memword)
{
switch (coproc_num) {
-#if defined(HASFPU)
case 1:
- StoreFPR(coproc_reg,fmt_uninterpreted,memword);
- break;
-#endif /* HASFPU */
+ if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
+ {
+ StoreFPR(coproc_reg,fmt_uninterpreted,memword);
+ break;
+ }
default:
- callback->printf_filtered(callback,"COP_LD(%d,%d,0x%08X%08X) at IPC = 0x%08X%08X : TODO (architecture specific)\n",coproc_num,coproc_reg,WORD64HI(memword),WORD64LO(memword),WORD64HI(IPC),WORD64LO(IPC));
+#if 0 /* this message should be controlled by a configuration option */
+ sim_io_printf(sd,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(memword),pr_addr(cia));
+#endif
break;
}
return;
}
-static unsigned int
-COP_SW(coproc_num,coproc_reg)
- int coproc_num, coproc_reg;
+
+/* start-sanitize-sky */
+#ifdef TARGET_SKY
+void
+cop_lq (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ int coproc_num,
+ int coproc_reg,
+ unsigned128 memword)
+{
+ switch (coproc_num)
+ {
+ case 2:
+ {
+ int i;
+
+ while(vu0_busy())
+ vu0_issue(sd);
+
+ /* one word at a time, argh! */
+ for(i=0; i<4; i++)
+ {
+ unsigned_4 value;
+ value = H2T_4(*A4_16(& memword, 3-i));
+ write_vu_vec_reg(&(vu0_device.regs), coproc_reg, i, & value);
+ }
+ }
+ break;
+
+ default:
+ sim_io_printf(sd,"COP_LQ(%d,%d,??) at PC = 0x%s : TODO (architecture specific)\n",
+ coproc_num,coproc_reg,pr_addr(cia));
+ break;
+ }
+
+ return;
+}
+#endif /* TARGET_SKY */
+/* end-sanitize-sky */
+
+
+unsigned int
+cop_sw (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ int coproc_num,
+ int coproc_reg)
{
unsigned int value = 0;
- switch (coproc_num) {
-#if defined(HASFPU)
+
+ switch (coproc_num)
+ {
case 1:
-#if 1
- value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted);
-#else
-#if 1
- value = (unsigned int)ValueFPR(coproc_reg,fpr_state[coproc_reg]);
-#else
-#ifdef DEBUG
- printf("DBG: COP_SW: reg in format %s (will be accessing as single)\n",DOFMT(fpr_state[coproc_reg]));
-#endif /* DEBUG */
- value = (unsigned int)ValueFPR(coproc_reg,fmt_single);
-#endif
-#endif
- break;
-#endif /* HASFPU */
+ if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
+ {
+ FP_formats hold;
+ hold = FPR_STATE[coproc_reg];
+ FPR_STATE[coproc_reg] = fmt_word;
+ value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted);
+ FPR_STATE[coproc_reg] = hold;
+ break;
+ }
default:
- callback->printf_filtered(callback,"COP_SW(%d,%d) at IPC = 0x%08X%08X : TODO (architecture specific)\n",coproc_num,coproc_reg,WORD64HI(IPC),WORD64LO(IPC));
- break;
- }
+#if 0 /* should be controlled by configuration option */
+ sim_io_printf(sd,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
+#endif
+ break;
+ }
return(value);
}
-static uword64
-COP_SD(coproc_num,coproc_reg)
- int coproc_num, coproc_reg;
+uword64
+cop_sd (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ int coproc_num,
+ int coproc_reg)
{
uword64 value = 0;
- switch (coproc_num) {
-#if defined(HASFPU)
+ switch (coproc_num)
+ {
case 1:
-#if 1
- value = ValueFPR(coproc_reg,fmt_uninterpreted);
-#else
-#if 1
- value = ValueFPR(coproc_reg,fpr_state[coproc_reg]);
-#else
-#ifdef DEBUG
- printf("DBG: COP_SD: reg in format %s (will be accessing as double)\n",DOFMT(fpr_state[coproc_reg]));
-#endif /* DEBUG */
- value = ValueFPR(coproc_reg,fmt_double);
-#endif
+ if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
+ {
+ value = ValueFPR(coproc_reg,fmt_uninterpreted);
+ break;
+ }
+
+ default:
+#if 0 /* should be controlled by configuration option */
+ sim_io_printf(sd,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
#endif
- break;
-#endif /* HASFPU */
+ break;
+ }
+
+ return(value);
+}
+
+/* start-sanitize-sky */
+#ifdef TARGET_SKY
+unsigned128
+cop_sq (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ int coproc_num,
+ int coproc_reg)
+{
+ unsigned128 value = U16_8(0, 0);
+ switch (coproc_num)
+ {
+ case 2:
+ {
+ unsigned_16 xyzw;
+ int i;
+
+ while(vu0_busy())
+ vu0_issue(sd);
+
+ /* one word at a time, argh! */
+ for(i=0; i<4; i++)
+ {
+ unsigned_4 value;
+ read_vu_vec_reg(&(vu0_device.regs), coproc_reg, i, & value);
+ *A4_16(& xyzw, 3-i) = T2H_4(value);
+ }
+ return xyzw;
+ }
+ break;
+
default:
- callback->printf_filtered(callback,"COP_SD(%d,%d) at IPC = 0x%08X%08X : TODO (architecture specific)\n",coproc_num,coproc_reg,WORD64HI(IPC),WORD64LO(IPC));
- break;
- }
+ sim_io_printf(sd,"COP_SQ(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",
+ coproc_num,coproc_reg,pr_addr(cia));
+ break;
+ }
return(value);
}
+#endif /* TARGET_SKY */
+/* end-sanitize-sky */
-static void
-decode_coproc(instruction)
- unsigned int instruction;
+
+void
+decode_coproc (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ unsigned int instruction)
{
int coprocnum = ((instruction >> 26) & 3);
- switch (coprocnum) {
+ switch (coprocnum)
+ {
case 0: /* standard CPU control and cache registers */
{
- /* NOTEs:
- Standard CP0 registers
- 0 = Index R4000 VR4100 VR4300
- 1 = Random R4000 VR4100 VR4300
- 2 = EntryLo0 R4000 VR4100 VR4300
- 3 = EntryLo1 R4000 VR4100 VR4300
- 4 = Context R4000 VR4100 VR4300
- 5 = PageMask R4000 VR4100 VR4300
- 6 = Wired R4000 VR4100 VR4300
- 8 = BadVAddr R4000 VR4100 VR4300
- 9 = Count R4000 VR4100 VR4300
- 10 = EntryHi R4000 VR4100 VR4300
- 11 = Compare R4000 VR4100 VR4300
- 12 = SR R4000 VR4100 VR4300
- 13 = Cause R4000 VR4100 VR4300
- 14 = EPC R4000 VR4100 VR4300
- 15 = PRId R4000 VR4100 VR4300
- 16 = Config R4000 VR4100 VR4300
- 17 = LLAddr R4000 VR4100 VR4300
- 18 = WatchLo R4000 VR4100 VR4300
- 19 = WatchHi R4000 VR4100 VR4300
- 20 = XContext R4000 VR4100 VR4300
- 26 = PErr or ECC R4000 VR4100 VR4300
- 27 = CacheErr R4000 VR4100
- 28 = TagLo R4000 VR4100 VR4300
- 29 = TagHi R4000 VR4100 VR4300
- 30 = ErrorEPC R4000 VR4100 VR4300
- */
int code = ((instruction >> 21) & 0x1F);
/* R4000 Users Manual (second edition) lists the following CP0
instructions:
- DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
- DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
- MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
- MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
- TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
- TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
- TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
- TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
- CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
- ERET Exception return (VR4100 = 01000010000000000000000000011000)
- */
- if (((code == 0x00) || (code == 0x04)) && ((instruction & 0x7FF) == 0)) {
- int rt = ((instruction >> 16) & 0x1F);
- int rd = ((instruction >> 11) & 0x1F);
- if (code == 0x00) { /* MF : move from */
- callback->printf_filtered(callback,"Warning: MFC0 %d,%d not handled yet (architecture specific)\n",rt,rd);
- GPR[rt] = 0xDEADC0DE; /* CPR[0,rd] */
- } else { /* MT : move to */
- /* CPR[0,rd] = GPR[rt]; */
- callback->printf_filtered(callback,"Warning: MTC0 %d,%d not handled yet (architecture specific)\n",rt,rd);
+ DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
+ DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
+ MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
+ MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
+ TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
+ TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
+ TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
+ TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
+ CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
+ ERET Exception return (VR4100 = 01000010000000000000000000011000)
+ */
+ if (((code == 0x00) || (code == 0x04)) && ((instruction & 0x7FF) == 0))
+ {
+ int rt = ((instruction >> 16) & 0x1F);
+ int rd = ((instruction >> 11) & 0x1F);
+
+ switch (rd) /* NOTEs: Standard CP0 registers */
+ {
+ /* 0 = Index R4000 VR4100 VR4300 */
+ /* 1 = Random R4000 VR4100 VR4300 */
+ /* 2 = EntryLo0 R4000 VR4100 VR4300 */
+ /* 3 = EntryLo1 R4000 VR4100 VR4300 */
+ /* 4 = Context R4000 VR4100 VR4300 */
+ /* 5 = PageMask R4000 VR4100 VR4300 */
+ /* 6 = Wired R4000 VR4100 VR4300 */
+ /* 8 = BadVAddr R4000 VR4100 VR4300 */
+ /* 9 = Count R4000 VR4100 VR4300 */
+ /* 10 = EntryHi R4000 VR4100 VR4300 */
+ /* 11 = Compare R4000 VR4100 VR4300 */
+ /* 12 = SR R4000 VR4100 VR4300 */
+ case 12:
+ if (code == 0x00)
+ GPR[rt] = SR;
+ else
+ SR = GPR[rt];
+ break;
+ /* 13 = Cause R4000 VR4100 VR4300 */
+ case 13:
+ if (code == 0x00)
+ GPR[rt] = CAUSE;
+ else
+ CAUSE = GPR[rt];
+ break;
+ /* 14 = EPC R4000 VR4100 VR4300 */
+ case 14:
+ if (code == 0x00)
+ GPR[rt] = (signed_word) (signed_address) EPC;
+ else
+ EPC = GPR[rt];
+ break;
+ /* 15 = PRId R4000 VR4100 VR4300 */
+#ifdef SUBTARGET_R3900
+ /* 16 = Debug */
+ case 16:
+ if (code == 0x00)
+ GPR[rt] = Debug;
+ else
+ Debug = GPR[rt];
+ break;
+#else
+ /* 16 = Config R4000 VR4100 VR4300 */
+ case 16:
+ if (code == 0x00)
+ GPR[rt] = C0_CONFIG;
+ else
+ C0_CONFIG = GPR[rt];
+ break;
+#endif
+#ifdef SUBTARGET_R3900
+ /* 17 = Debug */
+ case 17:
+ if (code == 0x00)
+ GPR[rt] = DEPC;
+ else
+ DEPC = GPR[rt];
+ break;
+#else
+ /* 17 = LLAddr R4000 VR4100 VR4300 */
+#endif
+ /* 18 = WatchLo R4000 VR4100 VR4300 */
+ /* 19 = WatchHi R4000 VR4100 VR4300 */
+ /* 20 = XContext R4000 VR4100 VR4300 */
+ /* 26 = PErr or ECC R4000 VR4100 VR4300 */
+ /* 27 = CacheErr R4000 VR4100 */
+ /* 28 = TagLo R4000 VR4100 VR4300 */
+ /* 29 = TagHi R4000 VR4100 VR4300 */
+ /* 30 = ErrorEPC R4000 VR4100 VR4300 */
+ GPR[rt] = 0xDEADC0DE; /* CPR[0,rd] */
+ /* CPR[0,rd] = GPR[rt]; */
+ default:
+ if (code == 0x00)
+ sim_io_printf(sd,"Warning: MFC0 %d,%d ignored (architecture specific)\n",rt,rd);
+ else
+ sim_io_printf(sd,"Warning: MTC0 %d,%d ignored (architecture specific)\n",rt,rd);
+ }
+ }
+ else if (code == 0x10 && (instruction & 0x3f) == 0x18)
+ {
+ /* ERET */
+ if (SR & status_ERL)
+ {
+ /* Oops, not yet available */
+ sim_io_printf(sd,"Warning: ERET when SR[ERL] set not handled yet");
+ PC = EPC;
+ SR &= ~status_ERL;
+ }
+ else
+ {
+ PC = EPC;
+ SR &= ~status_EXL;
+ }
+ }
+ else if (code == 0x10 && (instruction & 0x3f) == 0x10)
+ {
+ /* RFE */
+ }
+ else if (code == 0x10 && (instruction & 0x3f) == 0x1F)
+ {
+ /* DERET */
+ Debug &= ~Debug_DM;
+ DELAYSLOT();
+ DSPC = DEPC;
}
- } else
- callback->printf_filtered(callback,"Warning: Unrecognised COP0 instruction 0x%08X at IPC = 0x%08X%08X : No handler present\n",instruction,WORD64HI(IPC),WORD64LO(IPC));
+ else
+ sim_io_eprintf(sd,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction,pr_addr(cia));
/* TODO: When executing an ERET or RFE instruction we should
clear LLBIT, to ensure that any out-standing atomic
read/modify/write sequence fails. */
}
- break;
-
- case 2: /* undefined co-processor */
- callback->printf_filtered(callback,"Warning: COP2 instruction 0x%08X at IPC = 0x%08X%08X : No handler present\n",instruction,WORD64HI(IPC),WORD64LO(IPC));
- break;
-
+ break;
+
+ case 2: /* co-processor 2 */
+ {
+ int handle = 0;
+
+ /* start-sanitize-sky */
+#ifdef TARGET_SKY
+ /* On the R5900, this refers to a "VU" vector co-processor. */
+
+ int i_25_21 = (instruction >> 21) & 0x1f;
+ int i_20_16 = (instruction >> 16) & 0x1f;
+ int i_20_6 = (instruction >> 6) & 0x7fff;
+ int i_15_11 = (instruction >> 11) & 0x1f;
+ int i_15_0 = instruction & 0xffff;
+ int i_10_1 = (instruction >> 1) & 0x3ff;
+ int i_10_0 = instruction & 0x7ff;
+ int i_10_6 = (instruction >> 6) & 0x1f;
+ int i_5_0 = instruction & 0x03f;
+ int interlock = instruction & 0x01;
+ /* setup for semantic.c-like actions below */
+ typedef unsigned_4 instruction_word;
+ int CIA = cia;
+ int NIA = cia + 4;
+
+ handle = 1;
+
+ /* test COP2 usability */
+ if(! (SR & status_CU2))
+ {
+ SignalException(CoProcessorUnusable,instruction);
+ /* NOTREACHED */
+ }
+
+#define MY_INDEX itable_COPz_NORMAL
+#define MY_PREFIX COPz_NORMAL
+#define MY_NAME "COPz_NORMAL"
+
+ /* classify & execute basic COP2 instructions */
+ if(i_25_21 == 0x08 && i_20_16 == 0x00) /* BC2F */
+ {
+ address_word offset = EXTEND16(i_15_0) << 2;
+ if(! vu0_busy()) DELAY_SLOT(cia + 4 + offset);
+ }
+ else if(i_25_21 == 0x08 && i_20_16==0x02) /* BC2FL */
+ {
+ address_word offset = EXTEND16(i_15_0) << 2;
+ if(! vu0_busy()) DELAY_SLOT(cia + 4 + offset);
+ else NULLIFY_NEXT_INSTRUCTION();
+ }
+ else if(i_25_21 == 0x08 && i_20_16 == 0x01) /* BC2T */
+ {
+ address_word offset = EXTEND16(i_15_0) << 2;
+ if(vu0_busy()) DELAY_SLOT(cia + 4 + offset);
+ }
+ else if(i_25_21 == 0x08 && i_20_16 == 0x03) /* BC2TL */
+ {
+ address_word offset = EXTEND16(i_15_0) << 2;
+ if(vu0_busy()) DELAY_SLOT(cia + 4 + offset);
+ else NULLIFY_NEXT_INSTRUCTION();
+ }
+ else if((i_25_21 == 0x02 && i_10_1 == 0x000) || /* CFC2 */
+ (i_25_21 == 0x01)) /* QMFC2 */
+ {
+ int rt = i_20_16;
+ int id = i_15_11;
+
+ /* interlock checking */
+ /* POLICY: never busy in macro mode */
+ while(vu0_busy() && interlock)
+ vu0_issue(sd);
+
+ /* perform VU register address */
+ if(i_25_21 == 0x01) /* QMFC2 */
+ {
+ unsigned_16 xyzw;
+ /* one word at a time, argh! */
+ read_vu_vec_reg(&(vu0_device.regs), id, 0, A4_16(& xyzw, 3));
+ read_vu_vec_reg(&(vu0_device.regs), id, 1, A4_16(& xyzw, 2));
+ read_vu_vec_reg(&(vu0_device.regs), id, 2, A4_16(& xyzw, 1));
+ read_vu_vec_reg(&(vu0_device.regs), id, 3, A4_16(& xyzw, 0));
+ GPR[rt] = T2H_8(* A8_16(& xyzw, 1));
+ GPR1[rt] = T2H_8(* A8_16(& xyzw, 0));
+ }
+ else /* CFC2 */
+ {
+ unsigned_4 data;
+ /* enum + int calculation, argh! */
+ id = VU_REG_MST + 16 * id;
+ read_vu_misc_reg(&(vu0_device.regs), id, & data);
+ GPR[rt] = EXTEND32(T2H_4(data));
+ }
+ }
+ else if((i_25_21 == 0x06 && i_10_1 == 0x000) || /* CTC2 */
+ (i_25_21 == 0x05)) /* QMTC2 */
+ {
+ int rt = i_20_16;
+ int id = i_15_11;
+
+ /* interlock checking: wait until M or E bits set */
+ /* POLICY: never busy in macro mode */
+ while(vu0_busy() && interlock)
+ {
+ if(vu0_micro_interlock_released())
+ {
+ vu0_micro_interlock_clear();
+ break;
+ }
+
+ vu0_issue(sd);
+ }
+
+ /* perform VU register address */
+ if(i_25_21 == 0x05) /* QMTC2 */
+ {
+ unsigned_16 xyzw = U16_8(GPR1[rt], GPR[rt]);
+
+ xyzw = H2T_16(xyzw);
+ /* one word at a time, argh! */
+ write_vu_vec_reg(&(vu0_device.regs), id, 0, A4_16(& xyzw, 3));
+ write_vu_vec_reg(&(vu0_device.regs), id, 1, A4_16(& xyzw, 2));
+ write_vu_vec_reg(&(vu0_device.regs), id, 2, A4_16(& xyzw, 1));
+ write_vu_vec_reg(&(vu0_device.regs), id, 3, A4_16(& xyzw, 0));
+ }
+ else /* CTC2 */
+ {
+ unsigned_4 data = H2T_4(GPR[rt]);
+ /* enum + int calculation, argh! */
+ id = VU_REG_MST + 16 * id;
+ write_vu_misc_reg(&(vu0_device.regs), id, & data);
+ }
+ }
+ else if(i_10_0 == 0x3bf) /* VWAITQ */
+ {
+ while(vu0_q_busy())
+ vu0_issue(sd);
+ }
+ else if(i_5_0 == 0x38) /* VCALLMS */
+ {
+ unsigned_4 data = H2T_2(i_20_6);
+
+ while(vu0_busy())
+ vu0_issue(sd);
+
+ /* write to reserved CIA register to get VU0 moving */
+ write_vu_special_reg(& vu0_device, VU_REG_CIA, & data);
+
+ ASSERT(vu0_busy());
+ }
+ else if(i_5_0 == 0x39) /* VCALLMSR */
+ {
+ unsigned_4 data;
+
+ while(vu0_busy())
+ vu0_issue(sd);
+
+ read_vu_special_reg(& vu0_device, VU_REG_CMSAR0, & data);
+ /* write to reserved CIA register to get VU0 moving */
+ write_vu_special_reg(& vu0_device, VU_REG_CIA, & data);
+
+ ASSERT(vu0_busy());
+ }
+ /* handle all remaining UPPER VU instructions in one block */
+ else if((i_5_0 < 0x30) || /* VADDx .. VMINI */
+ (i_5_0 >= 0x3c && i_10_6 < 0x0c)) /* VADDAx .. VNOP */
+ {
+ unsigned_4 vu_upper, vu_lower;
+ vu_upper =
+ 0x00000000 | /* bits 31 .. 25 */
+ (instruction & 0x01ffffff); /* bits 24 .. 0 */
+ vu_lower = 0x8000033c; /* NOP */
+
+ /* POLICY: never busy in macro mode */
+ while(vu0_busy())
+ vu0_issue(sd);
+
+ vu0_macro_issue(vu_upper, vu_lower);
+
+ /* POLICY: wait for completion of macro-instruction */
+ while(vu0_busy())
+ vu0_issue(sd);
+ }
+ /* handle all remaining LOWER VU instructions in one block */
+ else if((i_5_0 >= 0x30 && i_5_0 <= 0x35) || /* VIADD .. VIOR */
+ (i_5_0 >= 0x3c && i_10_6 >= 0x0c)) /* VMOVE .. VRXOR */
+ { /* N.B.: VWAITQ already covered by prior case */
+ unsigned_4 vu_upper, vu_lower;
+ vu_upper = 0x000002ff; /* NOP/NOP */
+ vu_lower =
+ 0x80000000 | /* bits 31 .. 25 */
+ (instruction & 0x01ffffff); /* bits 24 .. 0 */
+
+ /* POLICY: never busy in macro mode */
+ while(vu0_busy())
+ vu0_issue(sd);
+
+ vu0_macro_issue(vu_upper, vu_lower);
+
+ /* POLICY: wait for completion of macro-instruction */
+ while(vu0_busy())
+ vu0_issue(sd);
+ }
+ /* ... no other COP2 instructions ... */
+ else
+ {
+ SignalException(ReservedInstruction, instruction);
+ /* NOTREACHED */
+ }
+
+ /* cleanup for semantic.c-like actions above */
+ PC = NIA;
+
+#undef MY_INDEX
+#undef MY_PREFIX
+#undef MY_NAME
+
+#endif /* TARGET_SKY */
+ /* end-sanitize-sky */
+
+ if(! handle)
+ {
+ sim_io_eprintf(sd, "COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",
+ instruction,pr_addr(cia));
+ }
+ }
+ break;
+
case 1: /* should not occur (FPU co-processor) */
case 3: /* should not occur (FPU co-processor) */
SignalException(ReservedInstruction,instruction);
break;
- }
-
+ }
+
return;
}
+
/*-- instruction simulation -------------------------------------------------*/
-static void
-simulate ()
+/* When the IGEN simulator is being built, the function below is be
+ replaced by a generated version. However, WITH_IGEN == 2 indicates
+ that the fubction below should be compiled but under a different
+ name (to allow backward compatibility) */
+
+#if (WITH_IGEN != 1)
+#if (WITH_IGEN > 1)
+void old_engine_run PARAMS ((SIM_DESC sd, int next_cpu_nr, int siggnal));
+void
+old_engine_run (sd, next_cpu_nr, nr_cpus, siggnal)
+#else
+void
+sim_engine_run (sd, next_cpu_nr, nr_cpus, siggnal)
+#endif
+ SIM_DESC sd;
+ int next_cpu_nr; /* ignore */
+ int nr_cpus; /* ignore */
+ int siggnal; /* ignore */
{
+ sim_cpu *cpu = STATE_CPU (sd, 0); /* hardwire to cpu 0 */
+#if !defined(FASTSIM)
unsigned int pipeline_count = 1;
+#endif
#ifdef DEBUG
- if (membank == NULL) {
+ if (STATE_MEMORY (sd) == NULL) {
printf("DBG: simulate() entered with no memory\n");
exit(1);
}
#endif
/* main controlling loop */
- do {
- /* Fetch the next instruction from the simulator memory: */
- uword64 vaddr = (uword64)PC;
- uword64 paddr;
+ while (1) {
+ /* vaddr is slowly being replaced with cia - current instruction
+ address */
+ address_word cia = (uword64)PC;
+ address_word vaddr = cia;
+ address_word paddr;
int cca;
- unsigned int instruction;
- int dsstate = (state & simDELAYSLOT);
+ unsigned int instruction; /* uword64? what's this used for? FIXME! */
#ifdef DEBUG
{
printf("DBG: state = 0x%08X :",state);
- if (state & simSTOP) printf(" simSTOP");
- if (state & simSTEP) printf(" simSTEP");
if (state & simHALTEX) printf(" simHALTEX");
if (state & simHALTIN) printf(" simHALTIN");
- if (state & simBE) printf(" simBE");
+ printf("\n");
}
#endif /* DEBUG */
+ DSSTATE = (STATE & simDELAYSLOT);
#ifdef DEBUG
if (dsstate)
- callback->printf_filtered(callback,"DBG: DSPC = 0x%08X%08X\n",WORD64HI(DSPC),WORD64LO(DSPC));
+ sim_io_printf(sd,"DBG: DSPC = 0x%s\n",pr_addr(DSPC));
#endif /* DEBUG */
- if (AddressTranslation(PC,isINSTRUCTION,isLOAD,&paddr,&cca,isTARGET,isREAL)) { /* Copy the action of the LW instruction */
- unsigned int reverse = (ReverseEndian ? 1 : 0);
- unsigned int bigend = (BigEndianCPU ? 1 : 0);
- uword64 value;
- unsigned int byte;
- paddr = ((paddr & ~0x7) | ((paddr & 0x7) ^ (reverse << 2)));
- value = LoadMemory(cca,AccessLength_WORD,paddr,vaddr,isINSTRUCTION,isREAL);
- byte = ((vaddr & 0x7) ^ (bigend << 2));
- instruction = ((value >> (8 * byte)) & 0xFFFFFFFF);
+ /* Fetch the next instruction from the simulator memory: */
+ if (AddressTranslation(cia,isINSTRUCTION,isLOAD,&paddr,&cca,isTARGET,isREAL)) {
+ if ((vaddr & 1) == 0) {
+ /* Copy the action of the LW instruction */
+ unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0);
+ unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0);
+ uword64 value;
+ unsigned int byte;
+ paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2)));
+ LoadMemory(&value,NULL,cca,AccessLength_WORD,paddr,vaddr,isINSTRUCTION,isREAL);
+ byte = ((vaddr & LOADDRMASK) ^ (bigend << 2));
+ instruction = ((value >> (8 * byte)) & 0xFFFFFFFF);
+ } else {
+ /* Copy the action of the LH instruction */
+ unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 1) : 0);
+ unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 1) : 0);
+ uword64 value;
+ unsigned int byte;
+ paddr = (((paddr & ~ (uword64) 1) & ~LOADDRMASK)
+ | (((paddr & ~ (uword64) 1) & LOADDRMASK) ^ (reverse << 1)));
+ LoadMemory(&value,NULL,cca, AccessLength_HALFWORD,
+ paddr & ~ (uword64) 1,
+ vaddr, isINSTRUCTION, isREAL);
+ byte = (((vaddr &~ (uword64) 1) & LOADDRMASK) ^ (bigend << 1));
+ instruction = ((value >> (8 * byte)) & 0xFFFF);
+ }
} else {
- fprintf(stderr,"Cannot translate address for PC = 0x%08X%08X failed\n",WORD64HI(PC),WORD64LO(PC));
+ fprintf(stderr,"Cannot translate address for PC = 0x%s failed\n",pr_addr(PC));
exit(1);
}
#ifdef DEBUG
- callback->printf_filtered(callback,"DBG: fetched 0x%08X from PC = 0x%08X%08X\n",instruction,WORD64HI(PC),WORD64LO(PC));
+ sim_io_printf(sd,"DBG: fetched 0x%08X from PC = 0x%s\n",instruction,pr_addr(PC));
#endif /* DEBUG */
-/*DBG*/ if (instruction == 0x46200005) /* ABS.D */
-/*DBG*/ callback->printf_filtered(callback,"DBG: ABS.D (0x%08X) instruction\n",instruction);
-
-#if !defined(FASTSIM) || defined(PROFILE)
- instruction_fetches++;
- /* Since we increment above, the value should only ever be zero if
- we have just overflowed: */
- if (instruction_fetches == 0)
- instruction_fetch_overflow++;
-#if defined(PROFILE)
- if ((state & simPROFILE) && ((instruction_fetches % profile_frequency) == 0) && profile_hist) {
- int n = ((unsigned int)(PC - profile_minpc) >> (profile_shift + 2));
- if (n < profile_nsamples) {
- /* NOTE: The counts for the profiling bins are only 16bits wide */
- if (profile_hist[n] != USHRT_MAX)
- (profile_hist[n])++;
- }
- }
-#endif /* PROFILE */
-#endif /* !FASTSIM && PROFILE */
-
- IPC = PC; /* copy PC for this instruction */
/* This is required by exception processing, to ensure that we can
cope with exceptions in the delay slots of branches that may
already have changed the PC. */
- PC += 4; /* increment ready for the next fetch */
+ if ((vaddr & 1) == 0)
+ PC += 4; /* increment ready for the next fetch */
+ else
+ PC += 2;
/* NOTE: If we perform a delay slot change to the PC, this
increment is not requuired. However, it would make the
simulator more complicated to try and avoid this small hit. */
treated as using a single cycle. NOTE: A standard system is not
provided by the default simulator because different MIPS
architectures have different cycle counts for the same
- instructions. */
+ instructions.
-#if defined(HASFPU)
- /* Set previous flag, depending on current: */
- if (state & simPCOC0)
- state |= simPCOC1;
- else
- state &= ~simPCOC1;
- /* and update the current value: */
- if (GETFCC(0))
- state |= simPCOC0;
- else
- state &= ~simPCOC0;
-#endif /* HASFPU */
+ [NOTE: pipeline_count has been replaced the event queue] */
+
+ /* shuffle the floating point status pipeline state */
+ ENGINE_ISSUE_PREFIX_HOOK();
/* NOTE: For multi-context simulation environments the "instruction"
variable should be local to this routine. */
variables (and a single-threaded simulator engine), then we can
create the actual variables with these names. */
- if (!(state & simSKIPNEXT)) {
+ if (!(STATE & simSKIPNEXT)) {
/* Include the simulator engine */
-#include "engine.c"
-#if ((GPRLEN == 64) && !defined(PROCESSOR_64BIT)) || ((GPRLEN == 32) && defined(PROCESSOR_64BIT))
+#include "oengine.c"
+#if ((GPRLEN == 64) && !PROCESSOR_64BIT) || ((GPRLEN == 32) && PROCESSOR_64BIT)
#error "Mismatch between run-time simulator code and simulation engine"
+#endif
+#if (WITH_TARGET_WORD_BITSIZE != GPRLEN)
+#error "Mismatch between configure WITH_TARGET_WORD_BITSIZE and gencode GPRLEN"
+#endif
+#if ((WITH_FLOATING_POINT == HARD_FLOATING_POINT) != defined (HASFPU))
+#error "Mismatch between configure WITH_FLOATING_POINT and gencode HASFPU"
#endif
-#if defined(WARN_LOHI)
- /* Decrement the HI/LO validity ticks */
- if (HIACCESS > 0)
- HIACCESS--;
- if (LOACCESS > 0)
- LOACCESS--;
-#endif /* WARN_LOHI */
-
-#if defined(WARN_ZERO)
/* For certain MIPS architectures, GPR[0] is hardwired to zero. We
should check for it being changed. It is better doing it here,
than within the simulator, since it will help keep the simulator
small. */
if (ZERO != 0) {
- callback->printf_filtered(callback,"SIM Warning: The ZERO register has been updated with 0x%08X%08X (PC = 0x%08X%08X)\nSIM Warning: Resetting back to zero\n",WORD64HI(ZERO),WORD64LO(ZERO),WORD64HI(IPC),WORD64LO(IPC));
+#if defined(WARN_ZERO)
+ sim_io_eprintf(sd,"The ZERO register has been updated with 0x%s (PC = 0x%s) (reset back to zero)\n",pr_addr(ZERO),pr_addr(cia));
+#endif /* WARN_ZERO */
ZERO = 0; /* reset back to zero before next instruction */
}
-#endif /* WARN_ZERO */
} else /* simSKIPNEXT check */
- state &= ~simSKIPNEXT;
+ STATE &= ~simSKIPNEXT;
/* If the delay slot was active before the instruction is
executed, then update the PC to its new value: */
- if (dsstate) {
+ if (DSSTATE) {
#ifdef DEBUG
- printf("DBG: dsstate set before instruction execution - updating PC to 0x%08X%08X\n",WORD64HI(DSPC),WORD64LO(DSPC));
+ printf("DBG: dsstate set before instruction execution - updating PC to 0x%s\n",pr_addr(DSPC));
#endif /* DEBUG */
PC = DSPC;
- state &= ~simDELAYSLOT;
+ CANCELDELAYSLOT();
}
- if (MIPSISA < 4) { /* The following is only required on pre MIPS IV processors: */
- /* Deal with pending register updates: */
-#ifdef DEBUG
- printf("DBG: EMPTY BEFORE pending_in = %d, pending_out = %d, pending_total = %d\n",pending_in,pending_out,pending_total);
-#endif /* DEBUG */
- if (pending_out != pending_in) {
- int loop;
- int index = pending_out;
- int total = pending_total;
- if (pending_total == 0) {
- fprintf(stderr,"FATAL: Mis-match on pending update pointers\n");
- exit(1);
- }
- for (loop = 0; (loop < total); loop++) {
-#ifdef DEBUG
- printf("DBG: BEFORE index = %d, loop = %d\n",index,loop);
-#endif /* DEBUG */
- if (pending_slot_reg[index] != (LAST_EMBED_REGNUM + 1)) {
-#ifdef DEBUG
- printf("pending_slot_count[%d] = %d\n",index,pending_slot_count[index]);
-#endif /* DEBUG */
- if (--(pending_slot_count[index]) == 0) {
-#ifdef DEBUG
- printf("pending_slot_reg[%d] = %d\n",index,pending_slot_reg[index]);
- printf("pending_slot_value[%d] = 0x%08X%08X\n",index,WORD64HI(pending_slot_value[index]),WORD64LO(pending_slot_value[index]));
-#endif /* DEBUG */
- if (pending_slot_reg[index] == COCIDX) {
- SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
- } else {
- registers[pending_slot_reg[index]] = pending_slot_value[index];
-#if defined(HASFPU)
- /* The only time we have PENDING updates to FPU
- registers, is when performing binary transfers. This
- means we should update the register type field. */
- if ((pending_slot_reg[index] >= FGRIDX) && (pending_slot_reg[index] < (FGRIDX + 32)))
- fpr_state[pending_slot_reg[index]] = fmt_uninterpreted;
-#endif /* HASFPU */
- }
-#ifdef DEBUG
- printf("registers[%d] = 0x%08X%08X\n",pending_slot_reg[index],WORD64HI(registers[pending_slot_reg[index]]),WORD64LO(registers[pending_slot_reg[index]]));
-#endif /* DEBUG */
- pending_slot_reg[index] = (LAST_EMBED_REGNUM + 1);
- pending_out++;
- if (pending_out == PSLOTS)
- pending_out = 0;
- pending_total--;
- }
- }
-#ifdef DEBUG
- printf("DBG: AFTER index = %d, loop = %d\n",index,loop);
-#endif /* DEBUG */
- index++;
- if (index == PSLOTS)
- index = 0;
- }
- }
-#ifdef DEBUG
- printf("DBG: EMPTY AFTER pending_in = %d, pending_out = %d, pending_total = %d\n",pending_in,pending_out,pending_total);
-#endif /* DEBUG */
- }
+ if (MIPSISA < 4)
+ PENDING_TICK();
#if !defined(FASTSIM)
- pipeline_ticks += pipeline_count;
+ if (sim_events_tickn (sd, pipeline_count))
+ {
+ /* cpu->cia = cia; */
+ sim_events_process (sd);
+ }
+#else
+ if (sim_events_tick (sd))
+ {
+ /* cpu->cia = cia; */
+ sim_events_process (sd);
+ }
#endif /* FASTSIM */
+ }
+}
+#endif
- if (state & simSTEP)
- state |= simSTOP;
- } while (!(state & simSTOP));
-#ifdef DEBUG
- if (membank == NULL) {
- printf("DBG: simulate() LEAVING with no memory\n");
- exit(1);
- }
-#endif /* DEBUG */
+/* This code copied from gdb's utils.c. Would like to share this code,
+ but don't know of a common place where both could get to it. */
- return;
+/* Temporary storage using circular buffer */
+#define NUMCELLS 16
+#define CELLSIZE 32
+static char*
+get_cell()
+{
+ static char buf[NUMCELLS][CELLSIZE];
+ static int cell=0;
+ if (++cell>=NUMCELLS) cell=0;
+ return buf[cell];
+}
+
+/* Print routines to handle variable size regs, etc */
+
+/* Eliminate warning from compiler on 32-bit systems */
+static int thirty_two = 32;
+
+char*
+pr_addr(addr)
+ SIM_ADDR addr;
+{
+ char *paddr_str=get_cell();
+ switch (sizeof(addr))
+ {
+ case 8:
+ sprintf(paddr_str,"%08lx%08lx",
+ (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
+ break;
+ case 4:
+ sprintf(paddr_str,"%08lx",(unsigned long)addr);
+ break;
+ case 2:
+ sprintf(paddr_str,"%04x",(unsigned short)(addr&0xffff));
+ break;
+ default:
+ sprintf(paddr_str,"%x",addr);
+ }
+ return paddr_str;
+}
+
+char*
+pr_uword64(addr)
+ uword64 addr;
+{
+ char *paddr_str=get_cell();
+ sprintf(paddr_str,"%08lx%08lx",
+ (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
+ return paddr_str;
}
+
+
/*---------------------------------------------------------------------------*/
/*> EOF interp.c <*/
projects / deliverable / binutils-gdb.git / blobdiff