:model:::mipsIV:mips8000:
:model:::mipsV:mipsisaV:
:model:::mips32:mipsisa32:
+:model:::mips32r2:mipsisa32r2:
:model:::mips64:mipsisa64:
+:model:::mips64r2:mipsisa64r2:
// Vendor ISAs:
//
// (or which pre-date or use different encodings than the standard
// instructions) are (for the most part) in separate .igen files.
:model:::vr4100:mips4100: // vr.igen
+:model:::vr4120:mips4120:
:model:::vr5000:mips5000:
+:model:::vr5400:mips5400:
+:model:::vr5500:mips5500:
:model:::r3900:mips3900: // tx.igen
// MIPS Application Specific Extensions (ASEs)
// Instructions for the ASEs are in separate .igen files.
// ASEs add instructions on to a base ISA.
:model:::mips16:mips16: // m16.igen (and m16.dc)
+:model:::mips16e:mips16e: // m16e.igen
+:model:::mips3d:mips3d: // mips3d.igen
:model:::mdmx:mdmx: // mdmx.igen
+:model:::dsp:dsp: // dsp.igen
+:model:::dsp2:dsp2: // dsp2.igen
+:model:::smartmips:smartmips: // smartmips.igen
+:model:::micromips32:micromips64: // micromips.igen
+:model:::micromips64:micromips64: // micromips.igen
+:model:::micromipsdsp:micromipsdsp: // micromipsdsp.igen
// Vendor Extensions
//
// Pseudo instructions known by interp.c
// For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
-000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
+000000,5.*,5.*,5.*,5.OP,111001:SPECIAL:32::RSVD
"rsvd <OP>"
{
SignalException (ReservedInstruction, instruction_0);
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*vr4100:
*vr5000:
*r3900:
+*micromips32:
{
return base + offset;
}
:function:::address_word:loadstore_ea:address_word base, address_word offset
*mips64:
+*mips64r2:
+*micromips64:
{
#if 0 /* XXX FIXME: enable this only after some additional testing. */
/* If in user mode and UX is not set, use 32-bit compatibility effective
*vr4100:
*vr5000:
*r3900:
-{
- /* For historical simulator compatibility (until documentation is
- found that makes these operations unpredictable on some of these
- architectures), this check never returns true. */
- return 0;
-}
-
-:function:::int:not_word_value:unsigned_word value
*mips32:
-{
- /* On MIPS32, since registers are 32-bits, there's no check to be done. */
- return 0;
-}
-
-:function:::int:not_word_value:unsigned_word value
+*mips32r2:
*mips64:
+*mips64r2:
+*micromips32:
+*micromips64:
{
- return ((value >> 32) != (value & 0x80000000 ? 0xFFFFFFFF : 0));
+#if WITH_TARGET_WORD_BITSIZE == 64
+ return value != (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
+#else
+ return 0;
+#endif
}
-
// Helper:
//
// Handle UNPREDICTABLE operation behaviour. The goal here is to prevent
:function:::void:unpredictable:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
+*micromips32:
+*micromips64:
{
unpredictable_action (CPU, CIA);
}
-// Helper:
+// Helpers:
//
// Check that an access to a HI/LO register meets timing requirements
//
-// The following requirements exist:
+// In all MIPS ISAs,
//
-// - A MT {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
-// - A OP {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
-// - A MF {HI,LO} read was not corrupted by a preceeding MT{LO,HI} update
-// corruption occures when MT{LO,HI} is preceeded by a OP {HI,LO}.
+// OP {HI and LO} followed by MT{LO or HI} (and not MT{HI or LO})
+// makes subsequent MF{HI or LO} UNPREDICTABLE. (1)
//
+// The following restrictions exist for MIPS I - MIPS III:
+//
+// MF{HI or LO} followed by MT{HI or LO} w/ less than 2 instructions
+// in between makes MF UNPREDICTABLE. (2)
+//
+// MF{HI or LO} followed by OP {HI and LO} w/ less than 2 instructions
+// in between makes MF UNPREDICTABLE. (3)
+//
+// On the r3900, restriction (2) is not present, and restriction (3) is not
+// present for multiplication.
+//
+// Unfortunately, there seems to be some confusion about whether the last
+// two restrictions should apply to "MIPS IV" as well. One edition of
+// the MIPS IV ISA says they do, but references in later ISA documents
+// suggest they don't.
+//
+// In reality, some MIPS IV parts, such as the VR5000 and VR5400, do have
+// these restrictions, while others, like the VR5500, don't. To accomodate
+// such differences, the MIPS IV and MIPS V version of these helper functions
+// use auxillary routines to determine whether the restriction applies.
+// check_mf_cycles:
+//
+// Helper used by check_mt_hilo, check_mult_hilo, and check_div_hilo
+// to check for restrictions (2) and (3) above.
+//
:function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
{
if (history->mf.timestamp + 3 > time)
return 1;
}
+
+// check_mt_hilo:
+//
+// Check for restriction (2) above (for ISAs/processors that have it),
+// and record timestamps for restriction (1) above.
+//
:function:::int:check_mt_hilo:hilo_history *history
*mipsI:
*mipsII:
*mipsIII:
-*mipsIV:
-*mipsV:
*vr4100:
*vr5000:
{
return ok;
}
+:function:::int:check_mt_hilo:hilo_history *history
+*mipsIV:
+*mipsV:
+{
+ signed64 time = sim_events_time (SD);
+ int ok = (! MIPS_MACH_HAS_MT_HILO_HAZARD (SD)
+ || check_mf_cycles (SD_, history, time, "MT"));
+ history->mt.timestamp = time;
+ history->mt.cia = CIA;
+ return ok;
+}
+
:function:::int:check_mt_hilo:hilo_history *history
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*r3900:
+*micromips32:
+*micromips64:
{
signed64 time = sim_events_time (SD);
history->mt.timestamp = time;
}
+// check_mf_hilo:
+//
+// Check for restriction (1) above, and record timestamps for
+// restriction (2) and (3) above.
+//
:function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
*mipsI:
*mipsII:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
+*micromips32:
+*micromips64:
{
signed64 time = sim_events_time (SD);
int ok = 1;
+// check_mult_hilo:
+//
+// Check for restriction (3) above (for ISAs/processors that have it)
+// for MULT ops, and record timestamps for restriction (1) above.
+//
:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
*mipsI:
*mipsII:
*mipsIII:
-*mipsIV:
-*mipsV:
*vr4100:
*vr5000:
{
return ok;
}
-// The r3900 mult and multu insns _can_ be exectuted immediatly after
-// a mf{hi,lo}
+:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
+*mipsIV:
+*mipsV:
+{
+ signed64 time = sim_events_time (SD);
+ int ok = (! MIPS_MACH_HAS_MULT_HILO_HAZARD (SD)
+ || (check_mf_cycles (SD_, hi, time, "OP")
+ && check_mf_cycles (SD_, lo, time, "OP")));
+ hi->op.timestamp = time;
+ lo->op.timestamp = time;
+ hi->op.cia = CIA;
+ lo->op.cia = CIA;
+ return ok;
+}
+
:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*r3900:
+*micromips32:
+*micromips64:
{
/* FIXME: could record the fact that a stall occured if we want */
signed64 time = sim_events_time (SD);
}
+// check_div_hilo:
+//
+// Check for restriction (3) above (for ISAs/processors that have it)
+// for DIV ops, and record timestamps for restriction (1) above.
+//
:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
*mipsI:
*mipsII:
*mipsIII:
+*vr4100:
+*vr5000:
+*r3900:
+{
+ signed64 time = sim_events_time (SD);
+ int ok = (check_mf_cycles (SD_, hi, time, "OP")
+ && check_mf_cycles (SD_, lo, time, "OP"));
+ hi->op.timestamp = time;
+ lo->op.timestamp = time;
+ hi->op.cia = CIA;
+ lo->op.cia = CIA;
+ return ok;
+}
+
+:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
*mipsIV:
*mipsV:
+{
+ signed64 time = sim_events_time (SD);
+ int ok = (! MIPS_MACH_HAS_DIV_HILO_HAZARD (SD)
+ || (check_mf_cycles (SD_, hi, time, "OP")
+ && check_mf_cycles (SD_, lo, time, "OP")));
+ hi->op.timestamp = time;
+ lo->op.timestamp = time;
+ hi->op.cia = CIA;
+ lo->op.cia = CIA;
+ return ok;
+}
+
+:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
+*micromips32:
+*micromips64:
+{
+ signed64 time = sim_events_time (SD);
+ hi->op.timestamp = time;
+ lo->op.timestamp = time;
+ hi->op.cia = CIA;
+ lo->op.cia = CIA;
+ return 1;
+}
+
+
+// Helper:
+//
+// Check that the 64-bit instruction can currently be used, and signal
+// a ReservedInstruction exception if not.
+//
+
+:function:::void:check_u64:instruction_word insn
+*mipsIII:
+*mipsIV:
+*mipsV:
*vr4100:
*vr5000:
+*vr5400:
+*vr5500:
*r3900:
{
- signed64 time = sim_events_time (SD);
- int ok = (check_mf_cycles (SD_, hi, time, "OP")
- && check_mf_cycles (SD_, lo, time, "OP"));
- hi->op.timestamp = time;
- lo->op.timestamp = time;
- hi->op.cia = CIA;
- lo->op.cia = CIA;
- return ok;
+ // The check should be similar to mips64 for any with PX/UX bit equivalents.
+}
+
+:function:::void:check_u64:instruction_word insn
+*mips16e:
+*mips64:
+*mips64r2:
+*mips32:
+*mips32r2:
+*micromips64:
+*micromips32:
+{
+#if 0 /* XXX FIXME: enable this only after some additional testing. */
+ if (UserMode && (SR & (status_UX|status_PX)) == 0)
+ SignalException (ReservedInstruction, insn);
+#endif
+}
+
+
+
+//
+// MIPS Architecture:
+//
+// CPU Instruction Set (mipsI - mipsV, mips32/r2, mips64/r2)
+//
+
+
+:function:::void:do_add:int rs, int rt, int rd
+{
+ if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
+ Unpredictable ();
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+ {
+ ALU32_BEGIN (GPR[rs]);
+ ALU32_ADD (GPR[rt]);
+ ALU32_END (GPR[rd]); /* This checks for overflow. */
+ }
+ TRACE_ALU_RESULT (GPR[rd]);
+}
+
+:function:::void:do_addi:int rs, int rt, unsigned16 immediate
+{
+ if (NotWordValue (GPR[rs]))
+ Unpredictable ();
+ TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
+ {
+ ALU32_BEGIN (GPR[rs]);
+ ALU32_ADD (EXTEND16 (immediate));
+ ALU32_END (GPR[rt]); /* This checks for overflow. */
+ }
+ TRACE_ALU_RESULT (GPR[rt]);
+}
+
+:function:::void:do_andi:int rs, int rt, unsigned int immediate
+{
+ TRACE_ALU_INPUT2 (GPR[rs], immediate);
+ GPR[rt] = GPR[rs] & immediate;
+ TRACE_ALU_RESULT (GPR[rt]);
+}
+
+:function:::void:do_dadd:int rd, int rs, int rt
+{
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+ {
+ ALU64_BEGIN (GPR[rs]);
+ ALU64_ADD (GPR[rt]);
+ ALU64_END (GPR[rd]); /* This checks for overflow. */
+ }
+ TRACE_ALU_RESULT (GPR[rd]);
+}
+
+:function:::void:do_daddi:int rt, int rs, int immediate
+{
+ TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
+ {
+ ALU64_BEGIN (GPR[rs]);
+ ALU64_ADD (EXTEND16 (immediate));
+ ALU64_END (GPR[rt]); /* This checks for overflow. */
+ }
+ TRACE_ALU_RESULT (GPR[rt]);
+}
+
+:function:::void:do_dsll32:int rd, int rt, int shift
+{
+ int s = 32 + shift;
+ TRACE_ALU_INPUT2 (GPR[rt], s);
+ GPR[rd] = GPR[rt] << s;
+ TRACE_ALU_RESULT (GPR[rd]);
+}
+
+:function:::void:do_dsra32:int rd, int rt, int shift
+{
+ int s = 32 + shift;
+ TRACE_ALU_INPUT2 (GPR[rt], s);
+ GPR[rd] = ((signed64) GPR[rt]) >> s;
+ TRACE_ALU_RESULT (GPR[rd]);
+}
+
+:function:::void:do_dsrl32:int rd, int rt, int shift
+{
+ int s = 32 + shift;
+ TRACE_ALU_INPUT2 (GPR[rt], s);
+ GPR[rd] = (unsigned64) GPR[rt] >> s;
+ TRACE_ALU_RESULT (GPR[rd]);
+}
+
+:function:::void:do_dsub:int rd, int rs, int rt
+{
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+ {
+ ALU64_BEGIN (GPR[rs]);
+ ALU64_SUB (GPR[rt]);
+ ALU64_END (GPR[rd]); /* This checks for overflow. */
+ }
+ TRACE_ALU_RESULT (GPR[rd]);
+}
+
+:function:::void:do_break:address_word instruction_0
+{
+ /* Check for some break instruction which are reserved for use by the
+ simulator. */
+ unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
+ if (break_code == (HALT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
+ break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
+ {
+ sim_engine_halt (SD, CPU, NULL, cia,
+ sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
+ }
+ else if (break_code == (BREAKPOINT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
+ break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
+ {
+ if (STATE & simDELAYSLOT)
+ PC = cia - 4; /* reference the branch instruction */
+ else
+ PC = cia;
+ SignalException (BreakPoint, instruction_0);
+ }
+
+ else
+ {
+ /* If we get this far, we're not an instruction reserved by the sim. Raise
+ the exception. */
+ SignalException (BreakPoint, instruction_0);
+ }
+}
+
+:function:::void:do_break16:address_word instruction_0
+{
+ if (STATE & simDELAYSLOT)
+ PC = cia - 2; /* reference the branch instruction */
+ else
+ PC = cia;
+ SignalException (BreakPoint, instruction_0);
+}
+
+:function:::void:do_clo:int rd, int rs
+{
+ unsigned32 temp = GPR[rs];
+ unsigned32 i, mask;
+ if (NotWordValue (GPR[rs]))
+ Unpredictable ();
+ TRACE_ALU_INPUT1 (GPR[rs]);
+ for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
+ {
+ if ((temp & mask) == 0)
+ break;
+ mask >>= 1;
+ }
+ GPR[rd] = EXTEND32 (i);
+ TRACE_ALU_RESULT (GPR[rd]);
+}
+
+:function:::void:do_clz:int rd, int rs
+{
+ unsigned32 temp = GPR[rs];
+ unsigned32 i, mask;
+ if (NotWordValue (GPR[rs]))
+ Unpredictable ();
+ TRACE_ALU_INPUT1 (GPR[rs]);
+ for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
+ {
+ if ((temp & mask) != 0)
+ break;
+ mask >>= 1;
+ }
+ GPR[rd] = EXTEND32 (i);
+ TRACE_ALU_RESULT (GPR[rd]);
+}
+
+:function:::void:do_dclo:int rd, int rs
+{
+ unsigned64 temp = GPR[rs];
+ unsigned32 i;
+ unsigned64 mask;
+ TRACE_ALU_INPUT1 (GPR[rs]);
+ for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
+ {
+ if ((temp & mask) == 0)
+ break;
+ mask >>= 1;
+ }
+ GPR[rd] = EXTEND32 (i);
+ TRACE_ALU_RESULT (GPR[rd]);
+}
+
+:function:::void:do_dclz:int rd, int rs
+{
+ unsigned64 temp = GPR[rs];
+ unsigned32 i;
+ unsigned64 mask;
+ TRACE_ALU_INPUT1 (GPR[rs]);
+ for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
+ {
+ if ((temp & mask) != 0)
+ break;
+ mask >>= 1;
+ }
+ GPR[rd] = EXTEND32 (i);
+ TRACE_ALU_RESULT (GPR[rd]);
+}
+
+:function:::void:do_lb:int rt, int offset, int base
+{
+ GPR[rt] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[base],
+ EXTEND16 (offset)));
+}
+
+:function:::void:do_lh:int rt, int offset, int base
+{
+ GPR[rt] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[base],
+ EXTEND16 (offset)));
+}
+
+:function:::void:do_lwr:int rt, int offset, int base
+{
+ GPR[rt] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[base],
+ EXTEND16 (offset), GPR[rt]));
+}
+
+:function:::void:do_lwl:int rt, int offset, int base
+{
+ GPR[rt] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[base],
+ EXTEND16 (offset), GPR[rt]));
+}
+
+:function:::void:do_lwc:int num, int rt, int offset, int base
+{
+ COP_LW (num, rt, do_load (SD_, AccessLength_WORD, GPR[base],
+ EXTEND16 (offset)));
+}
+
+:function:::void:do_lw:int rt, int offset, int base
+{
+ GPR[rt] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[base],
+ EXTEND16 (offset)));
+}
+
+:function:::void:do_lwu:int rt, int offset, int base, address_word instruction_0
+{
+ check_u64 (SD_, instruction_0);
+ GPR[rt] = do_load (SD_, AccessLength_WORD, GPR[base], EXTEND16 (offset));
+}
+
+:function:::void:do_lhu:int rt, int offset, int base
+{
+ GPR[rt] = do_load (SD_, AccessLength_HALFWORD, GPR[base], EXTEND16 (offset));
+}
+
+:function:::void:do_ldc:int num, int rt, int offset, int base
+{
+ COP_LD (num, rt, do_load (SD_, AccessLength_DOUBLEWORD, GPR[base],
+ EXTEND16 (offset)));
+}
+
+:function:::void:do_lbu:int rt, int offset, int base
+{
+ GPR[rt] = do_load (SD_, AccessLength_BYTE, GPR[base], EXTEND16 (offset));
+}
+
+:function:::void:do_ll:int rt, int insn_offset, int basereg
+{
+ address_word base = GPR[basereg];
+ address_word offset = EXTEND16 (insn_offset);
+ {
+ address_word vaddr = loadstore_ea (SD_, base, offset);
+ address_word paddr = vaddr;
+ if ((vaddr & 3) != 0)
+ {
+ SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer,
+ sim_core_unaligned_signal);
+ }
+ else
+ {
+ unsigned64 memval = 0;
+ unsigned64 memval1 = 0;
+ unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+ unsigned int shift = 2;
+ unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
+ unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
+ unsigned int byte;
+ paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
+ LoadMemory (&memval, &memval1, AccessLength_WORD, paddr, vaddr,
+ isDATA, isREAL);
+ byte = ((vaddr & mask) ^ (bigend << shift));
+ GPR[rt] = EXTEND32 (memval >> (8 * byte));
+ LLBIT = 1;
+ }
+ }
+}
+
+:function:::void:do_lld:int rt, int roffset, int rbase
+{
+ address_word base = GPR[rbase];
+ address_word offset = EXTEND16 (roffset);
+ {
+ address_word vaddr = loadstore_ea (SD_, base, offset);
+ address_word paddr = vaddr;
+
+ if ((vaddr & 7) != 0)
+ {
+ SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer,
+ sim_core_unaligned_signal);
+ }
+ else
+ {
+ unsigned64 memval = 0;
+ unsigned64 memval1 = 0;
+ LoadMemory (&memval, &memval1, AccessLength_DOUBLEWORD, paddr, vaddr,
+ isDATA, isREAL);
+ GPR[rt] = memval;
+ LLBIT = 1;
+ }
+ }
+}
+
+:function:::void:do_lui:int rt, int immediate
+{
+ TRACE_ALU_INPUT1 (immediate);
+ GPR[rt] = EXTEND32 (immediate << 16);
+ TRACE_ALU_RESULT (GPR[rt]);
+}
+
+:function:::void:do_madd:int rs, int rt
+{
+ signed64 temp;
+ check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
+ if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
+ Unpredictable ();
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+ temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
+ + ((signed64) EXTEND32 (GPR[rt]) * (signed64) EXTEND32 (GPR[rs])));
+ LO = EXTEND32 (temp);
+ HI = EXTEND32 (VH4_8 (temp));
+ TRACE_ALU_RESULT2 (HI, LO);
+}
+
+:function:::void:do_dsp_madd:int ac, int rs, int rt
+{
+ signed64 temp;
+ if (ac == 0)
+ check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
+ if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
+ Unpredictable ();
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+ temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac)))
+ + ((signed64) EXTEND32 (GPR[rt]) * (signed64) EXTEND32 (GPR[rs])));
+ DSPLO(ac) = EXTEND32 (temp);
+ DSPHI(ac) = EXTEND32 (VH4_8 (temp));
+ if (ac == 0)
+ TRACE_ALU_RESULT2 (HI, LO);
+}
+
+:function:::void:do_maddu:int rs, int rt
+{
+ unsigned64 temp;
+ check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
+ if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
+ Unpredictable ();
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+ temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
+ + ((unsigned64) VL4_8 (GPR[rs]) * (unsigned64) VL4_8 (GPR[rt])));
+ ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp; /* SmartMIPS */
+ LO = EXTEND32 (temp);
+ HI = EXTEND32 (VH4_8 (temp));
+ TRACE_ALU_RESULT2 (HI, LO);
+}
+
+:function:::void:do_dsp_maddu:int ac, int rs, int rt
+{
+ unsigned64 temp;
+ if (ac == 0)
+ check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
+ if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
+ Unpredictable ();
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+ temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac)))
+ + ((unsigned64) VL4_8 (GPR[rs]) * (unsigned64) VL4_8 (GPR[rt])));
+ if (ac == 0)
+ ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp; /* SmartMIPS */
+ DSPLO(ac) = EXTEND32 (temp);
+ DSPHI(ac) = EXTEND32 (VH4_8 (temp));
+ if (ac == 0)
+ TRACE_ALU_RESULT2 (HI, LO);
+}
+
+:function:::void:do_dsp_mfhi:int ac, int rd
+{
+ if (ac == 0)
+ do_mfhi (SD_, rd);
+ else
+ GPR[rd] = DSPHI(ac);
+}
+
+:function:::void:do_dsp_mflo:int ac, int rd
+{
+ if (ac == 0)
+ do_mflo (SD_, rd);
+ else
+ GPR[rd] = DSPLO(ac);
+}
+
+:function:::void:do_movn:int rd, int rs, int rt
+{
+ if (GPR[rt] != 0)
+ {
+ GPR[rd] = GPR[rs];
+ TRACE_ALU_RESULT (GPR[rd]);
+ }
+}
+
+:function:::void:do_movz:int rd, int rs, int rt
+{
+ if (GPR[rt] == 0)
+ {
+ GPR[rd] = GPR[rs];
+ TRACE_ALU_RESULT (GPR[rd]);
+ }
+}
+
+:function:::void:do_msub:int rs, int rt
+{
+ signed64 temp;
+ check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
+ if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
+ Unpredictable ();
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+ temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
+ - ((signed64) EXTEND32 (GPR[rt]) * (signed64) EXTEND32 (GPR[rs])));
+ LO = EXTEND32 (temp);
+ HI = EXTEND32 (VH4_8 (temp));
+ TRACE_ALU_RESULT2 (HI, LO);
+}
+
+:function:::void:do_dsp_msub:int ac, int rs, int rt
+{
+ signed64 temp;
+ if (ac == 0)
+ check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
+ if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
+ Unpredictable ();
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+ temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac)))
+ - ((signed64) EXTEND32 (GPR[rt]) * (signed64) EXTEND32 (GPR[rs])));
+ DSPLO(ac) = EXTEND32 (temp);
+ DSPHI(ac) = EXTEND32 (VH4_8 (temp));
+ if (ac == 0)
+ TRACE_ALU_RESULT2 (HI, LO);
+}
+
+:function:::void:do_msubu:int rs, int rt
+{
+ unsigned64 temp;
+ check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
+ if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
+ Unpredictable ();
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+ temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
+ - ((unsigned64) VL4_8 (GPR[rs]) * (unsigned64) VL4_8 (GPR[rt])));
+ LO = EXTEND32 (temp);
+ HI = EXTEND32 (VH4_8 (temp));
+ TRACE_ALU_RESULT2 (HI, LO);
+}
+
+:function:::void:do_dsp_msubu:int ac, int rs, int rt
+{
+ unsigned64 temp;
+ if (ac == 0)
+ check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
+ if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
+ Unpredictable ();
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+ temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac)))
+ - ((unsigned64) VL4_8 (GPR[rs]) * (unsigned64) VL4_8 (GPR[rt])));
+ DSPLO(ac) = EXTEND32 (temp);
+ DSPHI(ac) = EXTEND32 (VH4_8 (temp));
+ if (ac == 0)
+ TRACE_ALU_RESULT2 (HI, LO);
+}
+
+:function:::void:do_mthi:int rs
+{
+ check_mt_hilo (SD_, HIHISTORY);
+ HI = GPR[rs];
+}
+
+:function:::void:do_dsp_mthi:int ac, int rs
+{
+ if (ac == 0)
+ check_mt_hilo (SD_, HIHISTORY);
+ DSPHI(ac) = GPR[rs];
+}
+
+:function:::void:do_mtlo:int rs
+{
+ check_mt_hilo (SD_, LOHISTORY);
+ LO = GPR[rs];
+}
+
+:function:::void:do_dsp_mtlo:int ac, int rs
+{
+ if (ac == 0)
+ check_mt_hilo (SD_, LOHISTORY);
+ DSPLO(ac) = GPR[rs];
+}
+
+:function:::void:do_mul:int rd, int rs, int rt
+{
+ signed64 prod;
+ if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
+ Unpredictable ();
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+ prod = (((signed64)(signed32) GPR[rs])
+ * ((signed64)(signed32) GPR[rt]));
+ GPR[rd] = EXTEND32 (VL4_8 (prod));
+ TRACE_ALU_RESULT (GPR[rd]);
+}
+
+:function:::void:do_dsp_mult:int ac, int rs, int rt
+{
+ signed64 prod;
+ if (ac == 0)
+ check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
+ if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
+ Unpredictable ();
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+ prod = ((signed64)(signed32) GPR[rs])
+ * ((signed64)(signed32) GPR[rt]);
+ DSPLO(ac) = EXTEND32 (VL4_8 (prod));
+ DSPHI(ac) = EXTEND32 (VH4_8 (prod));
+ if (ac == 0)
+ {
+ ACX = 0; /* SmartMIPS */
+ TRACE_ALU_RESULT2 (HI, LO);
+ }
+}
+
+:function:::void:do_dsp_multu:int ac, int rs, int rt
+{
+ unsigned64 prod;
+ if (ac == 0)
+ check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
+ if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
+ Unpredictable ();
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+ prod = ((unsigned64)(unsigned32) GPR[rs])
+ * ((unsigned64)(unsigned32) GPR[rt]);
+ DSPLO(ac) = EXTEND32 (VL4_8 (prod));
+ DSPHI(ac) = EXTEND32 (VH4_8 (prod));
+ if (ac == 0)
+ TRACE_ALU_RESULT2 (HI, LO);
+}
+
+:function:::void:do_pref:int hint, int insn_offset, int insn_base
+{
+ address_word base = GPR[insn_base];
+ address_word offset = EXTEND16 (insn_offset);
+ {
+ address_word vaddr = loadstore_ea (SD_, base, offset);
+ address_word paddr = vaddr;
+ /* Prefetch (paddr, vaddr, isDATA, hint); */
+ }
+}
+
+:function:::void:do_sc:int rt, int offsetarg, int basereg, address_word instruction_0
+{
+ unsigned32 instruction = instruction_0;
+ address_word base = GPR[basereg];
+ address_word offset = EXTEND16 (offsetarg);
+ {
+ address_word vaddr = loadstore_ea (SD_, base, offset);
+ address_word paddr = vaddr;
+
+ if ((vaddr & 3) != 0)
+ {
+ SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer,
+ sim_core_unaligned_signal);
+ }
+ else
+ {
+ unsigned64 memval = 0;
+ unsigned64 memval1 = 0;
+ unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+ address_word reverseendian =
+ (ReverseEndian ? (mask ^ AccessLength_WORD) : 0);
+ address_word bigendiancpu =
+ (BigEndianCPU ? (mask ^ AccessLength_WORD) : 0);
+ unsigned int byte;
+ paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
+ byte = ((vaddr & mask) ^ bigendiancpu);
+ memval = ((unsigned64) GPR[rt] << (8 * byte));
+ if (LLBIT)
+ StoreMemory (AccessLength_WORD, memval, memval1, paddr, vaddr,
+ isREAL);
+ GPR[rt] = LLBIT;
+ }
+ }
+}
+
+:function:::void:do_scd:int rt, int roffset, int rbase
+{
+ address_word base = GPR[rbase];
+ address_word offset = EXTEND16 (roffset);
+ {
+ address_word vaddr = loadstore_ea (SD_, base, offset);
+ address_word paddr = vaddr;
+
+ if ((vaddr & 7) != 0)
+ {
+ SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer,
+ sim_core_unaligned_signal);
+ }
+ else
+ {
+ unsigned64 memval = 0;
+ unsigned64 memval1 = 0;
+ memval = GPR[rt];
+ if (LLBIT)
+ StoreMemory (AccessLength_DOUBLEWORD, memval, memval1, paddr, vaddr,
+ isREAL);
+ GPR[rt] = LLBIT;
+ }
+ }
+}
+
+:function:::void:do_sub:int rs, int rt, int rd
+{
+ if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
+ Unpredictable ();
+ TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
+ {
+ ALU32_BEGIN (GPR[rs]);
+ ALU32_SUB (GPR[rt]);
+ ALU32_END (GPR[rd]); /* This checks for overflow. */
+ }
+ TRACE_ALU_RESULT (GPR[rd]);
+}
+
+:function:::void:do_sw:int rt, int offset, int base
+{
+ do_store (SD_, AccessLength_WORD, GPR[base], EXTEND16 (offset), GPR[rt]);
+}
+
+:function:::void:do_teq:int rs, int rt, address_word instruction_0
+{
+ if ((signed_word) GPR[rs] == (signed_word) GPR[rt])
+ SignalException (Trap, instruction_0);
+}
+
+:function:::void:do_teqi:int rs, int immediate, address_word instruction_0
+{
+ if ((signed_word) GPR[rs] == (signed_word) EXTEND16 (immediate))
+ SignalException (Trap, instruction_0);
+}
+
+:function:::void:do_tge:int rs, int rt, address_word instruction_0
+{
+ if ((signed_word) GPR[rs] >= (signed_word) GPR[rt])
+ SignalException (Trap, instruction_0);
+}
+
+:function:::void:do_tgei:int rs, int immediate, address_word instruction_0
+{
+ if ((signed_word) GPR[rs] >= (signed_word) EXTEND16 (immediate))
+ SignalException (Trap, instruction_0);
+}
+
+:function:::void:do_tgeiu:int rs, int immediate, address_word instruction_0
+{
+ if ((unsigned_word) GPR[rs] >= (unsigned_word) EXTEND16 (immediate))
+ SignalException (Trap, instruction_0);
+}
+
+:function:::void:do_tgeu:int rs ,int rt, address_word instruction_0
+{
+ if ((unsigned_word) GPR[rs] >= (unsigned_word) GPR[rt])
+ SignalException (Trap, instruction_0);
+}
+
+:function:::void:do_tlt:int rs, int rt, address_word instruction_0
+{
+ if ((signed_word) GPR[rs] < (signed_word) GPR[rt])
+ SignalException (Trap, instruction_0);
+}
+
+:function:::void:do_tlti:int rs, int immediate, address_word instruction_0
+{
+ if ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate))
+ SignalException (Trap, instruction_0);
+}
+
+:function:::void:do_tltiu:int rs, int immediate, address_word instruction_0
+{
+ if ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate))
+ SignalException (Trap, instruction_0);
+}
+
+:function:::void:do_tltu:int rs, int rt, address_word instruction_0
+{
+ if ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt])
+ SignalException (Trap, instruction_0);
+}
+
+:function:::void:do_tne:int rs, int rt, address_word instruction_0
+{
+ if ((signed_word) GPR[rs] != (signed_word) GPR[rt])
+ SignalException (Trap, instruction_0);
+}
+
+:function:::void:do_tnei:int rs, int immediate, address_word instruction_0
+{
+ if ((signed_word) GPR[rs] != (signed_word) EXTEND16 (immediate))
+ SignalException (Trap, instruction_0);
+}
+
+:function:::void:do_abs_fmt:int fmt, int fd, int fs, address_word instruction_0
+{
+ check_fpu (SD_);
+ check_fmt_p (SD_, fmt, instruction_0);
+ StoreFPR (fd, fmt, AbsoluteValue (ValueFPR (fs, fmt), fmt));
+}
+
+:function:::void:do_add_fmt:int fmt, int fd, int fs, int ft, address_word instruction_0
+{
+ check_fpu (SD_);
+ check_fmt_p (SD_, fmt, instruction_0);
+ StoreFPR (fd, fmt, Add (ValueFPR (fs, fmt), ValueFPR (ft, fmt), fmt));
+}
+
+:function:::void:do_alnv_ps:int fd, int fs, int ft, int rs, address_word instruction_0
+{
+ unsigned64 fsx;
+ unsigned64 ftx;
+ unsigned64 fdx;
+ check_fpu (SD_);
+ check_u64 (SD_, instruction_0);
+ fsx = ValueFPR (fs, fmt_ps);
+ if ((GPR[rs] & 0x3) != 0)
+ Unpredictable ();
+ if ((GPR[rs] & 0x4) == 0)
+ fdx = fsx;
+ else
+ {
+ ftx = ValueFPR (ft, fmt_ps);
+ if (BigEndianCPU)
+ fdx = PackPS (PSLower (fsx), PSUpper (ftx));
+ else
+ fdx = PackPS (PSLower (ftx), PSUpper (fsx));
+ }
+ StoreFPR (fd, fmt_ps, fdx);
+}
+
+:function:::void:do_c_cond_fmt:int cond, int fmt, int cc, int fs, int ft, address_word instruction_0
+{
+ check_fpu (SD_);
+ check_fmt_p (SD_, fmt, instruction_0);
+ Compare (ValueFPR (fs, fmt), ValueFPR (ft, fmt), fmt, cond, cc);
+ TRACE_ALU_RESULT (ValueFCR (31));
+}
+
+:function:::void:do_ceil_fmt:int type, int fmt, int fd, int fs, address_word instruction_0
+{
+ check_fpu (SD_);
+ check_fmt_p (SD_, fmt, instruction_0);
+ StoreFPR (fd, type, Convert (FP_RM_TOPINF, ValueFPR (fs, fmt), fmt,
+ type));
+}
+
+:function:::void:do_cfc1:int rt, int fs
+{
+ check_fpu (SD_);
+ if (fs == 0 || fs == 25 || fs == 26 || fs == 28 || fs == 31)
+ {
+ unsigned_word fcr = ValueFCR (fs);
+ TRACE_ALU_INPUT1 (fcr);
+ GPR[rt] = fcr;
+ }
+ /* else NOP */
+ TRACE_ALU_RESULT (GPR[rt]);
+}
+
+:function:::void:do_ctc1:int rt, int fs
+{
+ check_fpu (SD_);
+ TRACE_ALU_INPUT1 (GPR[rt]);
+ if (fs == 25 || fs == 26 || fs == 28 || fs == 31)
+ StoreFCR (fs, GPR[rt]);
+ /* else NOP */
+}
+
+:function:::void:do_cvt_d_fmt:int fmt, int fd, int fs, address_word instruction_0
+{
+ check_fpu (SD_);
+ if ((fmt == fmt_double) | 0)
+ SignalException (ReservedInstruction, instruction_0);
+ StoreFPR (fd, fmt_double, Convert (GETRM (), ValueFPR (fs, fmt), fmt,
+ fmt_double));
+}
+
+:function:::void:do_cvt_l_fmt:int fmt, int fd, int fs, address_word instruction_0
+{
+ check_fpu (SD_);
+ if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word)))
+ SignalException (ReservedInstruction, instruction_0);
+ StoreFPR (fd, fmt_long, Convert (GETRM (), ValueFPR (fs, fmt), fmt,
+ fmt_long));
+}
+
+:function:::void:do_cvt_ps_s:int fd, int fs, int ft, address_word instruction_0
+{
+ check_fpu (SD_);
+ check_u64 (SD_, instruction_0);
+ StoreFPR (fd, fmt_ps, PackPS (ValueFPR (fs, fmt_single),
+ ValueFPR (ft, fmt_single)));
+}
+
+:function:::void:do_cvt_s_fmt:int fmt, int fd, int fs, address_word instruction_0
+{
+ check_fpu (SD_);
+ if ((fmt == fmt_single) | 0)
+ SignalException (ReservedInstruction, instruction_0);
+ StoreFPR (fd, fmt_single, Convert (GETRM (), ValueFPR (fs, fmt), fmt,
+ fmt_single));
+}
+
+:function:::void:do_cvt_s_pl:int fd, int fs, address_word instruction_0
+{
+ check_fpu (SD_);
+ check_u64 (SD_, instruction_0);
+ StoreFPR (fd, fmt_single, PSLower (ValueFPR (fs, fmt_ps)));
+}
+
+:function:::void:do_cvt_s_pu:int fd, int fs, address_word instruction_0
+{
+ check_fpu (SD_);
+ check_u64 (SD_, instruction_0);
+ StoreFPR (fd, fmt_single, PSUpper (ValueFPR (fs, fmt_ps)));
+}
+
+:function:::void:do_cvt_w_fmt:int fmt, int fd, int fs, address_word instruction_0
+{
+ check_fpu (SD_);
+ if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word)))
+ SignalException (ReservedInstruction, instruction_0);
+ StoreFPR (fd, fmt_word, Convert (GETRM (), ValueFPR (fs, fmt), fmt,
+ fmt_word));
+}
+
+:function:::void:do_div_fmt:int fmt, int fd, int fs, int ft, address_word instruction_0
+{
+ check_fpu (SD_);
+ StoreFPR (fd, fmt, Divide (ValueFPR (fs, fmt), ValueFPR (ft, fmt), fmt));
+}
+
+:function:::void:do_dmfc1b:int rt, int fs
+*mipsIV:
+*mipsV:
+*mips64:
+*mips64r2:
+*vr4100:
+*vr5000:
+*r3900:
+*micromips64:
+{
+ if (SizeFGR () == 64)
+ GPR[rt] = FGR[fs];
+ else if ((fs & 0x1) == 0)
+ GPR[rt] = SET64HI (FGR[fs+1]) | FGR[fs];
+ else
+ GPR[rt] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
+ TRACE_ALU_RESULT (GPR[rt]);
+}
+
+:function:::void:do_dmtc1b:int rt, int fs
+{
+ if (SizeFGR () == 64)
+ StoreFPR (fs, fmt_uninterpreted_64, GPR[rt]);
+ else if ((fs & 0x1) == 0)
+ StoreFPR (fs, fmt_uninterpreted_64, GPR[rt]);
+ else
+ Unpredictable ();
+}
+
+:function:::void:do_floor_fmt:int type, int fmt, int fd, int fs
+{
+ check_fpu (SD_);
+ StoreFPR (fd, type, Convert (FP_RM_TOMINF, ValueFPR (fs, fmt), fmt,
+ type));
+}
+
+:function:::void:do_luxc1_32:int fd, int rindex, int rbase
+*mips32r2:
+*micromips32:
+{
+ address_word base = GPR[rbase];
+ address_word index = GPR[rindex];
+ address_word vaddr = base + index;
+ check_fpu (SD_);
+ if (SizeFGR () != 64)
+ Unpredictable ();
+ /* Arrange for the bottom 3 bits of (base + index) to be 0. */
+ if ((vaddr & 0x7) != 0)
+ index -= (vaddr & 0x7);
+ COP_LD (1, fd, do_load_double (SD_, base, index));
+}
+
+:function:::void:do_luxc1_64:int fd, int rindex, int rbase
+{
+ address_word base = GPR[rbase];
+ address_word index = GPR[rindex];
+ address_word vaddr = base + index;
+ if (SizeFGR () != 64)
+ Unpredictable ();
+ /* Arrange for the bottom 3 bits of (base + index) to be 0. */
+ if ((vaddr & 0x7) != 0)
+ index -= (vaddr & 0x7);
+ COP_LD (1, fd, do_load (SD_, AccessLength_DOUBLEWORD, base, index));
+
+}
+
+:function:::void:do_lwc1:int ft, int offset, int base
+{
+ check_fpu (SD_);
+ COP_LW (1, ft, do_load (SD_, AccessLength_WORD, GPR[base],
+ EXTEND16 (offset)));
+}
+
+:function:::void:do_lwxc1:int fd, int index, int base, address_word instruction_0
+{
+ check_fpu (SD_);
+ check_u64 (SD_, instruction_0);
+ COP_LW (1, fd, do_load (SD_, AccessLength_WORD, GPR[base], GPR[index]));
+}
+
+:function:::void:do_madd_fmt:int fmt, int fd, int fr, int fs, int ft, address_word instruction_0
+{
+ check_fpu (SD_);
+ check_u64 (SD_, instruction_0);
+ check_fmt_p (SD_, fmt, instruction_0);
+ StoreFPR (fd, fmt, MultiplyAdd (ValueFPR (fs, fmt), ValueFPR (ft, fmt),
+ ValueFPR (fr, fmt), fmt));
+}
+
+:function:::void:do_mfc1b:int rt, int fs
+{
+ check_fpu (SD_);
+ GPR[rt] = EXTEND32 (FGR[fs]);
+ TRACE_ALU_RESULT (GPR[rt]);
+}
+
+:function:::void:do_mov_fmt:int fmt, int fd, int fs, address_word instruction_0
+{
+ check_fpu (SD_);
+ check_fmt_p (SD_, fmt, instruction_0);
+ StoreFPR (fd, fmt, ValueFPR (fs, fmt));
+}
+
+:function:::void:do_movtf:int tf, int rd, int rs, int cc
+{
+ check_fpu (SD_);
+ if (GETFCC(cc) == tf)
+ GPR[rd] = GPR[rs];
+}
+
+:function:::void:do_movtf_fmt:int tf, int fmt, int fd, int fs, int cc
+{
+ check_fpu (SD_);
+ if (fmt != fmt_ps)
+ {
+ if (GETFCC(cc) == tf)
+ StoreFPR (fd, fmt, ValueFPR (fs, fmt));
+ else
+ StoreFPR (fd, fmt, ValueFPR (fd, fmt)); /* set fmt */
+ }
+ else
+ {
+ unsigned64 fdx;
+ fdx = PackPS (PSUpper (ValueFPR ((GETFCC (cc+1) == tf) ? fs : fd,
+ fmt_ps)),
+ PSLower (ValueFPR ((GETFCC (cc+0) == tf) ? fs : fd,
+ fmt_ps)));
+ StoreFPR (fd, fmt_ps, fdx);
+ }
+}
+
+:function:::void:do_movn_fmt:int fmt, int fd, int fs, int rt
+{
+ check_fpu (SD_);
+ if (GPR[rt] != 0)
+ StoreFPR (fd, fmt, ValueFPR (fs, fmt));
+ else
+ StoreFPR (fd, fmt, ValueFPR (fd, fmt));
+}
+
+:function:::void:do_movz_fmt:int fmt, int fd, int fs, int rt
+{
+ check_fpu (SD_);
+ if (GPR[rt] == 0)
+ StoreFPR (fd, fmt, ValueFPR (fs, fmt));
+ else
+ StoreFPR (fd, fmt, ValueFPR (fd, fmt));
+}
+
+:function:::void:do_msub_fmt:int fmt, int fd, int fr, int fs, int ft, address_word instruction_0
+{
+ check_fpu (SD_);
+ check_u64 (SD_, instruction_0);
+ check_fmt_p (SD_, fmt, instruction_0);
+ StoreFPR (fd, fmt, MultiplySub (ValueFPR (fs, fmt), ValueFPR (ft, fmt),
+ ValueFPR (fr, fmt), fmt));
+}
+
+:function:::void:do_mtc1b:int rt, int fs
+{
+ check_fpu (SD_);
+ StoreFPR (fs, fmt_uninterpreted_32, VL4_8 (GPR[rt]));
+}
+
+:function:::void:do_mul_fmt:int fmt, int fd, int fs, int ft, address_word instruction_0
+{
+ check_fpu (SD_);
+ check_fmt_p (SD_, fmt, instruction_0);
+ StoreFPR (fd, fmt, Multiply (ValueFPR (fs, fmt), ValueFPR (ft, fmt), fmt));
+}
+
+:function:::void:do_neg_fmt:int fmt, int fd, int fs, address_word instruction_0
+{
+ check_fpu (SD_);
+ check_fmt_p (SD_, fmt, instruction_0);
+ StoreFPR (fd, fmt, Negate (ValueFPR (fs, fmt), fmt));
+}
+
+:function:::void:do_nmadd_fmt:int fmt, int fd, int fr, int fs, int ft, address_word instruction_0
+{
+ check_fpu (SD_);
+ check_u64 (SD_, instruction_0);
+ check_fmt_p (SD_, fmt, instruction_0);
+ StoreFPR (fd, fmt, NegMultiplyAdd (ValueFPR (fs, fmt), ValueFPR (ft, fmt),
+ ValueFPR (fr, fmt), fmt));
+}
+
+:function:::void:do_nmsub_fmt:int fmt, int fd, int fr, int fs, int ft, address_word instruction_0
+{
+ check_fpu (SD_);
+ check_u64 (SD_, instruction_0);
+ check_fmt_p (SD_, fmt, instruction_0);
+ StoreFPR (fd, fmt, NegMultiplySub (ValueFPR (fs, fmt), ValueFPR (ft, fmt),
+ ValueFPR (fr, fmt), fmt));
+}
+
+:function:::void:do_pll_ps:int fd, int fs, int ft, address_word instruction_0
+{
+ check_fpu (SD_);
+ check_u64 (SD_, instruction_0);
+ StoreFPR (fd, fmt_ps, PackPS (PSLower (ValueFPR (fs, fmt_ps)),
+ PSLower (ValueFPR (ft, fmt_ps))));
+}
+
+:function:::void:do_plu_ps:int fd, int fs, int ft, address_word instruction_0
+{
+ check_fpu (SD_);
+ check_u64 (SD_, instruction_0);
+ StoreFPR (fd, fmt_ps, PackPS (PSLower (ValueFPR (fs, fmt_ps)),
+ PSUpper (ValueFPR (ft, fmt_ps))));
+}
+
+:function:::void:do_pul_ps:int fd, int fs, int ft, address_word instruction_0
+{
+ check_fpu (SD_);
+ check_u64 (SD_, instruction_0);
+ StoreFPR (fd, fmt_ps, PackPS (PSUpper (ValueFPR (fs, fmt_ps)),
+ PSLower (ValueFPR (ft, fmt_ps))));
+}
+
+:function:::void:do_puu_ps:int fd, int fs, int ft, address_word instruction_0
+{
+ check_fpu (SD_);
+ check_u64 (SD_, instruction_0);
+ StoreFPR (fd, fmt_ps, PackPS (PSUpper (ValueFPR (fs, fmt_ps)),
+ PSUpper (ValueFPR (ft, fmt_ps))));
+}
+
+:function:::void:do_recip_fmt:int fmt, int fd, int fs
+{
+ check_fpu (SD_);
+ StoreFPR (fd, fmt, Recip (ValueFPR (fs, fmt), fmt));
+}
+
+:function:::void:do_round_fmt:int type, int fmt, int fd, int fs
+{
+ check_fpu (SD_);
+ StoreFPR (fd, type, Convert (FP_RM_NEAREST, ValueFPR (fs, fmt), fmt,
+ type));
+}
+
+:function:::void:do_rsqrt_fmt:int fmt, int fd, int fs
+{
+ check_fpu (SD_);
+ StoreFPR (fd, fmt, RSquareRoot (ValueFPR (fs, fmt), fmt));
+}
+
+:function:::void:do_prefx:int hint, int rindex, int rbase
+{
+ address_word base = GPR[rbase];
+ address_word index = GPR[rindex];
+ {
+ address_word vaddr = loadstore_ea (SD_, base, index);
+ address_word paddr = vaddr;
+ /* Prefetch (paddr, vaddr, isDATA, hint); */
+ }
+}
+
+:function:::void:do_sdc1:int ft, int offset, int base
+*mipsII:
+*mips32:
+*mips32r2:
+*micromips32:
+{
+ check_fpu (SD_);
+ do_store_double (SD_, GPR[base], EXTEND16 (offset), COP_SD (1, ft));
}
+:function:::void:do_suxc1_32:int fs, int rindex, int rbase
+*mips32r2:
+*micromips32:
+{
+ address_word base = GPR[rbase];
+ address_word index = GPR[rindex];
+ address_word vaddr = base + index;
+ check_fpu (SD_);
+ if (SizeFGR () != 64)
+ Unpredictable ();
+ /* Arrange for the bottom 3 bits of (base + index) to be 0. */
+ if ((vaddr & 0x7) != 0)
+ index -= (vaddr & 0x7);
+ do_store_double (SD_, base, index, COP_SD (1, fs));
+}
-// Helper:
-//
-// Check that the 64-bit instruction can currently be used, and signal
-// a ReservedInstruction exception if not.
-//
+:function:::void:do_suxc1_64:int fs, int rindex, int rbase
+{
+ address_word base = GPR[rbase];
+ address_word index = GPR[rindex];
+ address_word vaddr = base + index;
+ if (SizeFGR () != 64)
+ Unpredictable ();
+ /* Arrange for the bottom 3 bits of (base + index) to be 0. */
+ if ((vaddr & 0x7) != 0)
+ index -= (vaddr & 0x7);
+ do_store (SD_, AccessLength_DOUBLEWORD, base, index, COP_SD (1, fs));
+}
-:function:::void:check_u64:instruction_word insn
-*mipsIII:
-*mipsIV:
-*mipsV:
-*vr4100:
-*vr5000:
+:function:::void:do_sqrt_fmt:int fmt, int fd, int fs
{
- // The check should be similar to mips64 for any with PX/UX bit equivalents.
+ check_fpu (SD_);
+ StoreFPR (fd, fmt, (SquareRoot (ValueFPR (fs, fmt), fmt)));
}
-:function:::void:check_u64:instruction_word insn
-*mips64:
+:function:::void:do_sub_fmt:int fmt, int fd, int fs, int ft, address_word instruction_0
{
-#if 0 /* XXX FIXME: enable this only after some additional testing. */
- if (UserMode && (SR & (status_UX|status_PX)) == 0)
- SignalException (ReservedInstruction, insn);
-#endif
+ check_fpu (SD_);
+ check_fmt_p (SD_, fmt, instruction_0);
+ StoreFPR (fd, fmt, Sub (ValueFPR (fs, fmt), ValueFPR (ft, fmt), fmt));
}
+:function:::void:do_swc1:int ft, int roffset, int rbase, address_word instruction_0
+{
+ address_word base = GPR[rbase];
+ address_word offset = EXTEND16 (roffset);
+ check_fpu (SD_);
+ {
+ address_word vaddr = loadstore_ea (SD_, base, offset);
+ address_word paddr = vaddr;
+ if ((vaddr & 3) != 0)
+ {
+ SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr,
+ write_transfer, sim_core_unaligned_signal);
+ }
+ else
+ {
+ uword64 memval = 0;
+ uword64 memval1 = 0;
+ uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+ address_word reverseendian =
+ (ReverseEndian ? (mask ^ AccessLength_WORD) : 0);
+ address_word bigendiancpu =
+ (BigEndianCPU ? (mask ^ AccessLength_WORD) : 0);
+ unsigned int byte;
+ paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
+ byte = ((vaddr & mask) ^ bigendiancpu);
+ memval = (((uword64)COP_SW(1, ft)) << (8 * byte));
+ StoreMemory (AccessLength_WORD, memval, memval1, paddr, vaddr, isREAL);
+ }
+ }
+}
-//
-// MIPS Architecture:
-//
-// CPU Instruction Set (mipsI - mipsV, mips32, mips64)
-//
+:function:::void:do_swxc1:int fs, int rindex, int rbase, address_word instruction_0
+{
+ address_word base = GPR[rbase];
+ address_word index = GPR[rindex];
+ check_fpu (SD_);
+ check_u64 (SD_, instruction_0);
+ {
+ address_word vaddr = loadstore_ea (SD_, base, index);
+ address_word paddr = vaddr;
+ if ((vaddr & 3) != 0)
+ {
+ SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer,
+ sim_core_unaligned_signal);
+ }
+ else
+ {
+ unsigned64 memval = 0;
+ unsigned64 memval1 = 0;
+ unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+ address_word reverseendian =
+ (ReverseEndian ? (mask ^ AccessLength_WORD) : 0);
+ address_word bigendiancpu =
+ (BigEndianCPU ? (mask ^ AccessLength_WORD) : 0);
+ unsigned int byte;
+ paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
+ byte = ((vaddr & mask) ^ bigendiancpu);
+ memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
+ StoreMemory (AccessLength_WORD, memval, memval1, paddr, vaddr,
+ isREAL);
+ }
+ }
+}
+:function:::void:do_trunc_fmt:int type, int fmt, int fd, int fs
+{
+ check_fpu (SD_);
+ StoreFPR (fd, type, Convert (FP_RM_TOZERO, ValueFPR (fs, fmt), fmt,
+ type));
+}
000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
"add r<RD>, r<RS>, r<RT>"
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
- if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
- Unpredictable ();
- TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
- {
- ALU32_BEGIN (GPR[RS]);
- ALU32_ADD (GPR[RT]);
- ALU32_END (GPR[RD]); /* This checks for overflow. */
- }
- TRACE_ALU_RESULT (GPR[RD]);
+ do_add (SD_, RS, RT, RD);
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
- if (NotWordValue (GPR[RS]))
- Unpredictable ();
- TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
- {
- ALU32_BEGIN (GPR[RS]);
- ALU32_ADD (EXTEND16 (IMMEDIATE));
- ALU32_END (GPR[RT]); /* This checks for overflow. */
- }
- TRACE_ALU_RESULT (GPR[RT]);
+ do_addi (SD_, RS, RT, IMMEDIATE);
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
- TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
- GPR[RT] = GPR[RS] & IMMEDIATE;
- TRACE_ALU_RESULT (GPR[RT]);
+ do_andi (SD_,RS, RT, IMMEDIATE);
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
else
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if ((signed_word) GPR[RS] >= 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if (RS == 31)
Unpredictable ();
RA = (CIA + 8);
if ((signed_word) GPR[RS] >= 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if (RS == 31)
Unpredictable ();
RA = (CIA + 8);
executed */
if ((signed_word) GPR[RS] >= 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
else
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if ((signed_word) GPR[RS] >= 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
else
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if ((signed_word) GPR[RS] > 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
/* NOTE: The branch occurs AFTER the next instruction has been
executed */
if ((signed_word) GPR[RS] > 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
else
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
/* NOTE: The branch occurs AFTER the next instruction has been
executed */
if ((signed_word) GPR[RS] <= 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if ((signed_word) GPR[RS] <= 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
else
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if ((signed_word) GPR[RS] < 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if (RS == 31)
Unpredictable ();
RA = (CIA + 8);
executed */
if ((signed_word) GPR[RS] < 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if (RS == 31)
Unpredictable ();
RA = (CIA + 8);
if ((signed_word) GPR[RS] < 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
else
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
/* NOTE: The branch occurs AFTER the next instruction has been
executed */
if ((signed_word) GPR[RS] < 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
else
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
else
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
- /* Check for some break instruction which are reserved for use by the simulator. */
- unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
- if (break_code == (HALT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
- break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
- {
- sim_engine_halt (SD, CPU, NULL, cia,
- sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
- }
- else if (break_code == (BREAKPOINT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
- break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
- {
- if (STATE & simDELAYSLOT)
- PC = cia - 4; /* reference the branch instruction */
- else
- PC = cia;
- SignalException (BreakPoint, instruction_0);
- }
-
- else
- {
- /* If we get this far, we're not an instruction reserved by the sim. Raise
- the exception. */
- SignalException (BreakPoint, instruction_0);
- }
+ do_break (SD_, instruction_0);
}
011100,5.RS,5.RT,5.RD,00000,100001:SPECIAL2:32::CLO
"clo r<RD>, r<RS>"
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
+*vr5500:
{
- unsigned32 temp = GPR[RS];
- unsigned32 i, mask;
if (RT != RD)
Unpredictable ();
- if (NotWordValue (GPR[RS]))
- Unpredictable ();
- TRACE_ALU_INPUT1 (GPR[RS]);
- for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
- {
- if ((temp & mask) == 0)
- break;
- mask >>= 1;
- }
- GPR[RD] = EXTEND32 (i);
- TRACE_ALU_RESULT (GPR[RD]);
+ do_clo (SD_, RD, RS);
}
011100,5.RS,5.RT,5.RD,00000,100000:SPECIAL2:32::CLZ
"clz r<RD>, r<RS>"
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
+*vr5500:
{
- unsigned32 temp = GPR[RS];
- unsigned32 i, mask;
if (RT != RD)
Unpredictable ();
- if (NotWordValue (GPR[RS]))
- Unpredictable ();
- TRACE_ALU_INPUT1 (GPR[RS]);
- for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
- {
- if ((temp & mask) != 0)
- break;
- mask >>= 1;
- }
- GPR[RD] = EXTEND32 (i);
- TRACE_ALU_RESULT (GPR[RD]);
+ do_clz (SD_, RD, RS);
}
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
check_u64 (SD_, instruction_0);
- TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
- {
- ALU64_BEGIN (GPR[RS]);
- ALU64_ADD (GPR[RT]);
- ALU64_END (GPR[RD]); /* This checks for overflow. */
- }
- TRACE_ALU_RESULT (GPR[RD]);
+ do_dadd (SD_, RD, RS, RT);
}
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
check_u64 (SD_, instruction_0);
- TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
- {
- ALU64_BEGIN (GPR[RS]);
- ALU64_ADD (EXTEND16 (IMMEDIATE));
- ALU64_END (GPR[RT]); /* This checks for overflow. */
- }
- TRACE_ALU_RESULT (GPR[RT]);
+ do_daddi (SD_, RT, RS, IMMEDIATE);
}
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO
"dclo r<RD>, r<RS>"
*mips64:
+*mips64r2:
+*vr5500:
{
- unsigned64 temp = GPR[RS];
- unsigned32 i;
- unsigned64 mask;
- check_u64 (SD_, instruction_0);
if (RT != RD)
Unpredictable ();
- TRACE_ALU_INPUT1 (GPR[RS]);
- for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
- {
- if ((temp & mask) == 0)
- break;
- mask >>= 1;
- }
- GPR[RD] = EXTEND32 (i);
- TRACE_ALU_RESULT (GPR[RD]);
+ check_u64 (SD_, instruction_0);
+ do_dclo (SD_, RD, RS);
}
011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ
"dclz r<RD>, r<RS>"
*mips64:
+*mips64r2:
+*vr5500:
{
- unsigned64 temp = GPR[RS];
- unsigned32 i;
- unsigned64 mask;
- check_u64 (SD_, instruction_0);
if (RT != RD)
Unpredictable ();
- TRACE_ALU_INPUT1 (GPR[RS]);
- for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
- {
- if ((temp & mask) != 0)
- break;
- mask >>= 1;
- }
- GPR[RD] = EXTEND32 (i);
- TRACE_ALU_RESULT (GPR[RD]);
+ check_u64 (SD_, instruction_0);
+ do_dclz (SD_, RD, RS);
}
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
do_ddivu (SD_, RS, RT);
}
-
-
:function:::void:do_div:int rs, int rt
{
check_div_hilo (SD_, HIHISTORY, LOHISTORY);
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
}
-
:function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
{
unsigned64 lo;
sign = 0;
if (signed_p)
{
- if (op1 < 0)
+ if ((signed64) op1 < 0)
{
op1 = - op1;
++sign;
}
- if (op2 < 0)
+ if ((signed64) op2 < 0)
{
op2 = - op2;
++sign;
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
{
check_u64 (SD_, instruction_0);
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
{
check_u64 (SD_, instruction_0);
do_dmultu (SD_, RS, RT, RD);
}
+
+:function:::unsigned64:do_dror:unsigned64 x,unsigned64 y
+{
+ unsigned64 result;
+
+ y &= 63;
+ TRACE_ALU_INPUT2 (x, y);
+ result = ROTR64 (x, y);
+ TRACE_ALU_RESULT (result);
+ return result;
+}
+
+000000,00001,5.RT,5.RD,5.SHIFT,111010::64::DROR
+"dror r<RD>, r<RT>, <SHIFT>"
+*mips64r2:
+*vr5400:
+*vr5500:
+{
+ check_u64 (SD_, instruction_0);
+ GPR[RD] = do_dror (SD_, GPR[RT], SHIFT);
+}
+
+000000,00001,5.RT,5.RD,5.SHIFT,111110::64::DROR32
+"dror32 r<RD>, r<RT>, <SHIFT>"
+*mips64r2:
+*vr5400:
+*vr5500:
+{
+ check_u64 (SD_, instruction_0);
+ GPR[RD] = do_dror (SD_, GPR[RT], SHIFT + 32);
+}
+
+000000,5.RS,5.RT,5.RD,00001,010110::64::DRORV
+"drorv r<RD>, r<RT>, r<RS>"
+*mips64r2:
+*vr5400:
+*vr5500:
+{
+ check_u64 (SD_, instruction_0);
+ GPR[RD] = do_dror (SD_, GPR[RT], GPR[RS]);
+}
+
+
:function:::void:do_dsll:int rt, int rd, int shift
{
TRACE_ALU_INPUT2 (GPR[rt], shift);
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
- int s = 32 + SHIFT;
check_u64 (SD_, instruction_0);
- TRACE_ALU_INPUT2 (GPR[RT], s);
- GPR[RD] = GPR[RT] << s;
- TRACE_ALU_RESULT (GPR[RD]);
+ do_dsll32 (SD_, RD, RT, SHIFT);
}
:function:::void:do_dsllv:int rs, int rt, int rd
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
- int s = 32 + SHIFT;
check_u64 (SD_, instruction_0);
- TRACE_ALU_INPUT2 (GPR[RT], s);
- GPR[RD] = ((signed64) GPR[RT]) >> s;
- TRACE_ALU_RESULT (GPR[RD]);
+ do_dsra32 (SD_, RD, RT, SHIFT);
}
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
- int s = 32 + SHIFT;
check_u64 (SD_, instruction_0);
- TRACE_ALU_INPUT2 (GPR[RT], s);
- GPR[RD] = (unsigned64) GPR[RT] >> s;
- TRACE_ALU_RESULT (GPR[RD]);
+ do_dsrl32 (SD_, RD, RT, SHIFT);
}
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
check_u64 (SD_, instruction_0);
- TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
- {
- ALU64_BEGIN (GPR[RS]);
- ALU64_SUB (GPR[RT]);
- ALU64_END (GPR[RD]); /* This checks for overflow. */
- }
- TRACE_ALU_RESULT (GPR[RD]);
+ do_dsub (SD_, RD, RS, RT);
}
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
DELAY_SLOT (temp);
}
+000000,5.RS,00000,5.RD,10000,001001:SPECIAL:32::JALR_HB
+"jalr.hb r<RS>":RD == 31
+"jalr.hb r<RD>, r<RS>"
+*mips32r2:
+*mips64r2:
+{
+ address_word temp = GPR[RS];
+ GPR[RD] = CIA + 8;
+ DELAY_SLOT (temp);
+}
-000000,5.RS,000000000000000,001000:SPECIAL:32::JR
+000000,5.RS,0000000000,00000,001000:SPECIAL:32::JR
"jr r<RS>"
*mipsI:
*mipsII:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
DELAY_SLOT (GPR[RS]);
}
+000000,5.RS,0000000000,10000,001000:SPECIAL:32::JR_HB
+"jr.hb r<RS>"
+*mips32r2:
+*mips64r2:
+{
+ DELAY_SLOT (GPR[RS]);
+}
:function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
{
address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
unsigned int byte;
address_word paddr;
- int uncached;
unsigned64 memval;
address_word vaddr;
- vaddr = loadstore_ea (SD_, base, offset);
+ paddr = vaddr = loadstore_ea (SD_, base, offset);
if ((vaddr & access) != 0)
{
SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
}
- AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
- LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
+ LoadMemory (&memval, NULL, access, paddr, vaddr, isDATA, isREAL);
byte = ((vaddr & mask) ^ bigendiancpu);
return (memval >> (8 * byte));
}
unsigned int byte;
unsigned int word;
address_word paddr;
- int uncached;
unsigned64 memval;
address_word vaddr;
int nr_lhs_bits;
unsigned_word lhs_mask;
unsigned_word temp;
- vaddr = loadstore_ea (SD_, base, offset);
- AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
+ paddr = vaddr = loadstore_ea (SD_, base, offset);
paddr = (paddr ^ (reverseendian & mask));
if (BigEndianMem == 0)
paddr = paddr & ~access;
(long) ((unsigned64) paddr >> 32), (long) paddr,
word, byte, nr_lhs_bits, nr_rhs_bits); */
- LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
+ LoadMemory (&memval, NULL, byte, paddr, vaddr, isDATA, isREAL);
if (word == 0)
{
/* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
unsigned int byte;
address_word paddr;
- int uncached;
unsigned64 memval;
address_word vaddr;
- vaddr = loadstore_ea (SD_, base, offset);
- AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
+ paddr = vaddr = loadstore_ea (SD_, base, offset);
/* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
paddr = (paddr ^ (reverseendian & mask));
if (BigEndianMem != 0)
paddr = paddr & ~access;
byte = ((vaddr & mask) ^ (bigendiancpu & mask));
/* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */
- LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
+ LoadMemory (&memval, NULL, access - (access & byte), paddr, vaddr, isDATA, isREAL);
/* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
(long) paddr, byte, (long) paddr, (long) memval); */
{
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
- GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
+ do_lb (SD_,RT,OFFSET,BASE);
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
- GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
+ do_lbu (SD_, RT,OFFSET,BASE);
}
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
- COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
+ do_ldc (SD_, ZZ, RT, OFFSET, BASE);
}
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
- GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
+ do_lh (SD_,RT,OFFSET,BASE);
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
- GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
+ do_lhu (SD_,RT,OFFSET,BASE);
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
- address_word base = GPR[BASE];
- address_word offset = EXTEND16 (OFFSET);
- {
- address_word vaddr = loadstore_ea (SD_, base, offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 3) != 0)
- {
- SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal);
- }
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int shift = 2;
- unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
- unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
- LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
- byte = ((vaddr & mask) ^ (bigend << shift));
- GPR[RT] = EXTEND32 (memval >> (8 * byte));
- LLBIT = 1;
- }
- }
- }
+ do_ll (SD_, RT, OFFSET, BASE);
}
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
- address_word base = GPR[BASE];
- address_word offset = EXTEND16 (OFFSET);
check_u64 (SD_, instruction_0);
- {
- address_word vaddr = loadstore_ea (SD_, base, offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 7) != 0)
- {
- SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal);
- }
- else
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
- GPR[RT] = memval;
- LLBIT = 1;
- }
- }
- }
+ do_lld (SD_, RT, OFFSET, BASE);
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
- TRACE_ALU_INPUT1 (IMMEDIATE);
- GPR[RT] = EXTEND32 (IMMEDIATE << 16);
- TRACE_ALU_RESULT (GPR[RT]);
+ do_lui (SD_, RT, IMMEDIATE);
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
- GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
+ do_lw (SD_,RT,OFFSET,BASE);
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
- COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
+ do_lwc (SD_, ZZ, RT, OFFSET, BASE);
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
- GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
+ do_lwl (SD_, RT, OFFSET, BASE);
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
- GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
+ do_lwr (SD_, RT, OFFSET, BASE);
}
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
- check_u64 (SD_, instruction_0);
- GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
+ do_lwu (SD_, RT, OFFSET, BASE, instruction_0);
}
"madd r<RS>, r<RT>"
*mips32:
*mips64:
+*vr5500:
{
- signed64 temp;
- check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
- if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
- Unpredictable ();
- TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
- temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
- + ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
- LO = EXTEND32 (temp);
- HI = EXTEND32 (VH4_8 (temp));
- TRACE_ALU_RESULT2 (HI, LO);
+ do_madd (SD_, RS, RT);
}
+011100,5.RS,5.RT,000,2.AC,00000,000000:SPECIAL2:32::MADD
+"madd r<RS>, r<RT>":AC == 0
+"madd ac<AC>, r<RS>, r<RT>"
+*mips32r2:
+*mips64r2:
+*dsp2:
+{
+ do_dsp_madd (SD_, AC, RS, RT);
+}
+
011100,5.RS,5.RT,00000,00000,000001:SPECIAL2:32::MADDU
"maddu r<RS>, r<RT>"
*mips32:
*mips64:
+*vr5500:
{
- unsigned64 temp;
- check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
- if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
- Unpredictable ();
- TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
- temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
- + ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
- LO = EXTEND32 (temp);
- HI = EXTEND32 (VH4_8 (temp));
- TRACE_ALU_RESULT2 (HI, LO);
+ do_maddu (SD_, RS, RT);
+}
+
+
+011100,5.RS,5.RT,000,2.AC,00000,000001:SPECIAL2:32::MADDU
+"maddu r<RS>, r<RT>":AC == 0
+"maddu ac<AC>, r<RS>, r<RT>"
+*mips32r2:
+*mips64r2:
+*dsp2:
+{
+ do_dsp_maddu (SD_, AC, RS, RT);
}
*mipsIII:
*mipsIV:
*mipsV:
-*mips32:
-*mips64:
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
do_mfhi (SD_, RD);
}
+000000,000,2.AC,00000,5.RD,00000,010000:SPECIAL:32::MFHI
+"mfhi r<RD>":AC == 0
+"mfhi r<RD>, ac<AC>"
+*mips32r2:
+*mips64r2:
+*dsp:
+{
+ do_dsp_mfhi (SD_, AC, RD);
+}
+
:function:::void:do_mflo:int rd
{
*mipsIII:
*mipsIV:
*mipsV:
-*mips32:
-*mips64:
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
do_mflo (SD_, RD);
}
+000000,000,2.AC,00000,5.RD,00000,010010:SPECIAL:32::MFLO
+"mflo r<RD>":AC == 0
+"mflo r<RD>, ac<AC>"
+*mips32r2:
+*mips64r2:
+*dsp:
+{
+ do_dsp_mflo (SD_, AC, RD);
+}
+
000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN
"movn r<RD>, r<RS>, r<RT>"
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr5000:
{
- if (GPR[RT] != 0)
- GPR[RD] = GPR[RS];
+ do_movn (SD_, RD, RS, RT);
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr5000:
{
- if (GPR[RT] == 0)
- GPR[RD] = GPR[RS];
+ do_movz (SD_, RD, RS, RT);
}
"msub r<RS>, r<RT>"
*mips32:
*mips64:
+*vr5500:
{
- signed64 temp;
- check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
- if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
- Unpredictable ();
- TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
- temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
- - ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
- LO = EXTEND32 (temp);
- HI = EXTEND32 (VH4_8 (temp));
- TRACE_ALU_RESULT2 (HI, LO);
+ do_msub (SD_, RS, RT);
}
+011100,5.RS,5.RT,000,2.AC,00000,000100:SPECIAL2:32::MSUB
+"msub r<RS>, r<RT>":AC == 0
+"msub ac<AC>, r<RS>, r<RT>"
+*mips32r2:
+*mips64r2:
+*dsp2:
+{
+ do_dsp_msub (SD_, AC, RS, RT);
+}
+
011100,5.RS,5.RT,00000,00000,000101:SPECIAL2:32::MSUBU
"msubu r<RS>, r<RT>"
*mips32:
*mips64:
+*vr5500:
{
- unsigned64 temp;
- check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
- if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
- Unpredictable ();
- TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
- temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
- - ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
- LO = EXTEND32 (temp);
- HI = EXTEND32 (VH4_8 (temp));
- TRACE_ALU_RESULT2 (HI, LO);
+ do_msubu (SD_, RS, RT);
}
+011100,5.RS,5.RT,000,2.AC,00000,000101:SPECIAL2:32::MSUBU
+"msubu r<RS>, r<RT>":AC == 0
+"msubu ac<AC>, r<RS>, r<RT>"
+*mips32r2:
+*mips64r2:
+*dsp2:
+{
+ do_dsp_msubu (SD_, AC, RS, RT);
+}
+
000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
"mthi r<RS>"
*mipsIII:
*mipsIV:
*mipsV:
-*mips32:
-*mips64:
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
- check_mt_hilo (SD_, HIHISTORY);
- HI = GPR[RS];
+ do_mthi (SD_, RS);
}
+000000,5.RS,00000,000,2.AC,00000,010001:SPECIAL:32::MTHI
+"mthi r<RS>":AC == 0
+"mthi r<RS>, ac<AC>"
+*mips32r2:
+*mips64r2:
+*dsp:
+{
+ do_dsp_mthi (SD_, AC, RS);
+}
+
000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO
"mtlo r<RS>"
*mipsIII:
*mipsIV:
*mipsV:
-*mips32:
-*mips64:
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
- check_mt_hilo (SD_, LOHISTORY);
- LO = GPR[RS];
+ do_mtlo (SD_, RS);
}
+000000,5.RS,00000,000,2.AC,00000,010011:SPECIAL:32::MTLO
+"mtlo r<RS>":AC == 0
+"mtlo r<RS>, ac<AC>"
+*mips32r2:
+*mips64r2:
+*dsp:
+{
+ do_dsp_mtlo (SD_, AC, RS);
+}
+
011100,5.RS,5.RT,5.RD,00000,000010:SPECIAL2:32::MUL
"mul r<RD>, r<RS>, r<RT>"
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
+*vr5500:
{
- signed64 prod;
- if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
- Unpredictable ();
- TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
- prod = (((signed64)(signed32) GPR[RS])
- * ((signed64)(signed32) GPR[RT]));
- GPR[RD] = EXTEND32 (VL4_8 (prod));
- TRACE_ALU_RESULT (GPR[RD]);
+ do_mul (SD_, RD, RS, RT);
}
* ((signed64)(signed32) GPR[rt]));
LO = EXTEND32 (VL4_8 (prod));
HI = EXTEND32 (VH4_8 (prod));
+ ACX = 0; /* SmartMIPS */
if (rd != 0)
GPR[rd] = LO;
TRACE_ALU_RESULT2 (HI, LO);
}
+000000,5.RS,5.RT,000,2.AC,00000,011000:SPECIAL:32::MULT
+"mult r<RS>, r<RT>":AC == 0
+"mult ac<AC>, r<RS>, r<RT>"
+*mips32r2:
+*mips64r2:
+*dsp2:
+{
+ do_dsp_mult (SD_, AC, RS, RT);
+}
+
+
000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT
"mult r<RS>, r<RT>":RD == 0
"mult r<RD>, r<RS>, r<RT>"
do_multu (SD_, RS, RT, 0);
}
+
+000000,5.RS,5.RT,000,2.AC,00000,011001:SPECIAL:32::MULTU
+"multu r<RS>, r<RT>":AC == 0
+"multu r<RS>, r<RT>"
+*mips32r2:
+*mips64r2:
+*dsp2:
+{
+ do_dsp_multu (SD_, AC, RS, RT);
+}
+
+
000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU
"multu r<RS>, r<RT>":RD == 0
"multu r<RD>, r<RS>, r<RT>"
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr5000:
{
- address_word base = GPR[BASE];
- address_word offset = EXTEND16 (OFFSET);
- {
- address_word vaddr = loadstore_ea (SD_, base, offset);
- address_word paddr;
- int uncached;
- {
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- Prefetch(uncached,paddr,vaddr,isDATA,HINT);
- }
- }
+ do_pref (SD_, HINT, OFFSET, BASE);
+}
+
+
+:function:::unsigned64:do_ror:unsigned32 x,unsigned32 y
+{
+ unsigned64 result;
+
+ y &= 31;
+ TRACE_ALU_INPUT2 (x, y);
+ result = EXTEND32 (ROTR32 (x, y));
+ TRACE_ALU_RESULT (result);
+ return result;
+}
+
+000000,00001,5.RT,5.RD,5.SHIFT,000010::32::ROR
+"ror r<RD>, r<RT>, <SHIFT>"
+*mips32r2:
+*mips64r2:
+*smartmips:
+*vr5400:
+*vr5500:
+{
+ GPR[RD] = do_ror (SD_, GPR[RT], SHIFT);
+}
+
+000000,5.RS,5.RT,5.RD,00001,000110::32::RORV
+"rorv r<RD>, r<RT>, r<RS>"
+*mips32r2:
+*mips64r2:
+*smartmips:
+*vr5400:
+*vr5500:
+{
+ GPR[RD] = do_ror (SD_, GPR[RT], GPR[RS]);
}
address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
unsigned int byte;
address_word paddr;
- int uncached;
unsigned64 memval;
address_word vaddr;
- vaddr = loadstore_ea (SD_, base, offset);
+ paddr = vaddr = loadstore_ea (SD_, base, offset);
if ((vaddr & access) != 0)
{
SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
}
- AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
byte = ((vaddr & mask) ^ bigendiancpu);
memval = (word << (8 * byte));
- StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
+ StoreMemory (access, memval, 0, paddr, vaddr, isREAL);
}
:function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
unsigned int byte;
unsigned int word;
address_word paddr;
- int uncached;
unsigned64 memval;
address_word vaddr;
int nr_lhs_bits;
int nr_rhs_bits;
- vaddr = loadstore_ea (SD_, base, offset);
- AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
+ paddr = vaddr = loadstore_ea (SD_, base, offset);
paddr = (paddr ^ (reverseendian & mask));
if (BigEndianMem == 0)
paddr = paddr & ~access;
/* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
(long) ((unsigned64) rt >> 32), (long) rt,
(long) ((unsigned64) memval >> 32), (long) memval); */
- StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
+ StoreMemory (byte, memval, 0, paddr, vaddr, isREAL);
}
:function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
unsigned int byte;
address_word paddr;
- int uncached;
unsigned64 memval;
address_word vaddr;
- vaddr = loadstore_ea (SD_, base, offset);
- AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
+ paddr = vaddr = loadstore_ea (SD_, base, offset);
paddr = (paddr ^ (reverseendian & mask));
if (BigEndianMem != 0)
paddr &= ~access;
byte = ((vaddr & mask) ^ (bigendiancpu & mask));
memval = (rt << (byte * 8));
- StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
+ StoreMemory (access - (access & byte), memval, 0, paddr, vaddr, isREAL);
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
- unsigned32 instruction = instruction_0;
- address_word base = GPR[BASE];
- address_word offset = EXTEND16 (OFFSET);
- {
- address_word vaddr = loadstore_ea (SD_, base, offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 3) != 0)
- {
- SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
- }
- else
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
- byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
- memval = ((unsigned64) GPR[RT] << (8 * byte));
- if (LLBIT)
- {
- StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
- }
- GPR[RT] = LLBIT;
- }
- }
- }
+ do_sc (SD_, RT, OFFSET, BASE, instruction_0);
}
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
- address_word base = GPR[BASE];
- address_word offset = EXTEND16 (OFFSET);
check_u64 (SD_, instruction_0);
- {
- address_word vaddr = loadstore_ea (SD_, base, offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 7) != 0)
- {
- SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal);
- }
- else
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- memval = GPR[RT];
- if (LLBIT)
- {
- StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
- }
- GPR[RT] = LLBIT;
- }
- }
- }
+ do_scd (SD_, RT, OFFSET, BASE);
}
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
}
+
101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
"sh r<RT>, <OFFSET>(r<BASE>)"
*mipsI:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
"ssnop":RD == 0 && RT == 0 && SHIFT == 1
"sll r<RD>, r<RT>, <SHIFT>"
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
{
/* Skip shift for NOP and SSNOP, so that there won't be lots of
extraneous trace output. */
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
- if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
- Unpredictable ();
- TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
- {
- ALU32_BEGIN (GPR[RS]);
- ALU32_SUB (GPR[RT]);
- ALU32_END (GPR[RD]); /* This checks for overflow. */
- }
- TRACE_ALU_RESULT (GPR[RD]);
+ do_sub (SD_, RD, RS, RT);
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*r3900:
*vr5000:
{
- do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
+ do_sw (SD_, RT, OFFSET, BASE);
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
- if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
- SignalException (Trap, instruction_0);
+ do_teq (SD_, RS, RT, instruction_0);
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
- if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
- SignalException (Trap, instruction_0);
+ do_teqi (SD_, RS, IMMEDIATE, instruction_0);
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
- if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
- SignalException (Trap, instruction_0);
+ do_tge (SD_, RS, RT, instruction_0);
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
- if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
- SignalException (Trap, instruction_0);
+ do_tgei (SD_, RS, IMMEDIATE, instruction_0);
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
- if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
- SignalException (Trap, instruction_0);
+ do_tgeiu (SD_, RS, IMMEDIATE, instruction_0);
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
- if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
- SignalException (Trap, instruction_0);
+ do_tgeu (SD_, RS, RT, instruction_0);
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
- if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
- SignalException (Trap, instruction_0);
+ do_tlt (SD_, RS, RT, instruction_0);
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
- if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
- SignalException (Trap, instruction_0);
+ do_tlti (SD_, RS, IMMEDIATE, instruction_0);
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
- if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
- SignalException (Trap, instruction_0);
+ do_tltiu (SD_, RS, IMMEDIATE, instruction_0);
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
- if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
- SignalException (Trap, instruction_0);
+ do_tltu (SD_, RS, RT, instruction_0);
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
- if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
- SignalException (Trap, instruction_0);
+ do_tne (SD_, RS, RT, instruction_0);
}
000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
-"tne r<RS>, <IMMEDIATE>"
+"tnei r<RS>, <IMMEDIATE>"
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
- if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
- SignalException (Trap, instruction_0);
+ do_tnei (SD_, RS, IMMEDIATE, instruction_0);
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
case fmt_double: return "d";
case fmt_word: return "w";
case fmt_long: return "l";
- default: return "?";
- }
-}
-
-:%s::::X:int x
-{
- switch (x)
- {
- case 0: return "f";
- case 1: return "t";
+ case fmt_ps: return "ps";
default: return "?";
}
}
// ReservedInstruction exception if not.
//
-// check_fmt checks that the format is single or double.
-:function:::void:check_fmt:int fmt, instruction_word insn
+// check_fmt_p checks that the format is single, double, or paired single.
+:function:::void:check_fmt_p:int fmt, instruction_word insn
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-*mipsV:
*mips32:
-*mips64:
*vr4100:
*vr5000:
*r3900:
{
+ /* None of these ISAs support Paired Single, so just fall back to
+ the single/double check. */
if ((fmt != fmt_single) && (fmt != fmt_double))
SignalException (ReservedInstruction, insn);
}
-// check_fmt_p checks that the format is single, double, or paired single.
:function:::void:check_fmt_p:int fmt, instruction_word insn
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mips32:
-*vr4100:
-*vr5000:
-*r3900:
+*mips32r2:
+*micromips32:
{
- /* None of these ISAs support Paired Single, so just fall back to
- the single/double check. */
- check_fmt (SD_, fmt, insn);
+ if ((fmt != fmt_single) && (fmt != fmt_double) && (fmt != fmt_ps))
+ SignalException (ReservedInstruction, insn);
}
:function:::void:check_fmt_p:int fmt, instruction_word insn
*mipsV:
*mips64:
+*mips64r2:
+*micromips64:
{
-#if 0 /* XXX FIXME: FP code doesn't yet support paired single ops. */
if ((fmt != fmt_single) && (fmt != fmt_double)
&& (fmt != fmt_ps || (UserMode && (SR & (status_UX|status_PX)) == 0)))
SignalException (ReservedInstruction, insn);
-#else
- check_fmt (SD_, fmt, insn);
-#endif
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
+*micromips32:
+*micromips64:
{
if (! COP_Usable (1))
SignalExceptionCoProcessorUnusable (1);
}
-010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
+// Helper:
+//
+// Load a double word FP value using 2 32-bit memory cycles a la MIPS II
+// or MIPS32. do_load cannot be used instead because it returns an
+// unsigned_word, which is limited to the size of the machine's registers.
+//
+
+:function:::unsigned64:do_load_double:address_word base, address_word offset
+*mipsII:
+*mips32:
+*mips32r2:
+*micromips32:
+{
+ int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
+ address_word vaddr;
+ address_word paddr;
+ unsigned64 memval;
+ unsigned64 v;
+
+ paddr = vaddr = loadstore_ea (SD_, base, offset);
+ if ((vaddr & AccessLength_DOUBLEWORD) != 0)
+ {
+ SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map,
+ AccessLength_DOUBLEWORD + 1, vaddr, read_transfer,
+ sim_core_unaligned_signal);
+ }
+ LoadMemory (&memval, NULL, AccessLength_WORD, paddr, vaddr, isDATA, isREAL);
+ v = (unsigned64)memval;
+ LoadMemory (&memval, NULL, AccessLength_WORD, paddr + 4, vaddr + 4, isDATA,
+ isREAL);
+ return (bigendian ? ((v << 32) | memval) : (v | (memval << 32)));
+}
+
+
+// Helper:
+//
+// Store a double word FP value using 2 32-bit memory cycles a la MIPS II
+// or MIPS32. do_load cannot be used instead because it returns an
+// unsigned_word, which is limited to the size of the machine's registers.
+//
+
+:function:::void:do_store_double:address_word base, address_word offset, unsigned64 v
+*mipsII:
+*mips32:
+*mips32r2:
+*micromips32:
+{
+ int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
+ address_word vaddr;
+ address_word paddr;
+ unsigned64 memval;
+
+ paddr = vaddr = loadstore_ea (SD_, base, offset);
+ if ((vaddr & AccessLength_DOUBLEWORD) != 0)
+ {
+ SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map,
+ AccessLength_DOUBLEWORD + 1, vaddr, write_transfer,
+ sim_core_unaligned_signal);
+ }
+ memval = (bigendian ? (v >> 32) : (v & 0xFFFFFFFF));
+ StoreMemory (AccessLength_WORD, memval, 0, paddr, vaddr, isREAL);
+ memval = (bigendian ? (v & 0xFFFFFFFF) : (v >> 32));
+ StoreMemory (AccessLength_WORD, memval, 0, paddr + 4, vaddr + 4, isREAL);
+}
+
+
+010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
"abs.%s<FMT> f<FD>, f<FS>"
*mipsI:
*mipsII:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
- int fmt = FMT;
- check_fpu (SD_);
- check_fmt_p (SD_, fmt, instruction_0);
- StoreFPR(FD,fmt,AbsoluteValue(ValueFPR(FS,fmt),fmt));
+ do_abs_fmt (SD_, FMT, FD, FS, instruction_0);
}
-010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
+010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
"add.%s<FMT> f<FD>, f<FS>, f<FT>"
*mipsI:
*mipsII:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
- int fmt = FMT;
- check_fpu (SD_);
- check_fmt_p (SD_, fmt, instruction_0);
- StoreFPR(FD,fmt,Add(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt));
+ do_add_fmt (SD_, FMT, FD, FS, FT, instruction_0);
}
+010011,5.RS,5.FT,5.FS,5.FD,011,110:COP1X:32,f::ALNV.PS
+"alnv.ps f<FD>, f<FS>, f<FT>, r<RS>"
+*mipsV:
+*mips32r2:
+*mips64:
+*mips64r2:
+{
+ do_alnv_ps (SD_, FD, FS, FT, RS, instruction_0);
+}
+
// BC1F
// BC1FL
*mipsIII:
{
check_fpu (SD_);
- check_branch_bug ();
TRACE_BRANCH_INPUT (PREVCOC1());
if (PREVCOC1() == TF)
{
address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
TRACE_BRANCH_RESULT (dest);
- mark_branch_bug (dest);
DELAY_SLOT (dest);
}
else if (ND)
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
#*vr4100:
*vr5000:
*r3900:
{
check_fpu (SD_);
- check_branch_bug ();
if (GETFCC(CC) == TF)
{
address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
- mark_branch_bug (dest);
DELAY_SLOT (dest);
}
else if (ND)
}
-
-
-
-
-// C.EQ.S
-// C.EQ.D
-// ...
-
-:function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn
-{
- int less;
- int equal;
- int unordered;
- int condition;
- unsigned64 ofs = ValueFPR (fs, fmt);
- unsigned64 oft = ValueFPR (ft, fmt);
- if (NaN (ofs, fmt) || NaN (oft, fmt))
- {
- if (FCSR & FP_ENABLE (IO))
- {
- FCSR |= FP_CAUSE (IO);
- SignalExceptionFPE ();
- }
- less = 0;
- equal = 0;
- unordered = 1;
- }
- else
- {
- less = Less (ofs, oft, fmt);
- equal = Equal (ofs, oft, fmt);
- unordered = 0;
- }
- condition = (((cond & (1 << 2)) && less)
- || ((cond & (1 << 1)) && equal)
- || ((cond & (1 << 0)) && unordered));
- SETFCC (cc, condition);
-}
-
-010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32,f::C.cond.fmta
+010001,10,3.FMT!2!3!4!5!6!7,5.FT,5.FS,3.0,00,11,4.COND:COP1:32,f::C.cond.fmta
"c.%s<COND>.%s<FMT> f<FS>, f<FT>"
*mipsI:
*mipsII:
{
int fmt = FMT;
check_fpu (SD_);
- check_fmt_p (SD_, fmt, instruction_0);
- do_c_cond_fmt (SD_, fmt, FT, FS, 0, COND, instruction_0);
+ Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, 0);
+ TRACE_ALU_RESULT (ValueFCR (31));
}
-010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32,f::C.cond.fmtb
+010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32,f::C.cond.fmtb
"c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
"c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
- int fmt = FMT;
- check_fpu (SD_);
- check_fmt_p (SD_, fmt, instruction_0);
- do_c_cond_fmt (SD_, fmt, FT, FS, CC, COND, instruction_0);
+ do_c_cond_fmt (SD_, COND, FMT, CC, FS, FT, instruction_0);
}
-010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64,f::CEIL.L.fmt
+010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001010:COP1:32,f::CEIL.L.fmt
"ceil.l.%s<FMT> f<FD>, f<FS>"
*mipsIII:
*mipsIV:
*mipsV:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
- int fmt = FMT;
- check_fpu (SD_);
- check_fmt (SD_, fmt, instruction_0);
- StoreFPR(FD,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(FS,fmt),fmt,fmt_long));
+ do_ceil_fmt (SD_, fmt_long, FMT, FD, FS, instruction_0);
}
-010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32,f::CEIL.W
+010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001110:COP1:32,f::CEIL.W
+"ceil.w.%s<FMT> f<FD>, f<FS>"
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
- int fmt = FMT;
- check_fpu (SD_);
- check_fmt (SD_, fmt, instruction_0);
- StoreFPR(FD,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(FS,fmt),fmt,fmt_word));
+ do_ceil_fmt (SD_, fmt_word, FMT, FD, FS, instruction_0);
}
-// CFC1
-// CTC1
-010001,00,X,10,5.RT,5.FS,00000000000:COP1Sa:32,f::CxC1
-"c%s<X>c1 r<RT>, f<FS>"
+010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1a
+"cfc1 r<RT>, f<FS>"
*mipsI:
*mipsII:
*mipsIII:
{
check_fpu (SD_);
- if (X)
+ if (FS == 0)
+ PENDING_FILL (RT, EXTEND32 (FCR0));
+ else if (FS == 31)
+ PENDING_FILL (RT, EXTEND32 (FCR31));
+ /* else NOP */
+}
+
+010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1b
+"cfc1 r<RT>, f<FS>"
+*mipsIV:
+*vr4100:
+*vr5000:
+*r3900:
+{
+ check_fpu (SD_);
+ if (FS == 0 || FS == 31)
{
- if (FS == 0)
- PENDING_FILL(FCR0IDX,VL4_8(GPR[RT]));
- else if (FS == 31)
- PENDING_FILL(FCR31IDX,VL4_8(GPR[RT]));
- /* else NOP */
- PENDING_SCHED(FCSR, FCR31 & (1<<23), 1, 23);
- }
- else
- { /* control from */
- if (FS == 0)
- PENDING_FILL(RT, EXTEND32 (FCR0));
- else if (FS == 31)
- PENDING_FILL(RT, EXTEND32 (FCR31));
- /* else NOP */
+ unsigned_word fcr = ValueFCR (FS);
+ TRACE_ALU_INPUT1 (fcr);
+ GPR[RT] = fcr;
}
+ /* else NOP */
+ TRACE_ALU_RESULT (GPR[RT]);
}
-010001,00,X,10,5.RT,5.FS,00000000000:COP1Sb:32,f::CxC1
-"c%s<X>c1 r<RT>, f<FS>"
-*mipsIV:
+
+010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1c
+"cfc1 r<RT>, f<FS>"
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
+{
+ do_cfc1 (SD_, RT, FS);
+}
+
+010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1a
+"ctc1 r<RT>, f<FS>"
+*mipsI:
+*mipsII:
+*mipsIII:
+{
+ check_fpu (SD_);
+ if (FS == 31)
+ PENDING_FILL (FCRCS_REGNUM, VL4_8 (GPR[RT]));
+ /* else NOP */
+}
+
+010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1b
+"ctc1 r<RT>, f<FS>"
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
{
check_fpu (SD_);
- if (X)
- {
- /* control to */
- TRACE_ALU_INPUT1 (GPR[RT]);
- if (FS == 0)
- {
- FCR0 = VL4_8(GPR[RT]);
- TRACE_ALU_RESULT (FCR0);
- }
- else if (FS == 31)
- {
- FCR31 = VL4_8(GPR[RT]);
- SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
- TRACE_ALU_RESULT (FCR31);
- }
- else
- {
- TRACE_ALU_RESULT0 ();
- }
- /* else NOP */
- }
- else
- { /* control from */
- if (FS == 0)
- {
- TRACE_ALU_INPUT1 (FCR0);
- GPR[RT] = EXTEND32 (FCR0);
- }
- else if (FS == 31)
- {
- TRACE_ALU_INPUT1 (FCR31);
- GPR[RT] = EXTEND32 (FCR31);
- }
- TRACE_ALU_RESULT (GPR[RT]);
- /* else NOP */
- }
+ TRACE_ALU_INPUT1 (GPR[RT]);
+ if (FS == 31)
+ StoreFCR (FS, GPR[RT]);
+ /* else NOP */
+}
+
+010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1c
+"ctc1 r<RT>, f<FS>"
+*mipsV:
+*mips32:
+*mips32r2:
+*mips64:
+*mips64r2:
+{
+ do_ctc1 (SD_, RT, FS);
}
//
// FIXME: Does not correctly differentiate between mips*
//
-010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32,f::CVT.D.fmt
+010001,10,3.FMT!1!2!3!6!7,00000,5.FS,5.FD,100001:COP1:32,f::CVT.D.fmt
"cvt.d.%s<FMT> f<FD>, f<FS>"
*mipsI:
*mipsII:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
- int fmt = FMT;
- check_fpu (SD_);
- {
- if ((fmt == fmt_double) | 0)
- SignalException (ReservedInstruction, instruction_0);
- else
- StoreFPR(FD,fmt_double,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_double));
- }
+ do_cvt_d_fmt (SD_, FMT, FD, FS, instruction_0);
}
-010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64,f::CVT.L.fmt
+010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100101:COP1:32,f::CVT.L.fmt
"cvt.l.%s<FMT> f<FD>, f<FS>"
*mipsIII:
*mipsIV:
*mipsV:
+*mips32r2:
+*mips64:
+*mips64r2:
+*vr4100:
+*vr5000:
+*r3900:
+{
+ do_cvt_l_fmt (SD_, FMT, FD, FS, instruction_0);
+}
+
+
+010001,10,000,5.FT,5.FS,5.FD,100110:COP1:32,f::CVT.PS.S
+"cvt.ps.s f<FD>, f<FS>, f<FT>"
+*mipsV:
+*mips32r2:
+*mips64:
+*mips64r2:
+{
+ do_cvt_ps_s (SD_, FD, FS, FT, instruction_0);
+}
+
+
+//
+// FIXME: Does not correctly differentiate between mips*
+//
+010001,10,3.FMT!0!2!3!6!7,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt
+"cvt.s.%s<FMT> f<FD>, f<FS>"
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
+*mips32:
+*mips32r2:
+*mips64:
+*mips64r2:
+*vr4100:
+*vr5000:
+*r3900:
+{
+ do_cvt_s_fmt (SD_, FMT, FD, FS, instruction_0);
+}
+
+
+010001,10,110,00000,5.FS,5.FD,101000:COP1:32,f::CVT.S.PL
+"cvt.s.pl f<FD>, f<FS>"
+*mipsV:
+*mips32r2:
+*mips64:
+*mips64r2:
+{
+ do_cvt_s_pl (SD_, FD, FS, instruction_0);
+}
+
+
+010001,10,110,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.PU
+"cvt.s.pu f<FD>, f<FS>"
+*mipsV:
+*mips32r2:
*mips64:
-*vr4100:
-*vr5000:
-*r3900:
+*mips64r2:
{
- int fmt = FMT;
- check_fpu (SD_);
- {
- if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word)))
- SignalException (ReservedInstruction, instruction_0);
- else
- StoreFPR(FD,fmt_long,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_long));
- }
+ do_cvt_s_pu (SD_, FD, FS, instruction_0);
}
-//
-// FIXME: Does not correctly differentiate between mips*
-//
-010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt
-"cvt.s.%s<FMT> f<FD>, f<FS>"
+010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt
+"cvt.w.%s<FMT> f<FD>, f<FS>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
- int fmt = FMT;
- check_fpu (SD_);
- {
- if ((fmt == fmt_single) | 0)
- SignalException (ReservedInstruction, instruction_0);
- else
- StoreFPR(FD,fmt_single,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_single));
- }
+ do_cvt_w_fmt (SD_, FMT, FD, FS, instruction_0);
}
-010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt
-"cvt.w.%s<FMT> f<FD>, f<FS>"
+010001,10,3.FMT!2!3!4!5!6!7,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.fmt
+"div.%s<FMT> f<FD>, f<FS>, f<FT>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
- int fmt = FMT;
- check_fpu (SD_);
- {
- if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word)))
- SignalException (ReservedInstruction, instruction_0);
- else
- StoreFPR(FD,fmt_word,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_word));
- }
+ do_div_fmt (SD_, FMT, FD, FS, FT, instruction_0);
}
-010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.fmt
-"div.%s<FMT> f<FD>, f<FS>, f<FT>"
-*mipsI:
-*mipsII:
+010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1a
+"dmfc1 r<RT>, f<FS>"
*mipsIII:
+{
+ unsigned64 v;
+ check_fpu (SD_);
+ check_u64 (SD_, instruction_0);
+ if (SizeFGR () == 64)
+ v = FGR[FS];
+ else if ((FS & 0x1) == 0)
+ v = SET64HI (FGR[FS+1]) | FGR[FS];
+ else
+ v = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
+ PENDING_FILL (RT, v);
+ TRACE_ALU_RESULT (v);
+}
+
+010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1b
+"dmfc1 r<RT>, f<FS>"
*mipsIV:
*mipsV:
-*mips32:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
- int fmt = FMT;
check_fpu (SD_);
- check_fmt (SD_, fmt, instruction_0);
- StoreFPR(FD,fmt,Divide(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt));
+ check_u64 (SD_, instruction_0);
+ do_dmfc1b (SD_, RT, FS);
}
-// DMFC1
-// DMTC1
-010001,00,X,01,5.RT,5.FS,00000000000:COP1Sa:64,f::DMxC1
-"dm%s<X>c1 r<RT>, f<FS>"
+010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1a
+"dmtc1 r<RT>, f<FS>"
*mipsIII:
{
+ unsigned64 v;
check_fpu (SD_);
check_u64 (SD_, instruction_0);
- if (X)
+ if (SizeFGR () == 64)
+ PENDING_FILL ((FS + FGR_BASE), GPR[RT]);
+ else if ((FS & 0x1) == 0)
{
- if (SizeFGR() == 64)
- PENDING_FILL((FS + FGRIDX),GPR[RT]);
- else if ((FS & 0x1) == 0)
- {
- PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT]));
- PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT]));
- }
+ PENDING_FILL (((FS + 1) + FGR_BASE), VH4_8 (GPR[RT]));
+ PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
}
else
- {
- if (SizeFGR() == 64)
- PENDING_FILL(RT,FGR[FS]);
- else if ((FS & 0x1) == 0)
- PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
- else
- {
- if (STATE_VERBOSE_P(SD))
- sim_io_eprintf (SD,
- "Warning: PC 0x%lx: semantic_DMxC1_COP1Sa 32-bit use of odd FPR number\n",
- (long) CIA);
- PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
- }
- }
+ Unpredictable ();
+ TRACE_FP_RESULT (GPR[RT]);
}
-010001,00,X,01,5.RT,5.FS,00000000000:COP1Sb:64,f::DMxC1
-"dm%s<X>c1 r<RT>, f<FS>"
+
+010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1b
+"dmtc1 r<RT>, f<FS>"
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
check_fpu (SD_);
check_u64 (SD_, instruction_0);
- if (X)
- {
- if (SizeFGR() == 64)
- StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
- else if ((FS & 0x1) == 0)
- StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]);
- }
- else
- {
- if (SizeFGR() == 64)
- GPR[RT] = FGR[FS];
- else if ((FS & 0x1) == 0)
- GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
- else
- {
- if (STATE_VERBOSE_P(SD))
- sim_io_eprintf (SD,
- "Warning: PC 0x%lx: DMxC1 32-bit use of odd FPR number\n",
- (long) CIA);
- GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
- }
- }
+ do_dmtc1b (SD_, RT, FS);
}
-010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64,f::FLOOR.L.fmt
+010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001011:COP1:32,f::FLOOR.L.fmt
"floor.l.%s<FMT> f<FD>, f<FS>"
*mipsIII:
*mipsIV:
*mipsV:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
- int fmt = FMT;
- check_fpu (SD_);
- check_fmt (SD_, fmt, instruction_0);
- StoreFPR(FD,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(FS,fmt),fmt,fmt_long));
+ do_floor_fmt (SD_, fmt_long, FMT, FD, FS);
}
-010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32,f::FLOOR.W.fmt
+010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001111:COP1:32,f::FLOOR.W.fmt
"floor.w.%s<FMT> f<FD>, f<FS>"
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
- int fmt = FMT;
- check_fpu (SD_);
- check_fmt (SD_, fmt, instruction_0);
- StoreFPR(FD,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(FS,fmt),fmt,fmt_word));
+ do_floor_fmt (SD_, fmt_word, FMT, FD, FS);
}
-110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1
+110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1a
"ldc1 f<FT>, <OFFSET>(r<BASE>)"
*mipsII:
+*mips32:
+*mips32r2:
+{
+ check_fpu (SD_);
+ COP_LD (1, FT, do_load_double (SD_, GPR[BASE], EXTEND16 (OFFSET)));
+}
+
+
+110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1b
+"ldc1 f<FT>, <OFFSET>(r<BASE>)"
*mipsIII:
*mipsIV:
*mipsV:
-*mips32:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
}
+010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:32,f::LDXC1
+"ldxc1 f<FD>, r<INDEX>(r<BASE>)"
+*mips32r2:
+{
+ check_fpu (SD_);
+ COP_LD (1, FD, do_load_double (SD_, GPR[BASE], GPR[INDEX]));
+}
+
+
010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64,f::LDXC1
"ldxc1 f<FD>, r<INDEX>(r<BASE>)"
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr5000:
{
check_fpu (SD_);
}
+010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:32,f::LUXC1
+"luxc1 f<FD>, r<INDEX>(r<BASE>)"
+*mips32r2:
+{
+ do_luxc1_32 (SD_, FD, INDEX, BASE);
+}
+
+
+010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:64,f::LUXC1
+"luxc1 f<FD>, r<INDEX>(r<BASE>)"
+*mipsV:
+*mips64:
+*mips64r2:
+{
+ check_fpu (SD_);
+ check_u64 (SD_, instruction_0);
+ do_luxc1_64 (SD_, FD, INDEX, BASE);
+}
+
110001,5.BASE,5.FT,16.OFFSET:COP1:32,f::LWC1
"lwc1 f<FT>, <OFFSET>(r<BASE>)"
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
- check_fpu (SD_);
- COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
+ do_lwc1 (SD_, FT, OFFSET, BASE);
}
-010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:64,f::LWXC1
+010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32,f::LWXC1
"lwxc1 f<FD>, r<INDEX>(r<BASE>)"
*mipsIV:
*mipsV:
+*mips32r2:
*mips64:
+*mips64r2:
*vr5000:
{
- check_fpu (SD_);
- check_u64 (SD_, instruction_0);
- COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
+ do_lwxc1 (SD_, FD, INDEX, BASE, instruction_0);
}
-//
-// FIXME: Not correct for mips*
-//
-010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
-"madd.d f<FD>, f<FR>, f<FS>, f<FT>"
-*mipsIV:
-*mipsV:
-*mips64:
-*vr5000:
-{
- check_fpu (SD_);
- {
- StoreFPR(FD,fmt_double,Add(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double));
- }
-}
-
-
-010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
-"madd.s f<FD>, f<FR>, f<FS>, f<FT>"
+010011,5.FR,5.FT,5.FS,5.FD,100,3.FMT!2!3!4!5!7:COP1X:32,f::MADD.fmt
+"madd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
*mipsV:
+*mips32r2:
*mips64:
+*mips64r2:
*vr5000:
{
- check_fpu (SD_);
- {
- StoreFPR(FD,fmt_single,Add(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single));
- }
+ do_madd_fmt (SD_, FMT, FD, FR, FS, FT, instruction_0);
}
-// MFC1
-// MTC1
-010001,00,X,00,5.RT,5.FS,00000000000:COP1Sa:32,f::MxC1
-"m%s<X>c1 r<RT>, f<FS>"
+010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1a
+"mfc1 r<RT>, f<FS>"
*mipsI:
*mipsII:
*mipsIII:
{
+ unsigned64 v;
check_fpu (SD_);
- if (X)
- { /*MTC1*/
- if (SizeFGR() == 64)
- {
- if (STATE_VERBOSE_P(SD))
- sim_io_eprintf (SD,
- "Warning: PC 0x%lx: MTC1 not DMTC1 with 64 bit regs\n",
- (long) CIA);
- PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
- }
- else
- PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
- }
- else /*MFC1*/
- PENDING_FILL (RT, EXTEND32 (FGR[FS]));
+ v = EXTEND32 (FGR[FS]);
+ PENDING_FILL (RT, v);
+ TRACE_ALU_RESULT (v);
}
-010001,00,X,00,5.RT,5.FS,00000000000:COP1Sb:32,f::MxC1
-"m%s<X>c1 r<RT>, f<FS>"
+
+010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1b
+"mfc1 r<RT>, f<FS>"
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
-{
- int fs = FS;
- check_fpu (SD_);
- if (X)
- /*MTC1*/
- StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
- else /*MFC1*/
- GPR[RT] = EXTEND32 (FGR[FS]);
+{
+ do_mfc1b (SD_, RT, FS);
}
-010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32,f::MOV.fmt
+010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000110:COP1:32,f::MOV.fmt
"mov.%s<FMT> f<FD>, f<FS>"
*mipsI:
*mipsII:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
- int fmt = FMT;
- check_fpu (SD_);
- check_fmt_p (SD_, fmt, instruction_0);
- StoreFPR(FD,fmt,ValueFPR(FS,fmt));
+ do_mov_fmt (SD_, FMT, FD, FS, instruction_0);
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr5000:
{
- check_fpu (SD_);
- if (GETFCC(CC) == TF)
- GPR[RD] = GPR[RS];
+ do_movtf (SD_, TF, RD, RS, CC);
}
// MOVF.fmt
// MOVT.fmt
-010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32,f::MOVtf.fmt
+010001,10,3.FMT!2!3!4!5!7,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32,f::MOVtf.fmt
"mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr5000:
{
- int fmt = FMT;
- check_fpu (SD_);
- {
- if (GETFCC(CC) == TF)
- StoreFPR (FD, fmt, ValueFPR (FS, fmt));
- else
- StoreFPR (FD, fmt, ValueFPR (FD, fmt));
- }
+ do_movtf_fmt (SD_, TF, FMT, FD, FS, CC);
}
-010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32,f::MOVN.fmt
+010001,10,3.FMT!2!3!4!5!7,5.RT,5.FS,5.FD,010011:COP1:32,f::MOVN.fmt
"movn.%s<FMT> f<FD>, f<FS>, r<RT>"
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr5000:
{
- check_fpu (SD_);
- if (GPR[RT] != 0)
- StoreFPR (FD, FMT, ValueFPR (FS, FMT));
- else
- StoreFPR (FD, FMT, ValueFPR (FD, FMT));
+ do_movn_fmt (SD_, FMT, FD, FS, RT);
}
-010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32,f::MOVZ.fmt
+010001,10,3.FMT!2!3!4!5!7,5.RT,5.FS,5.FD,010010:COP1:32,f::MOVZ.fmt
"movz.%s<FMT> f<FD>, f<FS>, r<RT>"
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr5000:
{
- check_fpu (SD_);
- if (GPR[RT] == 0)
- StoreFPR (FD, FMT, ValueFPR (FS, FMT));
- else
- StoreFPR (FD, FMT, ValueFPR (FD, FMT));
+ do_movz_fmt (SD_, FMT, FD, FS, RT);
}
-// MSUB.fmt
-010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32,f::MSUB.D
-"msub.d f<FD>, f<FR>, f<FS>, f<FT>"
+010011,5.FR,5.FT,5.FS,5.FD,101,3.FMT!2!3!4!5!7:COP1X:32,f::MSUB.fmt
+"msub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
*mipsV:
+*mips32r2:
*mips64:
+*mips64r2:
*vr5000:
{
- check_fpu (SD_);
- StoreFPR(FD,fmt_double,Sub(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double));
+ do_msub_fmt (SD_, FMT, FD, FR, FS, FT, instruction_0);
}
-// MSUB.fmt
-010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32,f::MSUB.S
-"msub.s f<FD>, f<FR>, f<FS>, f<FT>"
+010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1a
+"mtc1 r<RT>, f<FS>"
+*mipsI:
+*mipsII:
+*mipsIII:
+{
+ check_fpu (SD_);
+ if (SizeFGR () == 64)
+ PENDING_FILL ((FS + FGR_BASE), (SET64HI (0xDEADC0DE) | VL4_8 (GPR[RT])));
+ else
+ PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
+ TRACE_FP_RESULT (GPR[RT]);
+}
+
+010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1b
+"mtc1 r<RT>, f<FS>"
*mipsIV:
*mipsV:
+*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
+*vr4100:
*vr5000:
+*r3900:
{
- check_fpu (SD_);
- StoreFPR(FD,fmt_single,Sub(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single));
+ do_mtc1b (SD_, RT, FS);
}
-// MTC1 see MxC1
-
-
-010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt
+010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt
"mul.%s<FMT> f<FD>, f<FS>, f<FT>"
*mipsI:
*mipsII:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
- int fmt = FMT;
- check_fpu (SD_);
- check_fmt_p (SD_, fmt, instruction_0);
- StoreFPR(FD,fmt,Multiply(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt));
+ do_mul_fmt (SD_, FMT, FD, FS, FT, instruction_0);
}
-010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32,f::NEG.fmt
+010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000111:COP1:32,f::NEG.fmt
"neg.%s<FMT> f<FD>, f<FS>"
*mipsI:
*mipsII:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
- int fmt = FMT;
- check_fpu (SD_);
- check_fmt_p (SD_, fmt, instruction_0);
- StoreFPR(FD,fmt,Negate(ValueFPR(FS,fmt),fmt));
+ do_neg_fmt (SD_, FMT, FD, FS, instruction_0);
}
-// NMADD.fmt
-010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32,f::NMADD.D
-"nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
+010011,5.FR,5.FT,5.FS,5.FD,110,3.FMT!2!3!4!5!7:COP1X:32,f::NMADD.fmt
+"nmadd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
*mipsV:
+*mips32r2:
*mips64:
+*mips64r2:
*vr5000:
{
- check_fpu (SD_);
- StoreFPR(FD,fmt_double,Negate(Add(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double),fmt_double));
+ do_nmadd_fmt (SD_, FMT, FD, FR, FS, FT, instruction_0);
}
-// NMADD.fmt
-010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32,f::NMADD.S
-"nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
+010011,5.FR,5.FT,5.FS,5.FD,111,3.FMT!2!3!4!5!7:COP1X:32,f::NMSUB.fmt
+"nmsub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
*mipsV:
+*mips32r2:
*mips64:
+*mips64r2:
*vr5000:
{
- check_fpu (SD_);
- StoreFPR(FD,fmt_single,Negate(Add(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single),fmt_single));
+ do_nmsub_fmt (SD_, FMT, FD, FR, FS, FT, instruction_0);
}
-// NMSUB.fmt
-010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32,f::NMSUB.D
-"nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
-*mipsIV:
+010001,10,110,5.FT,5.FS,5.FD,101100:COP1:32,f::PLL.PS
+"pll.ps f<FD>, f<FS>, f<FT>"
*mipsV:
+*mips32r2:
*mips64:
-*vr5000:
+*mips64r2:
{
- check_fpu (SD_);
- StoreFPR(FD,fmt_double,Negate(Sub(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double),fmt_double));
+ do_pll_ps (SD_, FD, FS, FT, instruction_0);
}
-// NMSUB.fmt
-010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32,f::NMSUB.S
-"nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
-*mipsIV:
+010001,10,110,5.FT,5.FS,5.FD,101101:COP1:32,f::PLU.PS
+"plu.ps f<FD>, f<FS>, f<FT>"
*mipsV:
+*mips32r2:
*mips64:
-*vr5000:
+*mips64r2:
{
- check_fpu (SD_);
- StoreFPR(FD,fmt_single,Negate(Sub(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single),fmt_single));
+ do_plu_ps (SD_, FD, FS, FT, instruction_0);
}
-010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:64::PREFX
+010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:32::PREFX
"prefx <HINT>, r<INDEX>(r<BASE>)"
*mipsIV:
*mipsV:
+*mips32r2:
*mips64:
+*mips64r2:
*vr5000:
{
- address_word base = GPR[BASE];
- address_word index = GPR[INDEX];
- {
- address_word vaddr = loadstore_ea (SD_, base, index);
- address_word paddr;
- int uncached;
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- Prefetch(uncached,paddr,vaddr,isDATA,HINT);
- }
+ do_prefx (SD_, HINT, INDEX, BASE);
+}
+
+
+010001,10,110,5.FT,5.FS,5.FD,101110:COP1:32,f::PUL.PS
+"pul.ps f<FD>, f<FS>, f<FT>"
+*mipsV:
+*mips32r2:
+*mips64:
+*mips64r2:
+{
+ do_pul_ps (SD_, FD, FS, FT, instruction_0);
}
-010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.fmt
+
+010001,10,110,5.FT,5.FS,5.FD,101111:COP1:32,f::PUU.PS
+"puu.ps f<FD>, f<FS>, f<FT>"
+*mipsV:
+*mips32r2:
+*mips64:
+*mips64r2:
+{
+ do_puu_ps (SD_, FD, FS, FT, instruction_0);
+}
+
+
+010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.fmt
"recip.%s<FMT> f<FD>, f<FS>"
*mipsIV:
*mipsV:
+*mips32r2:
*mips64:
+*mips64r2:
*vr5000:
{
- int fmt = FMT;
- check_fpu (SD_);
- check_fmt (SD_, fmt, instruction_0);
- StoreFPR(FD,fmt,Recip(ValueFPR(FS,fmt),fmt));
+ do_recip_fmt (SD_, FMT, FD, FS);
}
-010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64,f::ROUND.L.fmt
+010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001000:COP1:32,f::ROUND.L.fmt
"round.l.%s<FMT> f<FD>, f<FS>"
*mipsIII:
*mipsIV:
*mipsV:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
- int fmt = FMT;
- check_fpu (SD_);
- check_fmt (SD_, fmt, instruction_0);
- StoreFPR(FD,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(FS,fmt),fmt,fmt_long));
+ do_round_fmt (SD_, fmt_long, FMT, FD, FS);
}
-010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32,f::ROUND.W.fmt
+010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001100:COP1:32,f::ROUND.W.fmt
"round.w.%s<FMT> f<FD>, f<FS>"
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
- int fmt = FMT;
- check_fpu (SD_);
- check_fmt (SD_, fmt, instruction_0);
- StoreFPR(FD,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(FS,fmt),fmt,fmt_word));
+ do_round_fmt (SD_, fmt_word, FMT, FD, FS);
}
-010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.fmt
+010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.fmt
+"rsqrt.%s<FMT> f<FD>, f<FS>"
*mipsIV:
*mipsV:
+*mips32r2:
*mips64:
-"rsqrt.%s<FMT> f<FD>, f<FS>"
+*mips64r2:
*vr5000:
{
- int fmt = FMT;
- check_fpu (SD_);
- check_fmt (SD_, fmt, instruction_0);
- StoreFPR(FD,fmt,Recip(SquareRoot(ValueFPR(FS,fmt),fmt),fmt));
+ do_rsqrt_fmt (SD_, FMT, FD, FS);
}
-111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1
+111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1a
"sdc1 f<FT>, <OFFSET>(r<BASE>)"
*mipsII:
+*mips32:
+*mips32r2:
+{
+ do_sdc1 (SD_, FT, OFFSET, BASE);
+}
+
+
+111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1b
+"sdc1 f<FT>, <OFFSET>(r<BASE>)"
*mipsIII:
*mipsIV:
*mipsV:
-*mips32:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
}
+010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:32,f::SDXC1
+"sdxc1 f<FS>, r<INDEX>(r<BASE>)"
+*mips32r2
+{
+ check_fpu (SD_);
+ do_store_double (SD_, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
+}
+
+
010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64,f::SDXC1
"sdxc1 f<FS>, r<INDEX>(r<BASE>)"
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr5000:
{
check_fpu (SD_);
}
-010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.fmt
+010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:32,f::SUXC1
+"suxc1 f<FS>, r<INDEX>(r<BASE>)"
+*mips32r2:
+{
+ do_suxc1_32 (SD_, FS, INDEX, BASE);
+}
+
+
+010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:64,f::SUXC1
+"suxc1 f<FS>, r<INDEX>(r<BASE>)"
+*mipsV:
+*mips64:
+*mips64r2:
+{
+ check_fpu (SD_);
+ check_u64 (SD_, instruction_0);
+ do_suxc1_64 (SD_, FS, INDEX, BASE);
+}
+
+
+010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.fmt
"sqrt.%s<FMT> f<FD>, f<FS>"
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
- int fmt = FMT;
- check_fpu (SD_);
- check_fmt (SD_, fmt, instruction_0);
- StoreFPR(FD,fmt,(SquareRoot(ValueFPR(FS,fmt),fmt)));
+ do_sqrt_fmt (SD_, FMT, FD, FS);
}
-010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32,f::SUB.fmt
+010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000001:COP1:32,f::SUB.fmt
"sub.%s<FMT> f<FD>, f<FS>, f<FT>"
*mipsI:
*mipsII:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
- int fmt = FMT;
- check_fpu (SD_);
- check_fmt_p (SD_, fmt, instruction_0);
- StoreFPR(FD,fmt,Sub(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt));
+ do_sub_fmt (SD_, FMT, FD, FS, FT, instruction_0);
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
- address_word base = GPR[BASE];
- address_word offset = EXTEND16 (OFFSET);
- check_fpu (SD_);
- {
- address_word vaddr = loadstore_ea (SD_, base, offset);
- address_word paddr;
- int uncached;
- if ((vaddr & 3) != 0)
- {
- SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal);
- }
- else
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- uword64 memval = 0;
- uword64 memval1 = 0;
- uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
- address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
- address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
- byte = ((vaddr & mask) ^ bigendiancpu);
- memval = (((uword64)COP_SW(((instruction_0 >> 26) & 0x3),FT)) << (8 * byte));
- StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
- }
- }
- }
+ do_swc1 (SD_, FT, OFFSET, BASE, instruction_0);
}
"swxc1 f<FS>, r<INDEX>(r<BASE>)"
*mipsIV:
*mipsV:
+*mips32r2:
*mips64:
+*mips64r2:
*vr5000:
{
-
- address_word base = GPR[BASE];
- address_word index = GPR[INDEX];
- check_fpu (SD_);
- check_u64 (SD_, instruction_0);
- {
- address_word vaddr = loadstore_ea (SD_, base, index);
- address_word paddr;
- int uncached;
- if ((vaddr & 3) != 0)
- {
- SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
- }
- else
- {
- if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
- {
- unsigned64 memval = 0;
- unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
- unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
- byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
- memval = (((unsigned64)COP_SW(1,FS)) << (8 * byte));
- {
- StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
- }
- }
- }
- }
+ do_swxc1 (SD_, FS, INDEX, BASE, instruction_0);
}
-010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64,f::TRUNC.L.fmt
+010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001001:COP1:32,f::TRUNC.L.fmt
"trunc.l.%s<FMT> f<FD>, f<FS>"
*mipsIII:
*mipsIV:
*mipsV:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
- int fmt = FMT;
- check_fpu (SD_);
- check_fmt (SD_, fmt, instruction_0);
- StoreFPR(FD,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(FS,fmt),fmt,fmt_long));
+ do_trunc_fmt (SD_, fmt_long, FMT, FD, FS);
}
-010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32,f::TRUNC.W
+010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001101:COP1:32,f::TRUNC.W
"trunc.w.%s<FMT> f<FD>, f<FS>"
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
- int fmt = FMT;
- check_fpu (SD_);
- check_fmt (SD_, fmt, instruction_0);
- StoreFPR(FD,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(FS,fmt),fmt,fmt_word));
+ do_trunc_fmt (SD_, fmt_word, FMT, FD, FS);
}
\f
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
address_word offset = EXTEND16 (OFFSET);
{
address_word vaddr = loadstore_ea (SD_, base, offset);
- address_word paddr;
- int uncached;
- if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
- CacheOp(OP,vaddr,paddr,instruction_0);
+ address_word paddr = vaddr;
+ CacheOp(OP, vaddr, paddr, instruction_0);
}
}
-010000,1,0000000000000000000,111001:COP0:32::DI
-"di"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*vr4100:
-*vr5000:
-
-
-010000,00001,5.RT,5.RD,00000000000:COP0:64::DMFC0
+010000,00001,5.RT,5.RD,00000000,3.SEL:COP0:64::DMFC0
"dmfc0 r<RT>, r<RD>"
*mipsIII:
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
{
check_u64 (SD_, instruction_0);
- DecodeCoproc (instruction_0);
+ DecodeCoproc (instruction_0, 0, cp0_dmfc0, RT, RD, SEL);
}
-010000,00101,5.RT,5.RD,00000000000:COP0:64::DMTC0
+010000,00101,5.RT,5.RD,00000000,3.SEL:COP0:64::DMTC0
"dmtc0 r<RT>, r<RD>"
*mipsIII:
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
{
check_u64 (SD_, instruction_0);
- DecodeCoproc (instruction_0);
+ DecodeCoproc (instruction_0, 0, cp0_dmtc0, RT, RD, SEL);
}
-010000,1,0000000000000000000,111000:COP0:32::EI
-"ei"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips64:
-*vr4100:
-*vr5000:
-
-
010000,1,0000000000000000000,011000:COP0:32::ERET
"eret"
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
}
-010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
-"mfc0 r<RT>, r<RD> # <REGX>"
+010000,00000,5.RT,5.RD,00000000,3.SEL:COP0:32::MFC0
+"mfc0 r<RT>, r<RD> # <SEL>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
TRACE_ALU_INPUT0 ();
- DecodeCoproc (instruction_0);
+ DecodeCoproc (instruction_0, 0, cp0_mfc0, RT, RD, SEL);
TRACE_ALU_RESULT (GPR[RT]);
}
-010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
-"mtc0 r<RT>, r<RD> # <REGX>"
+010000,00100,5.RT,5.RD,00000000,3.SEL:COP0:32::MTC0
+"mtc0 r<RT>, r<RD> # <SEL>"
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
- DecodeCoproc (instruction_0);
+ DecodeCoproc (instruction_0, 0, cp0_mtc0, RT, RD, SEL);
}
*vr5000:
*r3900:
{
- DecodeCoproc (instruction_0);
+ DecodeCoproc (instruction_0, 0, cp0_rfe, 0, 0, 0x10);
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*r3900:
{
- DecodeCoproc (instruction_0);
+ DecodeCoproc (instruction_0, 2, 0, 0, 0, 0);
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
-\f
+
+:include:::mips3264r2.igen
:include:::m16.igen
+:include:::m16e.igen
:include:::mdmx.igen
+:include:::mips3d.igen
:include:::sb1.igen
:include:::tx.igen
:include:::vr.igen
-\f
+:include:::dsp.igen
+:include:::dsp2.igen
+:include:::smartmips.igen
+:include:::micromips.igen
+:include:::micromipsdsp.igen
+
projects / deliverable / binutils-gdb.git / blobdiff