:model:::mipsIV:mips8000:
:model:::mipsV:mipsisaV:
:model:::mips32:mipsisa32:
+:model:::mips32r2:mipsisa32r2:
:model:::mips64:mipsisa64:
+:model:::mips64r2:mipsisa64r2:
// Vendor ISAs:
//
// (or which pre-date or use different encodings than the standard
// instructions) are (for the most part) in separate .igen files.
:model:::vr4100:mips4100: // vr.igen
+:model:::vr4120:mips4120:
:model:::vr5000:mips5000:
+:model:::vr5400:mips5400:
+:model:::vr5500:mips5500:
:model:::r3900:mips3900: // tx.igen
// MIPS Application Specific Extensions (ASEs)
// Instructions for the ASEs are in separate .igen files.
// ASEs add instructions on to a base ISA.
:model:::mips16:mips16: // m16.igen (and m16.dc)
+:model:::mips16e:mips16e: // m16e.igen
+:model:::mips3d:mips3d: // mips3d.igen
:model:::mdmx:mdmx: // mdmx.igen
+:model:::dsp:dsp: // dsp.igen
+:model:::dsp2:dsp2: // dsp2.igen
+:model:::smartmips:smartmips: // smartmips.igen
// Vendor Extensions
//
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*vr4100:
*vr5000:
*r3900:
:function:::address_word:loadstore_ea:address_word base, address_word offset
*mips64:
+*mips64r2:
{
#if 0 /* XXX FIXME: enable this only after some additional testing. */
/* If in user mode and UX is not set, use 32-bit compatibility effective
*vr4100:
*vr5000:
*r3900:
-{
- /* For historical simulator compatibility (until documentation is
- found that makes these operations unpredictable on some of these
- architectures), this check never returns true. */
- return 0;
-}
-
-:function:::int:not_word_value:unsigned_word value
*mips32:
-{
- /* On MIPS32, since registers are 32-bits, there's no check to be done. */
- return 0;
-}
-
-:function:::int:not_word_value:unsigned_word value
+*mips32r2:
*mips64:
+*mips64r2:
{
- return ((value >> 32) != (value & 0x80000000 ? 0xFFFFFFFF : 0));
+#if WITH_TARGET_WORD_BITSIZE == 64
+ return value != (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
+#else
+ return 0;
+#endif
}
-
// Helper:
//
// Handle UNPREDICTABLE operation behaviour. The goal here is to prevent
:function:::void:unpredictable:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
{
unpredictable_action (CPU, CIA);
}
-// Helper:
+// Helpers:
//
// Check that an access to a HI/LO register meets timing requirements
//
-// The following requirements exist:
+// In all MIPS ISAs,
//
-// - A MT {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
-// - A OP {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
-// - A MF {HI,LO} read was not corrupted by a preceeding MT{LO,HI} update
-// corruption occures when MT{LO,HI} is preceeded by a OP {HI,LO}.
+// OP {HI and LO} followed by MT{LO or HI} (and not MT{HI or LO})
+// makes subsequent MF{HI or LO} UNPREDICTABLE. (1)
//
+// The following restrictions exist for MIPS I - MIPS III:
+//
+// MF{HI or LO} followed by MT{HI or LO} w/ less than 2 instructions
+// in between makes MF UNPREDICTABLE. (2)
+//
+// MF{HI or LO} followed by OP {HI and LO} w/ less than 2 instructions
+// in between makes MF UNPREDICTABLE. (3)
+//
+// On the r3900, restriction (2) is not present, and restriction (3) is not
+// present for multiplication.
+//
+// Unfortunately, there seems to be some confusion about whether the last
+// two restrictions should apply to "MIPS IV" as well. One edition of
+// the MIPS IV ISA says they do, but references in later ISA documents
+// suggest they don't.
+//
+// In reality, some MIPS IV parts, such as the VR5000 and VR5400, do have
+// these restrictions, while others, like the VR5500, don't. To accomodate
+// such differences, the MIPS IV and MIPS V version of these helper functions
+// use auxillary routines to determine whether the restriction applies.
+// check_mf_cycles:
+//
+// Helper used by check_mt_hilo, check_mult_hilo, and check_div_hilo
+// to check for restrictions (2) and (3) above.
+//
:function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
{
if (history->mf.timestamp + 3 > time)
return 1;
}
+
+// check_mt_hilo:
+//
+// Check for restriction (2) above (for ISAs/processors that have it),
+// and record timestamps for restriction (1) above.
+//
:function:::int:check_mt_hilo:hilo_history *history
*mipsI:
*mipsII:
*mipsIII:
-*mipsIV:
-*mipsV:
*vr4100:
*vr5000:
{
return ok;
}
+:function:::int:check_mt_hilo:hilo_history *history
+*mipsIV:
+*mipsV:
+{
+ signed64 time = sim_events_time (SD);
+ int ok = (! MIPS_MACH_HAS_MT_HILO_HAZARD (SD)
+ || check_mf_cycles (SD_, history, time, "MT"));
+ history->mt.timestamp = time;
+ history->mt.cia = CIA;
+ return ok;
+}
+
:function:::int:check_mt_hilo:hilo_history *history
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*r3900:
{
signed64 time = sim_events_time (SD);
}
+// check_mf_hilo:
+//
+// Check for restriction (1) above, and record timestamps for
+// restriction (2) and (3) above.
+//
:function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
*mipsI:
*mipsII:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
+// check_mult_hilo:
+//
+// Check for restriction (3) above (for ISAs/processors that have it)
+// for MULT ops, and record timestamps for restriction (1) above.
+//
:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
*mipsI:
*mipsII:
*mipsIII:
-*mipsIV:
-*mipsV:
*vr4100:
*vr5000:
{
return ok;
}
-// The r3900 mult and multu insns _can_ be exectuted immediatly after
-// a mf{hi,lo}
+:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
+*mipsIV:
+*mipsV:
+{
+ signed64 time = sim_events_time (SD);
+ int ok = (! MIPS_MACH_HAS_MULT_HILO_HAZARD (SD)
+ || (check_mf_cycles (SD_, hi, time, "OP")
+ && check_mf_cycles (SD_, lo, time, "OP")));
+ hi->op.timestamp = time;
+ lo->op.timestamp = time;
+ hi->op.cia = CIA;
+ lo->op.cia = CIA;
+ return ok;
+}
+
:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*r3900:
{
/* FIXME: could record the fact that a stall occured if we want */
}
+// check_div_hilo:
+//
+// Check for restriction (3) above (for ISAs/processors that have it)
+// for DIV ops, and record timestamps for restriction (1) above.
+//
:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
*mipsI:
*mipsII:
*mipsIII:
-*mipsIV:
-*mipsV:
-*mips32:
-*mips64:
*vr4100:
*vr5000:
*r3900:
return ok;
}
+:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
+*mipsIV:
+*mipsV:
+{
+ signed64 time = sim_events_time (SD);
+ int ok = (! MIPS_MACH_HAS_DIV_HILO_HAZARD (SD)
+ || (check_mf_cycles (SD_, hi, time, "OP")
+ && check_mf_cycles (SD_, lo, time, "OP")));
+ hi->op.timestamp = time;
+ lo->op.timestamp = time;
+ hi->op.cia = CIA;
+ lo->op.cia = CIA;
+ return ok;
+}
+
+:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
+*mips32:
+*mips32r2:
+*mips64:
+*mips64r2:
+{
+ signed64 time = sim_events_time (SD);
+ hi->op.timestamp = time;
+ lo->op.timestamp = time;
+ hi->op.cia = CIA;
+ lo->op.cia = CIA;
+ return 1;
+}
+
// Helper:
//
*mipsV:
*vr4100:
*vr5000:
+*vr5400:
+*vr5500:
{
// The check should be similar to mips64 for any with PX/UX bit equivalents.
}
:function:::void:check_u64:instruction_word insn
+*mips16e:
*mips64:
+*mips64r2:
{
#if 0 /* XXX FIXME: enable this only after some additional testing. */
if (UserMode && (SR & (status_UX|status_PX)) == 0)
//
// MIPS Architecture:
//
-// CPU Instruction Set (mipsI - mipsV, mips32, mips64)
+// CPU Instruction Set (mipsI - mipsV, mips32/r2, mips64/r2)
//
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
else
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if ((signed_word) GPR[RS] >= 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if (RS == 31)
Unpredictable ();
RA = (CIA + 8);
if ((signed_word) GPR[RS] >= 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if (RS == 31)
Unpredictable ();
RA = (CIA + 8);
executed */
if ((signed_word) GPR[RS] >= 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
else
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if ((signed_word) GPR[RS] >= 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
else
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if ((signed_word) GPR[RS] > 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
/* NOTE: The branch occurs AFTER the next instruction has been
executed */
if ((signed_word) GPR[RS] > 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
else
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
/* NOTE: The branch occurs AFTER the next instruction has been
executed */
if ((signed_word) GPR[RS] <= 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if ((signed_word) GPR[RS] <= 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
else
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if ((signed_word) GPR[RS] < 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if (RS == 31)
Unpredictable ();
RA = (CIA + 8);
executed */
if ((signed_word) GPR[RS] < 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if (RS == 31)
Unpredictable ();
RA = (CIA + 8);
if ((signed_word) GPR[RS] < 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
else
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
/* NOTE: The branch occurs AFTER the next instruction has been
executed */
if ((signed_word) GPR[RS] < 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
else
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
else
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
011100,5.RS,5.RT,5.RD,00000,100001:SPECIAL2:32::CLO
"clo r<RD>, r<RS>"
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
+*vr5500:
{
unsigned32 temp = GPR[RS];
unsigned32 i, mask;
011100,5.RS,5.RT,5.RD,00000,100000:SPECIAL2:32::CLZ
"clz r<RD>, r<RS>"
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
+*vr5500:
{
unsigned32 temp = GPR[RS];
unsigned32 i, mask;
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO
"dclo r<RD>, r<RS>"
*mips64:
+*mips64r2:
+*vr5500:
{
unsigned64 temp = GPR[RS];
unsigned32 i;
011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ
"dclz r<RD>, r<RS>"
*mips64:
+*mips64r2:
+*vr5500:
{
unsigned64 temp = GPR[RS];
unsigned32 i;
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
do_ddivu (SD_, RS, RT);
}
-
-
:function:::void:do_div:int rs, int rt
{
check_div_hilo (SD_, HIHISTORY, LOHISTORY);
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
}
-
:function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
{
unsigned64 lo;
sign = 0;
if (signed_p)
{
- if (op1 < 0)
+ if ((signed64) op1 < 0)
{
op1 = - op1;
++sign;
}
- if (op2 < 0)
+ if ((signed64) op2 < 0)
{
op2 = - op2;
++sign;
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
{
check_u64 (SD_, instruction_0);
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
{
check_u64 (SD_, instruction_0);
do_dmultu (SD_, RS, RT, RD);
}
+
+:function:::unsigned64:do_dror:unsigned64 x,unsigned64 y
+{
+ unsigned64 result;
+
+ y &= 63;
+ TRACE_ALU_INPUT2 (x, y);
+ result = ROTR64 (x, y);
+ TRACE_ALU_RESULT (result);
+ return result;
+}
+
+000000,00001,5.RT,5.RD,5.SHIFT,111010::64::DROR
+"dror r<RD>, r<RT>, <SHIFT>"
+*mips64r2:
+*vr5400:
+*vr5500:
+{
+ check_u64 (SD_, instruction_0);
+ GPR[RD] = do_dror (SD_, GPR[RT], SHIFT);
+}
+
+000000,00001,5.RT,5.RD,5.SHIFT,111110::64::DROR32
+"dror32 r<RD>, r<RT>, <SHIFT>"
+*mips64r2:
+*vr5400:
+*vr5500:
+{
+ check_u64 (SD_, instruction_0);
+ GPR[RD] = do_dror (SD_, GPR[RT], SHIFT + 32);
+}
+
+000000,5.RS,5.RT,5.RD,00001,010110::64::DRORV
+"drorv r<RD>, r<RT>, r<RS>"
+*mips64r2:
+*vr5400:
+*vr5500:
+{
+ check_u64 (SD_, instruction_0);
+ GPR[RD] = do_dror (SD_, GPR[RT], GPR[RS]);
+}
+
+
:function:::void:do_dsll:int rt, int rd, int shift
{
TRACE_ALU_INPUT2 (GPR[rt], shift);
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
DELAY_SLOT (temp);
}
+000000,5.RS,00000,5.RD,10000,001001:SPECIAL:32::JALR_HB
+"jalr.hb r<RS>":RD == 31
+"jalr.hb r<RD>, r<RS>"
+*mips32r2:
+*mips64r2:
+{
+ address_word temp = GPR[RS];
+ GPR[RD] = CIA + 8;
+ DELAY_SLOT (temp);
+}
-000000,5.RS,000000000000000,001000:SPECIAL:32::JR
+000000,5.RS,0000000000,00000,001000:SPECIAL:32::JR
"jr r<RS>"
*mipsI:
*mipsII:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
DELAY_SLOT (GPR[RS]);
}
+000000,5.RS,0000000000,10000,001000:SPECIAL:32::JR_HB
+"jr.hb r<RS>"
+*mips32r2:
+*mips64r2:
+{
+ DELAY_SLOT (GPR[RS]);
+}
:function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
{
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
{
unsigned64 memval = 0;
unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
+ unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
unsigned int shift = 2;
unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
"madd r<RS>, r<RT>"
*mips32:
*mips64:
+*vr5500:
{
signed64 temp;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
}
+011100,5.RS,5.RT,000,2.AC,00000,000000:SPECIAL2:32::MADD
+"madd r<RS>, r<RT>":AC == 0
+"madd ac<AC>, r<RS>, r<RT>"
+*mips32r2:
+*mips64r2:
+*dsp2:
+{
+ signed64 temp;
+ if (AC == 0)
+ check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
+ if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
+ Unpredictable ();
+ TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
+ temp = (U8_4 (VL4_8 (DSPHI(AC)), VL4_8 (DSPLO(AC)))
+ + ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
+ DSPLO(AC) = EXTEND32 (temp);
+ DSPHI(AC) = EXTEND32 (VH4_8 (temp));
+ if (AC == 0)
+ TRACE_ALU_RESULT2 (HI, LO);
+}
+
011100,5.RS,5.RT,00000,00000,000001:SPECIAL2:32::MADDU
"maddu r<RS>, r<RT>"
*mips32:
*mips64:
+*vr5500:
{
unsigned64 temp;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
+ ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
+ ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp; /* SmartMIPS */
LO = EXTEND32 (temp);
HI = EXTEND32 (VH4_8 (temp));
TRACE_ALU_RESULT2 (HI, LO);
}
+011100,5.RS,5.RT,000,2.AC,00000,000001:SPECIAL2:32::MADDU
+"maddu r<RS>, r<RT>":AC == 0
+"maddu ac<AC>, r<RS>, r<RT>"
+*mips32r2:
+*mips64r2:
+*dsp2:
+{
+ unsigned64 temp;
+ if (AC == 0)
+ check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
+ if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
+ Unpredictable ();
+ TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
+ temp = (U8_4 (VL4_8 (DSPHI(AC)), VL4_8 (DSPLO(AC)))
+ + ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
+ if (AC == 0)
+ ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp; /* SmartMIPS */
+ DSPLO(AC) = EXTEND32 (temp);
+ DSPHI(AC) = EXTEND32 (VH4_8 (temp));
+ if (AC == 0)
+ TRACE_ALU_RESULT2 (HI, LO);
+}
+
+
:function:::void:do_mfhi:int rd
{
check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
*mipsIII:
*mipsIV:
*mipsV:
-*mips32:
-*mips64:
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
do_mfhi (SD_, RD);
}
+000000,000,2.AC,00000,5.RD,00000,010000:SPECIAL:32::MFHI
+"mfhi r<RD>":AC == 0
+"mfhi r<RD>, ac<AC>"
+*mips32r2:
+*mips64r2:
+*dsp:
+{
+ if (AC == 0)
+ do_mfhi (SD_, RD);
+ else
+ GPR[RD] = DSPHI(AC);
+}
+
:function:::void:do_mflo:int rd
{
*mipsIII:
*mipsIV:
*mipsV:
-*mips32:
-*mips64:
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
do_mflo (SD_, RD);
}
+000000,000,2.AC,00000,5.RD,00000,010010:SPECIAL:32::MFLO
+"mflo r<RD>":AC == 0
+"mflo r<RD>, ac<AC>"
+*mips32r2:
+*mips64r2:
+*dsp:
+{
+ if (AC == 0)
+ do_mflo (SD_, RD);
+ else
+ GPR[RD] = DSPLO(AC);
+}
+
000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN
"movn r<RD>, r<RS>, r<RT>"
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr5000:
{
if (GPR[RT] != 0)
- GPR[RD] = GPR[RS];
+ {
+ GPR[RD] = GPR[RS];
+ TRACE_ALU_RESULT (GPR[RD]);
+ }
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr5000:
{
if (GPR[RT] == 0)
- GPR[RD] = GPR[RS];
+ {
+ GPR[RD] = GPR[RS];
+ TRACE_ALU_RESULT (GPR[RD]);
+ }
}
"msub r<RS>, r<RT>"
*mips32:
*mips64:
+*vr5500:
{
signed64 temp;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
}
+011100,5.RS,5.RT,000,2.AC,00000,000100:SPECIAL2:32::MSUB
+"msub r<RS>, r<RT>":AC == 0
+"msub ac<AC>, r<RS>, r<RT>"
+*mips32r2:
+*mips64r2:
+*dsp2:
+{
+ signed64 temp;
+ if (AC == 0)
+ check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
+ if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
+ Unpredictable ();
+ TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
+ temp = (U8_4 (VL4_8 (DSPHI(AC)), VL4_8 (DSPLO(AC)))
+ - ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
+ DSPLO(AC) = EXTEND32 (temp);
+ DSPHI(AC) = EXTEND32 (VH4_8 (temp));
+ if (AC == 0)
+ TRACE_ALU_RESULT2 (HI, LO);
+}
+
011100,5.RS,5.RT,00000,00000,000101:SPECIAL2:32::MSUBU
"msubu r<RS>, r<RT>"
*mips32:
*mips64:
+*vr5500:
{
unsigned64 temp;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
}
+011100,5.RS,5.RT,000,2.AC,00000,000101:SPECIAL2:32::MSUBU
+"msubu r<RS>, r<RT>":AC == 0
+"msubu ac<AC>, r<RS>, r<RT>"
+*mips32r2:
+*mips64r2:
+*dsp2:
+{
+ unsigned64 temp;
+ if (AC == 0)
+ check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
+ if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
+ Unpredictable ();
+ TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
+ temp = (U8_4 (VL4_8 (DSPHI(AC)), VL4_8 (DSPLO(AC)))
+ - ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
+ DSPLO(AC) = EXTEND32 (temp);
+ DSPHI(AC) = EXTEND32 (VH4_8 (temp));
+ if (AC == 0)
+ TRACE_ALU_RESULT2 (HI, LO);
+}
+
000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
"mthi r<RS>"
*mipsIII:
*mipsIV:
*mipsV:
-*mips32:
-*mips64:
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
check_mt_hilo (SD_, HIHISTORY);
HI = GPR[RS];
}
+000000,5.RS,00000,000,2.AC,00000,010001:SPECIAL:32::MTHI
+"mthi r<RS>":AC == 0
+"mthi r<RS>, ac<AC>"
+*mips32r2:
+*mips64r2:
+*dsp:
+{
+ if (AC == 0)
+ check_mt_hilo (SD_, HIHISTORY);
+ DSPHI(AC) = GPR[RS];
+}
+
000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO
"mtlo r<RS>"
*mipsIII:
*mipsIV:
*mipsV:
-*mips32:
-*mips64:
*vr4100:
*vr5000:
*r3900:
+*mips32:
+*mips64:
{
check_mt_hilo (SD_, LOHISTORY);
LO = GPR[RS];
}
+000000,5.RS,00000,000,2.AC,00000,010011:SPECIAL:32::MTLO
+"mtlo r<RS>":AC == 0
+"mtlo r<RS>, ac<AC>"
+*mips32r2:
+*mips64r2:
+*dsp:
+{
+ if (AC == 0)
+ check_mt_hilo (SD_, LOHISTORY);
+ DSPLO(AC) = GPR[RS];
+}
+
011100,5.RS,5.RT,5.RD,00000,000010:SPECIAL2:32::MUL
"mul r<RD>, r<RS>, r<RT>"
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
+*vr5500:
{
signed64 prod;
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
* ((signed64)(signed32) GPR[rt]));
LO = EXTEND32 (VL4_8 (prod));
HI = EXTEND32 (VH4_8 (prod));
+ ACX = 0; /* SmartMIPS */
if (rd != 0)
GPR[rd] = LO;
TRACE_ALU_RESULT2 (HI, LO);
}
+000000,5.RS,5.RT,000,2.AC,00000,011000:SPECIAL:32::MULT
+"mult r<RS>, r<RT>":AC == 0
+"mult ac<AC>, r<RS>, r<RT>"
+*mips32r2:
+*mips64r2:
+*dsp2:
+{
+ signed64 prod;
+ if (AC == 0)
+ check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
+ if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
+ Unpredictable ();
+ TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
+ prod = ((signed64)(signed32) GPR[RS])
+ * ((signed64)(signed32) GPR[RT]);
+ DSPLO(AC) = EXTEND32 (VL4_8 (prod));
+ DSPHI(AC) = EXTEND32 (VH4_8 (prod));
+ if (AC == 0)
+ {
+ ACX = 0; /* SmartMIPS */
+ TRACE_ALU_RESULT2 (HI, LO);
+ }
+}
+
+
000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT
"mult r<RS>, r<RT>":RD == 0
"mult r<RD>, r<RS>, r<RT>"
do_multu (SD_, RS, RT, 0);
}
+
+000000,5.RS,5.RT,000,2.AC,00000,011001:SPECIAL:32::MULTU
+"multu r<RS>, r<RT>":AC == 0
+"multu r<RS>, r<RT>"
+*mips32r2:
+*mips64r2:
+*dsp2:
+{
+ unsigned64 prod;
+ if (AC == 0)
+ check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
+ if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
+ Unpredictable ();
+ TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
+ prod = ((unsigned64)(unsigned32) GPR[RS])
+ * ((unsigned64)(unsigned32) GPR[RT]);
+ DSPLO(AC) = EXTEND32 (VL4_8 (prod));
+ DSPHI(AC) = EXTEND32 (VH4_8 (prod));
+ if (AC == 0)
+ TRACE_ALU_RESULT2 (HI, LO);
+}
+
+
000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU
"multu r<RS>, r<RT>":RD == 0
"multu r<RD>, r<RS>, r<RT>"
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr5000:
{
address_word base = GPR[BASE];
}
+:function:::unsigned64:do_ror:unsigned32 x,unsigned32 y
+{
+ unsigned64 result;
+
+ y &= 31;
+ TRACE_ALU_INPUT2 (x, y);
+ result = EXTEND32 (ROTR32 (x, y));
+ TRACE_ALU_RESULT (result);
+ return result;
+}
+
+000000,00001,5.RT,5.RD,5.SHIFT,000010::32::ROR
+"ror r<RD>, r<RT>, <SHIFT>"
+*mips32r2:
+*mips64r2:
+*smartmips:
+*vr5400:
+*vr5500:
+{
+ GPR[RD] = do_ror (SD_, GPR[RT], SHIFT);
+}
+
+000000,5.RS,5.RT,5.RD,00001,000110::32::RORV
+"rorv r<RD>, r<RT>, r<RS>"
+*mips32r2:
+*mips64r2:
+*smartmips:
+*vr5400:
+*vr5500:
+{
+ GPR[RD] = do_ror (SD_, GPR[RT], GPR[RS]);
+}
+
+
:function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
{
address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
{
unsigned64 memval = 0;
unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
+ unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+ address_word reverseendian = (ReverseEndian ? (mask ^ AccessLength_WORD) : 0);
+ address_word bigendiancpu = (BigEndianCPU ? (mask ^ AccessLength_WORD) : 0);
unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
- byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
+ paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
+ byte = ((vaddr & mask) ^ bigendiancpu);
memval = ((unsigned64) GPR[RT] << (8 * byte));
if (LLBIT)
{
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
}
+
101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
"sh r<RT>, <OFFSET>(r<BASE>)"
*mipsI:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
"ssnop":RD == 0 && RT == 0 && SHIFT == 1
"sll r<RD>, r<RT>, <SHIFT>"
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
{
/* Skip shift for NOP and SSNOP, so that there won't be lots of
extraneous trace output. */
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*r3900:
*vr5000:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
-"tne r<RS>, <IMMEDIATE>"
+"tnei r<RS>, <IMMEDIATE>"
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
case fmt_double: return "d";
case fmt_word: return "w";
case fmt_long: return "l";
- default: return "?";
- }
-}
-
-:%s::::X:int x
-{
- switch (x)
- {
- case 0: return "f";
- case 1: return "t";
+ case fmt_ps: return "ps";
default: return "?";
}
}
// ReservedInstruction exception if not.
//
-// check_fmt checks that the format is single or double.
-:function:::void:check_fmt:int fmt, instruction_word insn
+// check_fmt_p checks that the format is single, double, or paired single.
+:function:::void:check_fmt_p:int fmt, instruction_word insn
*mipsI:
*mipsII:
*mipsIII:
*mipsIV:
-*mipsV:
*mips32:
-*mips64:
*vr4100:
*vr5000:
*r3900:
{
+ /* None of these ISAs support Paired Single, so just fall back to
+ the single/double check. */
if ((fmt != fmt_single) && (fmt != fmt_double))
SignalException (ReservedInstruction, insn);
}
-// check_fmt_p checks that the format is single, double, or paired single.
:function:::void:check_fmt_p:int fmt, instruction_word insn
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mips32:
-*vr4100:
-*vr5000:
-*r3900:
+*mips32r2:
{
- /* None of these ISAs support Paired Single, so just fall back to
- the single/double check. */
- check_fmt (SD_, fmt, insn);
+ if ((fmt != fmt_single) && (fmt != fmt_double) && (fmt != fmt_ps))
+ SignalException (ReservedInstruction, insn);
}
:function:::void:check_fmt_p:int fmt, instruction_word insn
*mipsV:
*mips64:
+*mips64r2:
{
-#if 0 /* XXX FIXME: FP code doesn't yet support paired single ops. */
if ((fmt != fmt_single) && (fmt != fmt_double)
&& (fmt != fmt_ps || (UserMode && (SR & (status_UX|status_PX)) == 0)))
SignalException (ReservedInstruction, insn);
-#else
- check_fmt (SD_, fmt, insn);
-#endif
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
}
-010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
-"abs.%s<FMT> f<FD>, f<FS>"
-*mipsI:
+// Helper:
+//
+// Load a double word FP value using 2 32-bit memory cycles a la MIPS II
+// or MIPS32. do_load cannot be used instead because it returns an
+// unsigned_word, which is limited to the size of the machine's registers.
+//
+
+:function:::unsigned64:do_load_double:address_word base, address_word offset
*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
*mips32:
-*mips64:
-*vr4100:
-*vr5000:
-*r3900:
+*mips32r2:
{
- int fmt = FMT;
- check_fpu (SD_);
+ int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
+ address_word vaddr;
+ address_word paddr;
+ int uncached;
+ unsigned64 memval;
+ unsigned64 v;
+
+ vaddr = loadstore_ea (SD_, base, offset);
+ if ((vaddr & AccessLength_DOUBLEWORD) != 0)
+ {
+ SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map,
+ AccessLength_DOUBLEWORD + 1, vaddr, read_transfer,
+ sim_core_unaligned_signal);
+ }
+ AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET,
+ isREAL);
+ LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr, vaddr,
+ isDATA, isREAL);
+ v = (unsigned64)memval;
+ LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr + 4, vaddr + 4,
+ isDATA, isREAL);
+ return (bigendian ? ((v << 32) | memval) : (v | (memval << 32)));
+}
+
+
+// Helper:
+//
+// Store a double word FP value using 2 32-bit memory cycles a la MIPS II
+// or MIPS32. do_load cannot be used instead because it returns an
+// unsigned_word, which is limited to the size of the machine's registers.
+//
+
+:function:::void:do_store_double:address_word base, address_word offset, unsigned64 v
+*mipsII:
+*mips32:
+*mips32r2:
+{
+ int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
+ address_word vaddr;
+ address_word paddr;
+ int uncached;
+ unsigned64 memval;
+
+ vaddr = loadstore_ea (SD_, base, offset);
+ if ((vaddr & AccessLength_DOUBLEWORD) != 0)
+ {
+ SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map,
+ AccessLength_DOUBLEWORD + 1, vaddr, write_transfer,
+ sim_core_unaligned_signal);
+ }
+ AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET,
+ isREAL);
+ memval = (bigendian ? (v >> 32) : (v & 0xFFFFFFFF));
+ StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
+ isREAL);
+ memval = (bigendian ? (v & 0xFFFFFFFF) : (v >> 32));
+ StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr + 4, vaddr + 4,
+ isREAL);
+}
+
+
+010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
+"abs.%s<FMT> f<FD>, f<FS>"
+*mipsI:
+*mipsII:
+*mipsIII:
+*mipsIV:
+*mipsV:
+*mips32:
+*mips32r2:
+*mips64:
+*mips64r2:
+*vr4100:
+*vr5000:
+*r3900:
+{
+ int fmt = FMT;
+ check_fpu (SD_);
check_fmt_p (SD_, fmt, instruction_0);
- StoreFPR(FD,fmt,AbsoluteValue(ValueFPR(FS,fmt),fmt));
+ StoreFPR (FD, fmt, AbsoluteValue (ValueFPR (FS, fmt), fmt));
}
-010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
+010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
"add.%s<FMT> f<FD>, f<FS>, f<FT>"
*mipsI:
*mipsII:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
int fmt = FMT;
check_fpu (SD_);
check_fmt_p (SD_, fmt, instruction_0);
- StoreFPR(FD,fmt,Add(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt));
+ StoreFPR (FD, fmt, Add (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
}
+010011,5.RS,5.FT,5.FS,5.FD,011,110:COP1X:32,f::ALNV.PS
+"alnv.ps f<FD>, f<FS>, f<FT>, r<RS>"
+*mipsV:
+*mips32r2:
+*mips64:
+*mips64r2:
+{
+ unsigned64 fs;
+ unsigned64 ft;
+ unsigned64 fd;
+ check_fpu (SD_);
+ check_u64 (SD_, instruction_0);
+ fs = ValueFPR (FS, fmt_ps);
+ if ((GPR[RS] & 0x3) != 0)
+ Unpredictable ();
+ if ((GPR[RS] & 0x4) == 0)
+ fd = fs;
+ else
+ {
+ ft = ValueFPR (FT, fmt_ps);
+ if (BigEndianCPU)
+ fd = PackPS (PSLower (fs), PSUpper (ft));
+ else
+ fd = PackPS (PSLower (ft), PSUpper (fs));
+ }
+ StoreFPR (FD, fmt_ps, fd);
+}
+
// BC1F
// BC1FL
*mipsIII:
{
check_fpu (SD_);
- check_branch_bug ();
TRACE_BRANCH_INPUT (PREVCOC1());
if (PREVCOC1() == TF)
{
address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
TRACE_BRANCH_RESULT (dest);
- mark_branch_bug (dest);
DELAY_SLOT (dest);
}
else if (ND)
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
#*vr4100:
*vr5000:
*r3900:
{
check_fpu (SD_);
- check_branch_bug ();
if (GETFCC(CC) == TF)
{
address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
- mark_branch_bug (dest);
DELAY_SLOT (dest);
}
else if (ND)
}
-
-
-
-
-// C.EQ.S
-// C.EQ.D
-// ...
-
-:function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn
-{
- int less;
- int equal;
- int unordered;
- int condition;
- unsigned64 ofs = ValueFPR (fs, fmt);
- unsigned64 oft = ValueFPR (ft, fmt);
- if (NaN (ofs, fmt) || NaN (oft, fmt))
- {
- if (FCSR & FP_ENABLE (IO))
- {
- FCSR |= FP_CAUSE (IO);
- SignalExceptionFPE ();
- }
- less = 0;
- equal = 0;
- unordered = 1;
- }
- else
- {
- less = Less (ofs, oft, fmt);
- equal = Equal (ofs, oft, fmt);
- unordered = 0;
- }
- condition = (((cond & (1 << 2)) && less)
- || ((cond & (1 << 1)) && equal)
- || ((cond & (1 << 0)) && unordered));
- SETFCC (cc, condition);
-}
-
-010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32,f::C.cond.fmta
+010001,10,3.FMT!2!3!4!5!6!7,5.FT,5.FS,3.0,00,11,4.COND:COP1:32,f::C.cond.fmta
"c.%s<COND>.%s<FMT> f<FS>, f<FT>"
*mipsI:
*mipsII:
{
int fmt = FMT;
check_fpu (SD_);
- check_fmt_p (SD_, fmt, instruction_0);
- do_c_cond_fmt (SD_, fmt, FT, FS, 0, COND, instruction_0);
+ Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, 0);
+ TRACE_ALU_RESULT (ValueFCR (31));
}
-010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32,f::C.cond.fmtb
+010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32,f::C.cond.fmtb
"c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
"c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
int fmt = FMT;
check_fpu (SD_);
check_fmt_p (SD_, fmt, instruction_0);
- do_c_cond_fmt (SD_, fmt, FT, FS, CC, COND, instruction_0);
+ Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, CC);
+ TRACE_ALU_RESULT (ValueFCR (31));
}
-010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64,f::CEIL.L.fmt
+010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001010:COP1:32,f::CEIL.L.fmt
"ceil.l.%s<FMT> f<FD>, f<FS>"
*mipsIII:
*mipsIV:
*mipsV:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
int fmt = FMT;
check_fpu (SD_);
- check_fmt (SD_, fmt, instruction_0);
- StoreFPR(FD,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(FS,fmt),fmt,fmt_long));
+ StoreFPR (FD, fmt_long, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
+ fmt_long));
}
-010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32,f::CEIL.W
+010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001110:COP1:32,f::CEIL.W
+"ceil.w.%s<FMT> f<FD>, f<FS>"
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
int fmt = FMT;
check_fpu (SD_);
- check_fmt (SD_, fmt, instruction_0);
- StoreFPR(FD,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(FS,fmt),fmt,fmt_word));
+ StoreFPR (FD, fmt_word, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
+ fmt_word));
}
-// CFC1
-// CTC1
-010001,00,X,10,5.RT,5.FS,00000000000:COP1Sa:32,f::CxC1
-"c%s<X>c1 r<RT>, f<FS>"
+010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1a
+"cfc1 r<RT>, f<FS>"
*mipsI:
*mipsII:
*mipsIII:
{
check_fpu (SD_);
- if (X)
+ if (FS == 0)
+ PENDING_FILL (RT, EXTEND32 (FCR0));
+ else if (FS == 31)
+ PENDING_FILL (RT, EXTEND32 (FCR31));
+ /* else NOP */
+}
+
+010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1b
+"cfc1 r<RT>, f<FS>"
+*mipsIV:
+*vr4100:
+*vr5000:
+*r3900:
+{
+ check_fpu (SD_);
+ if (FS == 0 || FS == 31)
{
- if (FS == 0)
- PENDING_FILL(FCR0IDX,VL4_8(GPR[RT]));
- else if (FS == 31)
- PENDING_FILL(FCR31IDX,VL4_8(GPR[RT]));
- /* else NOP */
- PENDING_SCHED(FCSR, FCR31 & (1<<23), 1, 23);
- }
- else
- { /* control from */
- if (FS == 0)
- PENDING_FILL(RT, EXTEND32 (FCR0));
- else if (FS == 31)
- PENDING_FILL(RT, EXTEND32 (FCR31));
- /* else NOP */
+ unsigned_word fcr = ValueFCR (FS);
+ TRACE_ALU_INPUT1 (fcr);
+ GPR[RT] = fcr;
}
+ /* else NOP */
+ TRACE_ALU_RESULT (GPR[RT]);
}
-010001,00,X,10,5.RT,5.FS,00000000000:COP1Sb:32,f::CxC1
-"c%s<X>c1 r<RT>, f<FS>"
-*mipsIV:
+
+010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1c
+"cfc1 r<RT>, f<FS>"
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
+{
+ check_fpu (SD_);
+ if (FS == 0 || FS == 25 || FS == 26 || FS == 28 || FS == 31)
+ {
+ unsigned_word fcr = ValueFCR (FS);
+ TRACE_ALU_INPUT1 (fcr);
+ GPR[RT] = fcr;
+ }
+ /* else NOP */
+ TRACE_ALU_RESULT (GPR[RT]);
+}
+
+010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1a
+"ctc1 r<RT>, f<FS>"
+*mipsI:
+*mipsII:
+*mipsIII:
+{
+ check_fpu (SD_);
+ if (FS == 31)
+ PENDING_FILL (FCRCS_REGNUM, VL4_8 (GPR[RT]));
+ /* else NOP */
+}
+
+010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1b
+"ctc1 r<RT>, f<FS>"
+*mipsIV:
*vr4100:
*vr5000:
*r3900:
{
check_fpu (SD_);
- if (X)
- {
- /* control to */
- TRACE_ALU_INPUT1 (GPR[RT]);
- if (FS == 0)
- {
- FCR0 = VL4_8(GPR[RT]);
- TRACE_ALU_RESULT (FCR0);
- }
- else if (FS == 31)
- {
- FCR31 = VL4_8(GPR[RT]);
- SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
- TRACE_ALU_RESULT (FCR31);
- }
- else
- {
- TRACE_ALU_RESULT0 ();
- }
- /* else NOP */
- }
- else
- { /* control from */
- if (FS == 0)
- {
- TRACE_ALU_INPUT1 (FCR0);
- GPR[RT] = EXTEND32 (FCR0);
- }
- else if (FS == 31)
- {
- TRACE_ALU_INPUT1 (FCR31);
- GPR[RT] = EXTEND32 (FCR31);
- }
- TRACE_ALU_RESULT (GPR[RT]);
- /* else NOP */
- }
+ TRACE_ALU_INPUT1 (GPR[RT]);
+ if (FS == 31)
+ StoreFCR (FS, GPR[RT]);
+ /* else NOP */
+}
+
+010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1c
+"ctc1 r<RT>, f<FS>"
+*mipsV:
+*mips32:
+*mips32r2:
+*mips64:
+*mips64r2:
+{
+ check_fpu (SD_);
+ TRACE_ALU_INPUT1 (GPR[RT]);
+ if (FS == 25 || FS == 26 || FS == 28 || FS == 31)
+ StoreFCR (FS, GPR[RT]);
+ /* else NOP */
}
//
// FIXME: Does not correctly differentiate between mips*
//
-010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32,f::CVT.D.fmt
+010001,10,3.FMT!1!2!3!6!7,00000,5.FS,5.FD,100001:COP1:32,f::CVT.D.fmt
"cvt.d.%s<FMT> f<FD>, f<FS>"
*mipsI:
*mipsII:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
int fmt = FMT;
check_fpu (SD_);
- {
- if ((fmt == fmt_double) | 0)
- SignalException (ReservedInstruction, instruction_0);
- else
- StoreFPR(FD,fmt_double,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_double));
- }
+ if ((fmt == fmt_double) | 0)
+ SignalException (ReservedInstruction, instruction_0);
+ StoreFPR (FD, fmt_double, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
+ fmt_double));
}
-010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64,f::CVT.L.fmt
+010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100101:COP1:32,f::CVT.L.fmt
"cvt.l.%s<FMT> f<FD>, f<FS>"
*mipsIII:
*mipsIV:
*mipsV:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
int fmt = FMT;
check_fpu (SD_);
- {
- if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word)))
- SignalException (ReservedInstruction, instruction_0);
- else
- StoreFPR(FD,fmt_long,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_long));
- }
+ if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word)))
+ SignalException (ReservedInstruction, instruction_0);
+ StoreFPR (FD, fmt_long, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
+ fmt_long));
+}
+
+
+010001,10,000,5.FT,5.FS,5.FD,100110:COP1:32,f::CVT.PS.S
+"cvt.ps.s f<FD>, f<FS>, f<FT>"
+*mipsV:
+*mips32r2:
+*mips64:
+*mips64r2:
+{
+ check_fpu (SD_);
+ check_u64 (SD_, instruction_0);
+ StoreFPR (FD, fmt_ps, PackPS (ValueFPR (FS, fmt_single),
+ ValueFPR (FT, fmt_single)));
}
//
// FIXME: Does not correctly differentiate between mips*
//
-010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt
+010001,10,3.FMT!0!2!3!6!7,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt
"cvt.s.%s<FMT> f<FD>, f<FS>"
*mipsI:
*mipsII:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
int fmt = FMT;
check_fpu (SD_);
- {
- if ((fmt == fmt_single) | 0)
- SignalException (ReservedInstruction, instruction_0);
- else
- StoreFPR(FD,fmt_single,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_single));
- }
+ if ((fmt == fmt_single) | 0)
+ SignalException (ReservedInstruction, instruction_0);
+ StoreFPR (FD, fmt_single, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
+ fmt_single));
+}
+
+
+010001,10,110,00000,5.FS,5.FD,101000:COP1:32,f::CVT.S.PL
+"cvt.s.pl f<FD>, f<FS>"
+*mipsV:
+*mips32r2:
+*mips64:
+*mips64r2:
+{
+ check_fpu (SD_);
+ check_u64 (SD_, instruction_0);
+ StoreFPR (FD, fmt_single, PSLower (ValueFPR (FS, fmt_ps)));
}
-010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt
+010001,10,110,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.PU
+"cvt.s.pu f<FD>, f<FS>"
+*mipsV:
+*mips32r2:
+*mips64:
+*mips64r2:
+{
+ check_fpu (SD_);
+ check_u64 (SD_, instruction_0);
+ StoreFPR (FD, fmt_single, PSUpper (ValueFPR (FS, fmt_ps)));
+}
+
+
+010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt
"cvt.w.%s<FMT> f<FD>, f<FS>"
*mipsI:
*mipsII:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
int fmt = FMT;
check_fpu (SD_);
- {
- if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word)))
- SignalException (ReservedInstruction, instruction_0);
- else
- StoreFPR(FD,fmt_word,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_word));
- }
+ if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word)))
+ SignalException (ReservedInstruction, instruction_0);
+ StoreFPR (FD, fmt_word, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
+ fmt_word));
}
-010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.fmt
+010001,10,3.FMT!2!3!4!5!6!7,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.fmt
"div.%s<FMT> f<FD>, f<FS>, f<FT>"
*mipsI:
*mipsII:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
int fmt = FMT;
check_fpu (SD_);
- check_fmt (SD_, fmt, instruction_0);
- StoreFPR(FD,fmt,Divide(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt));
+ StoreFPR (FD, fmt, Divide (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
}
-// DMFC1
-// DMTC1
-010001,00,X,01,5.RT,5.FS,00000000000:COP1Sa:64,f::DMxC1
-"dm%s<X>c1 r<RT>, f<FS>"
+010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1a
+"dmfc1 r<RT>, f<FS>"
*mipsIII:
{
+ unsigned64 v;
check_fpu (SD_);
check_u64 (SD_, instruction_0);
- if (X)
- {
- if (SizeFGR() == 64)
- PENDING_FILL((FS + FGR_BASE),GPR[RT]);
- else if ((FS & 0x1) == 0)
- {
- PENDING_FILL(((FS + 1) + FGR_BASE),VH4_8(GPR[RT]));
- PENDING_FILL((FS + FGR_BASE),VL4_8(GPR[RT]));
- }
- }
+ if (SizeFGR () == 64)
+ v = FGR[FS];
+ else if ((FS & 0x1) == 0)
+ v = SET64HI (FGR[FS+1]) | FGR[FS];
else
- {
- if (SizeFGR() == 64)
- PENDING_FILL(RT,FGR[FS]);
- else if ((FS & 0x1) == 0)
- PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
- else
- {
- if (STATE_VERBOSE_P(SD))
- sim_io_eprintf (SD,
- "Warning: PC 0x%lx: semantic_DMxC1_COP1Sa 32-bit use of odd FPR number\n",
- (long) CIA);
- PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
- }
- }
+ v = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
+ PENDING_FILL (RT, v);
+ TRACE_ALU_RESULT (v);
}
-010001,00,X,01,5.RT,5.FS,00000000000:COP1Sb:64,f::DMxC1
-"dm%s<X>c1 r<RT>, f<FS>"
+
+010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1b
+"dmfc1 r<RT>, f<FS>"
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
check_fpu (SD_);
check_u64 (SD_, instruction_0);
- if (X)
- {
- if (SizeFGR() == 64)
- StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
- else if ((FS & 0x1) == 0)
- StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]);
- }
+ if (SizeFGR () == 64)
+ GPR[RT] = FGR[FS];
+ else if ((FS & 0x1) == 0)
+ GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
else
+ GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
+ TRACE_ALU_RESULT (GPR[RT]);
+}
+
+
+010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1a
+"dmtc1 r<RT>, f<FS>"
+*mipsIII:
+{
+ unsigned64 v;
+ check_fpu (SD_);
+ check_u64 (SD_, instruction_0);
+ if (SizeFGR () == 64)
+ PENDING_FILL ((FS + FGR_BASE), GPR[RT]);
+ else if ((FS & 0x1) == 0)
{
- if (SizeFGR() == 64)
- GPR[RT] = FGR[FS];
- else if ((FS & 0x1) == 0)
- GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
- else
- {
- if (STATE_VERBOSE_P(SD))
- sim_io_eprintf (SD,
- "Warning: PC 0x%lx: DMxC1 32-bit use of odd FPR number\n",
- (long) CIA);
- GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
- }
+ PENDING_FILL (((FS + 1) + FGR_BASE), VH4_8 (GPR[RT]));
+ PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
}
+ else
+ Unpredictable ();
+ TRACE_FP_RESULT (GPR[RT]);
+}
+
+010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1b
+"dmtc1 r<RT>, f<FS>"
+*mipsIV:
+*mipsV:
+*mips64:
+*mips64r2:
+*vr4100:
+*vr5000:
+*r3900:
+{
+ check_fpu (SD_);
+ check_u64 (SD_, instruction_0);
+ if (SizeFGR () == 64)
+ StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
+ else if ((FS & 0x1) == 0)
+ StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
+ else
+ Unpredictable ();
}
-010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64,f::FLOOR.L.fmt
+010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001011:COP1:32,f::FLOOR.L.fmt
"floor.l.%s<FMT> f<FD>, f<FS>"
*mipsIII:
*mipsIV:
*mipsV:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
int fmt = FMT;
check_fpu (SD_);
- check_fmt (SD_, fmt, instruction_0);
- StoreFPR(FD,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(FS,fmt),fmt,fmt_long));
+ StoreFPR (FD, fmt_long, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
+ fmt_long));
}
-010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32,f::FLOOR.W.fmt
+010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001111:COP1:32,f::FLOOR.W.fmt
"floor.w.%s<FMT> f<FD>, f<FS>"
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
int fmt = FMT;
check_fpu (SD_);
- check_fmt (SD_, fmt, instruction_0);
- StoreFPR(FD,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(FS,fmt),fmt,fmt_word));
+ StoreFPR (FD, fmt_word, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
+ fmt_word));
}
-110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1
+110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1a
"ldc1 f<FT>, <OFFSET>(r<BASE>)"
*mipsII:
+*mips32:
+*mips32r2:
+{
+ check_fpu (SD_);
+ COP_LD (1, FT, do_load_double (SD_, GPR[BASE], EXTEND16 (OFFSET)));
+}
+
+
+110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1b
+"ldc1 f<FT>, <OFFSET>(r<BASE>)"
*mipsIII:
*mipsIV:
*mipsV:
-*mips32:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
}
+010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:32,f::LDXC1
+"ldxc1 f<FD>, r<INDEX>(r<BASE>)"
+*mips32r2:
+{
+ check_fpu (SD_);
+ COP_LD (1, FD, do_load_double (SD_, GPR[BASE], GPR[INDEX]));
+}
+
+
010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64,f::LDXC1
"ldxc1 f<FD>, r<INDEX>(r<BASE>)"
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr5000:
{
check_fpu (SD_);
}
+010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:32,f::LUXC1
+"luxc1 f<FD>, r<INDEX>(r<BASE>)"
+*mips32r2:
+{
+ address_word base = GPR[BASE];
+ address_word index = GPR[INDEX];
+ address_word vaddr = base + index;
+ check_fpu (SD_);
+ if (SizeFGR () != 64)
+ Unpredictable ();
+ /* Arrange for the bottom 3 bits of (base + index) to be 0. */
+ if ((vaddr & 0x7) != 0)
+ index -= (vaddr & 0x7);
+ COP_LD (1, FD, do_load_double (SD_, base, index));
+}
+
+
+010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:64,f::LUXC1
+"luxc1 f<FD>, r<INDEX>(r<BASE>)"
+*mipsV:
+*mips64:
+*mips64r2:
+{
+ address_word base = GPR[BASE];
+ address_word index = GPR[INDEX];
+ address_word vaddr = base + index;
+ check_fpu (SD_);
+ check_u64 (SD_, instruction_0);
+ if (SizeFGR () != 64)
+ Unpredictable ();
+ /* Arrange for the bottom 3 bits of (base + index) to be 0. */
+ if ((vaddr & 0x7) != 0)
+ index -= (vaddr & 0x7);
+ COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, base, index));
+}
+
110001,5.BASE,5.FT,16.OFFSET:COP1:32,f::LWC1
"lwc1 f<FT>, <OFFSET>(r<BASE>)"
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
}
-010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:64,f::LWXC1
+010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32,f::LWXC1
"lwxc1 f<FD>, r<INDEX>(r<BASE>)"
*mipsIV:
*mipsV:
+*mips32r2:
*mips64:
+*mips64r2:
*vr5000:
{
check_fpu (SD_);
-//
-// FIXME: Not correct for mips*
-//
-010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
-"madd.d f<FD>, f<FR>, f<FS>, f<FT>"
-*mipsIV:
-*mipsV:
-*mips64:
-*vr5000:
-{
- check_fpu (SD_);
- {
- StoreFPR(FD,fmt_double,Add(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double));
- }
-}
-
-
-010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
-"madd.s f<FD>, f<FR>, f<FS>, f<FT>"
+010011,5.FR,5.FT,5.FS,5.FD,100,3.FMT!2!3!4!5!7:COP1X:32,f::MADD.fmt
+"madd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
*mipsV:
+*mips32r2:
*mips64:
+*mips64r2:
*vr5000:
{
+ int fmt = FMT;
check_fpu (SD_);
- {
- StoreFPR(FD,fmt_single,Add(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single));
- }
+ check_u64 (SD_, instruction_0);
+ check_fmt_p (SD_, fmt, instruction_0);
+ StoreFPR (FD, fmt, MultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
+ ValueFPR (FR, fmt), fmt));
}
-// MFC1
-// MTC1
-010001,00,X,00,5.RT,5.FS,00000000000:COP1Sa:32,f::MxC1
-"m%s<X>c1 r<RT>, f<FS>"
+010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1a
+"mfc1 r<RT>, f<FS>"
*mipsI:
*mipsII:
*mipsIII:
{
+ unsigned64 v;
check_fpu (SD_);
- if (X)
- { /*MTC1*/
- if (SizeFGR() == 64)
- {
- if (STATE_VERBOSE_P(SD))
- sim_io_eprintf (SD,
- "Warning: PC 0x%lx: MTC1 not DMTC1 with 64 bit regs\n",
- (long) CIA);
- PENDING_FILL ((FS + FGR_BASE), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
- }
- else
- PENDING_FILL ((FS + FGR_BASE), VL4_8(GPR[RT]));
- }
- else /*MFC1*/
- PENDING_FILL (RT, EXTEND32 (FGR[FS]));
+ v = EXTEND32 (FGR[FS]);
+ PENDING_FILL (RT, v);
+ TRACE_ALU_RESULT (v);
}
-010001,00,X,00,5.RT,5.FS,00000000000:COP1Sb:32,f::MxC1
-"m%s<X>c1 r<RT>, f<FS>"
+
+010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1b
+"mfc1 r<RT>, f<FS>"
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
-{
- int fs = FS;
+{
check_fpu (SD_);
- if (X)
- /*MTC1*/
- StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
- else /*MFC1*/
- GPR[RT] = EXTEND32 (FGR[FS]);
+ GPR[RT] = EXTEND32 (FGR[FS]);
+ TRACE_ALU_RESULT (GPR[RT]);
}
-010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32,f::MOV.fmt
+010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000110:COP1:32,f::MOV.fmt
"mov.%s<FMT> f<FD>, f<FS>"
*mipsI:
*mipsII:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
int fmt = FMT;
check_fpu (SD_);
check_fmt_p (SD_, fmt, instruction_0);
- StoreFPR(FD,fmt,ValueFPR(FS,fmt));
+ StoreFPR (FD, fmt, ValueFPR (FS, fmt));
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr5000:
{
check_fpu (SD_);
// MOVF.fmt
// MOVT.fmt
-010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32,f::MOVtf.fmt
+010001,10,3.FMT!2!3!4!5!7,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32,f::MOVtf.fmt
"mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr5000:
{
int fmt = FMT;
check_fpu (SD_);
- {
- if (GETFCC(CC) == TF)
- StoreFPR (FD, fmt, ValueFPR (FS, fmt));
- else
- StoreFPR (FD, fmt, ValueFPR (FD, fmt));
- }
+ if (fmt != fmt_ps)
+ {
+ if (GETFCC(CC) == TF)
+ StoreFPR (FD, fmt, ValueFPR (FS, fmt));
+ else
+ StoreFPR (FD, fmt, ValueFPR (FD, fmt)); /* set fmt */
+ }
+ else
+ {
+ unsigned64 fd;
+ fd = PackPS (PSUpper (ValueFPR ((GETFCC (CC+1) == TF) ? FS : FD,
+ fmt_ps)),
+ PSLower (ValueFPR ((GETFCC (CC+0) == TF) ? FS : FD,
+ fmt_ps)));
+ StoreFPR (FD, fmt_ps, fd);
+ }
}
-010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32,f::MOVN.fmt
+010001,10,3.FMT!2!3!4!5!7,5.RT,5.FS,5.FD,010011:COP1:32,f::MOVN.fmt
"movn.%s<FMT> f<FD>, f<FS>, r<RT>"
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr5000:
{
check_fpu (SD_);
-010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32,f::MOVZ.fmt
+010001,10,3.FMT!2!3!4!5!7,5.RT,5.FS,5.FD,010010:COP1:32,f::MOVZ.fmt
"movz.%s<FMT> f<FD>, f<FS>, r<RT>"
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr5000:
{
check_fpu (SD_);
}
-// MSUB.fmt
-010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32,f::MSUB.D
-"msub.d f<FD>, f<FR>, f<FS>, f<FT>"
+010011,5.FR,5.FT,5.FS,5.FD,101,3.FMT!2!3!4!5!7:COP1X:32,f::MSUB.fmt
+"msub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
*mipsV:
+*mips32r2:
*mips64:
+*mips64r2:
*vr5000:
{
+ int fmt = FMT;
check_fpu (SD_);
- StoreFPR(FD,fmt_double,Sub(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double));
+ check_u64 (SD_, instruction_0);
+ check_fmt_p (SD_, fmt, instruction_0);
+ StoreFPR (FD, fmt, MultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
+ ValueFPR (FR, fmt), fmt));
}
-// MSUB.fmt
-010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32,f::MSUB.S
-"msub.s f<FD>, f<FR>, f<FS>, f<FT>"
+010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1a
+"mtc1 r<RT>, f<FS>"
+*mipsI:
+*mipsII:
+*mipsIII:
+{
+ check_fpu (SD_);
+ if (SizeFGR () == 64)
+ PENDING_FILL ((FS + FGR_BASE), (SET64HI (0xDEADC0DE) | VL4_8 (GPR[RT])));
+ else
+ PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
+ TRACE_FP_RESULT (GPR[RT]);
+}
+
+010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1b
+"mtc1 r<RT>, f<FS>"
*mipsIV:
*mipsV:
+*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
+*vr4100:
*vr5000:
+*r3900:
{
- check_fpu (SD_);
- StoreFPR(FD,fmt_single,Sub(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single));
+ check_fpu (SD_);
+ StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
}
-// MTC1 see MxC1
-
-
-010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt
+010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt
"mul.%s<FMT> f<FD>, f<FS>, f<FT>"
*mipsI:
*mipsII:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
int fmt = FMT;
check_fpu (SD_);
check_fmt_p (SD_, fmt, instruction_0);
- StoreFPR(FD,fmt,Multiply(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt));
+ StoreFPR (FD, fmt, Multiply (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
}
-010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32,f::NEG.fmt
+010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000111:COP1:32,f::NEG.fmt
"neg.%s<FMT> f<FD>, f<FS>"
*mipsI:
*mipsII:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
int fmt = FMT;
check_fpu (SD_);
check_fmt_p (SD_, fmt, instruction_0);
- StoreFPR(FD,fmt,Negate(ValueFPR(FS,fmt),fmt));
+ StoreFPR (FD, fmt, Negate (ValueFPR (FS, fmt), fmt));
}
-// NMADD.fmt
-010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32,f::NMADD.D
-"nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
+010011,5.FR,5.FT,5.FS,5.FD,110,3.FMT!2!3!4!5!7:COP1X:32,f::NMADD.fmt
+"nmadd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
*mipsV:
+*mips32r2:
*mips64:
+*mips64r2:
*vr5000:
{
+ int fmt = FMT;
check_fpu (SD_);
- StoreFPR(FD,fmt_double,Negate(Add(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double),fmt_double));
+ check_u64 (SD_, instruction_0);
+ check_fmt_p (SD_, fmt, instruction_0);
+ StoreFPR (FD, fmt, NegMultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
+ ValueFPR (FR, fmt), fmt));
}
-// NMADD.fmt
-010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32,f::NMADD.S
-"nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
+010011,5.FR,5.FT,5.FS,5.FD,111,3.FMT!2!3!4!5!7:COP1X:32,f::NMSUB.fmt
+"nmsub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
*mipsIV:
*mipsV:
+*mips32r2:
*mips64:
+*mips64r2:
*vr5000:
{
+ int fmt = FMT;
check_fpu (SD_);
- StoreFPR(FD,fmt_single,Negate(Add(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single),fmt_single));
+ check_u64 (SD_, instruction_0);
+ check_fmt_p (SD_, fmt, instruction_0);
+ StoreFPR (FD, fmt, NegMultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
+ ValueFPR (FR, fmt), fmt));
}
-// NMSUB.fmt
-010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32,f::NMSUB.D
-"nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
-*mipsIV:
+010001,10,110,5.FT,5.FS,5.FD,101100:COP1:32,f::PLL.PS
+"pll.ps f<FD>, f<FS>, f<FT>"
*mipsV:
+*mips32r2:
*mips64:
-*vr5000:
+*mips64r2:
{
check_fpu (SD_);
- StoreFPR(FD,fmt_double,Negate(Sub(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double),fmt_double));
+ check_u64 (SD_, instruction_0);
+ StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
+ PSLower (ValueFPR (FT, fmt_ps))));
}
-// NMSUB.fmt
-010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32,f::NMSUB.S
-"nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
-*mipsIV:
+010001,10,110,5.FT,5.FS,5.FD,101101:COP1:32,f::PLU.PS
+"plu.ps f<FD>, f<FS>, f<FT>"
*mipsV:
+*mips32r2:
*mips64:
-*vr5000:
+*mips64r2:
{
check_fpu (SD_);
- StoreFPR(FD,fmt_single,Negate(Sub(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single),fmt_single));
+ check_u64 (SD_, instruction_0);
+ StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
+ PSUpper (ValueFPR (FT, fmt_ps))));
}
-010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:64::PREFX
+010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:32::PREFX
"prefx <HINT>, r<INDEX>(r<BASE>)"
*mipsIV:
*mipsV:
+*mips32r2:
*mips64:
+*mips64r2:
*vr5000:
{
address_word base = GPR[BASE];
}
}
-010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.fmt
+
+010001,10,110,5.FT,5.FS,5.FD,101110:COP1:32,f::PUL.PS
+"pul.ps f<FD>, f<FS>, f<FT>"
+*mipsV:
+*mips32r2:
+*mips64:
+*mips64r2:
+{
+ check_fpu (SD_);
+ check_u64 (SD_, instruction_0);
+ StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
+ PSLower (ValueFPR (FT, fmt_ps))));
+}
+
+
+010001,10,110,5.FT,5.FS,5.FD,101111:COP1:32,f::PUU.PS
+"puu.ps f<FD>, f<FS>, f<FT>"
+*mipsV:
+*mips32r2:
+*mips64:
+*mips64r2:
+{
+ check_fpu (SD_);
+ check_u64 (SD_, instruction_0);
+ StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
+ PSUpper (ValueFPR (FT, fmt_ps))));
+}
+
+
+010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.fmt
"recip.%s<FMT> f<FD>, f<FS>"
*mipsIV:
*mipsV:
+*mips32r2:
*mips64:
+*mips64r2:
*vr5000:
{
int fmt = FMT;
check_fpu (SD_);
- check_fmt (SD_, fmt, instruction_0);
- StoreFPR(FD,fmt,Recip(ValueFPR(FS,fmt),fmt));
+ StoreFPR (FD, fmt, Recip (ValueFPR (FS, fmt), fmt));
}
-010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64,f::ROUND.L.fmt
+010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001000:COP1:32,f::ROUND.L.fmt
"round.l.%s<FMT> f<FD>, f<FS>"
*mipsIII:
*mipsIV:
*mipsV:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
int fmt = FMT;
check_fpu (SD_);
- check_fmt (SD_, fmt, instruction_0);
- StoreFPR(FD,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(FS,fmt),fmt,fmt_long));
+ StoreFPR (FD, fmt_long, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
+ fmt_long));
}
-010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32,f::ROUND.W.fmt
+010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001100:COP1:32,f::ROUND.W.fmt
"round.w.%s<FMT> f<FD>, f<FS>"
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
int fmt = FMT;
check_fpu (SD_);
- check_fmt (SD_, fmt, instruction_0);
- StoreFPR(FD,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(FS,fmt),fmt,fmt_word));
+ StoreFPR (FD, fmt_word, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
+ fmt_word));
}
-010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.fmt
+010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.fmt
+"rsqrt.%s<FMT> f<FD>, f<FS>"
*mipsIV:
*mipsV:
+*mips32r2:
*mips64:
-"rsqrt.%s<FMT> f<FD>, f<FS>"
+*mips64r2:
*vr5000:
{
int fmt = FMT;
check_fpu (SD_);
- check_fmt (SD_, fmt, instruction_0);
- StoreFPR(FD,fmt,Recip(SquareRoot(ValueFPR(FS,fmt),fmt),fmt));
+ StoreFPR (FD, fmt, RSquareRoot (ValueFPR (FS, fmt), fmt));
}
-111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1
+111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1a
"sdc1 f<FT>, <OFFSET>(r<BASE>)"
*mipsII:
+*mips32:
+*mips32r2:
+{
+ check_fpu (SD_);
+ do_store_double (SD_, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
+}
+
+
+111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1b
+"sdc1 f<FT>, <OFFSET>(r<BASE>)"
*mipsIII:
*mipsIV:
*mipsV:
-*mips32:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
}
+010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:32,f::SDXC1
+"sdxc1 f<FS>, r<INDEX>(r<BASE>)"
+*mips32r2
+{
+ check_fpu (SD_);
+ do_store_double (SD_, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
+}
+
+
010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64,f::SDXC1
"sdxc1 f<FS>, r<INDEX>(r<BASE>)"
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
*vr5000:
{
check_fpu (SD_);
}
-010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.fmt
+010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:32,f::SUXC1
+"suxc1 f<FS>, r<INDEX>(r<BASE>)"
+*mips32r2:
+{
+ address_word base = GPR[BASE];
+ address_word index = GPR[INDEX];
+ address_word vaddr = base + index;
+ check_fpu (SD_);
+ if (SizeFGR () != 64)
+ Unpredictable ();
+ /* Arrange for the bottom 3 bits of (base + index) to be 0. */
+ if ((vaddr & 0x7) != 0)
+ index -= (vaddr & 0x7);
+ do_store_double (SD_, base, index, COP_SD (1, FS));
+}
+
+
+010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:64,f::SUXC1
+"suxc1 f<FS>, r<INDEX>(r<BASE>)"
+*mipsV:
+*mips64:
+*mips64r2:
+{
+ address_word base = GPR[BASE];
+ address_word index = GPR[INDEX];
+ address_word vaddr = base + index;
+ check_fpu (SD_);
+ check_u64 (SD_, instruction_0);
+ if (SizeFGR () != 64)
+ Unpredictable ();
+ /* Arrange for the bottom 3 bits of (base + index) to be 0. */
+ if ((vaddr & 0x7) != 0)
+ index -= (vaddr & 0x7);
+ do_store (SD_, AccessLength_DOUBLEWORD, base, index, COP_SD (1, FS));
+}
+
+
+010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.fmt
"sqrt.%s<FMT> f<FD>, f<FS>"
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
int fmt = FMT;
check_fpu (SD_);
- check_fmt (SD_, fmt, instruction_0);
- StoreFPR(FD,fmt,(SquareRoot(ValueFPR(FS,fmt),fmt)));
+ StoreFPR (FD, fmt, (SquareRoot (ValueFPR (FS, fmt), fmt)));
}
-010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32,f::SUB.fmt
+010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000001:COP1:32,f::SUB.fmt
"sub.%s<FMT> f<FD>, f<FS>, f<FT>"
*mipsI:
*mipsII:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
int fmt = FMT;
check_fpu (SD_);
check_fmt_p (SD_, fmt, instruction_0);
- StoreFPR(FD,fmt,Sub(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt));
+ StoreFPR (FD, fmt, Sub (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
}
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
"swxc1 f<FS>, r<INDEX>(r<BASE>)"
*mipsIV:
*mipsV:
+*mips32r2:
*mips64:
+*mips64r2:
*vr5000:
{
{
unsigned64 memval = 0;
unsigned64 memval1 = 0;
- unsigned64 mask = 0x7;
+ unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+ address_word reverseendian = (ReverseEndian ? (mask ^ AccessLength_WORD) : 0);
+ address_word bigendiancpu = (BigEndianCPU ? (mask ^ AccessLength_WORD) : 0);
unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
- byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
+ paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
+ byte = ((vaddr & mask) ^ bigendiancpu);
memval = (((unsigned64)COP_SW(1,FS)) << (8 * byte));
{
StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
}
-010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64,f::TRUNC.L.fmt
+010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001001:COP1:32,f::TRUNC.L.fmt
"trunc.l.%s<FMT> f<FD>, f<FS>"
*mipsIII:
*mipsIV:
*mipsV:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
int fmt = FMT;
check_fpu (SD_);
- check_fmt (SD_, fmt, instruction_0);
- StoreFPR(FD,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(FS,fmt),fmt,fmt_long));
+ StoreFPR (FD, fmt_long, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
+ fmt_long));
}
-010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32,f::TRUNC.W
+010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001101:COP1:32,f::TRUNC.W
"trunc.w.%s<FMT> f<FD>, f<FS>"
*mipsII:
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
{
int fmt = FMT;
check_fpu (SD_);
- check_fmt (SD_, fmt, instruction_0);
- StoreFPR(FD,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(FS,fmt),fmt,fmt_word));
+ StoreFPR (FD, fmt_word, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
+ fmt_word));
}
\f
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
}
-010000,1,0000000000000000000,111001:COP0:32::DI
-"di"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*vr4100:
-*vr5000:
-
-
010000,00001,5.RT,5.RD,00000000000:COP0:64::DMFC0
"dmfc0 r<RT>, r<RD>"
*mipsIII:
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
{
check_u64 (SD_, instruction_0);
DecodeCoproc (instruction_0);
*mipsIV:
*mipsV:
*mips64:
+*mips64r2:
{
check_u64 (SD_, instruction_0);
DecodeCoproc (instruction_0);
}
-010000,1,0000000000000000000,111000:COP0:32::EI
-"ei"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-*mipsV:
-*mips64:
-*vr4100:
-*vr5000:
-
-
010000,1,0000000000000000000,011000:COP0:32::ERET
"eret"
*mipsIII:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
{
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*r3900:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*r3900:
{
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
*mipsIV:
*mipsV:
*mips32:
+*mips32r2:
*mips64:
+*mips64r2:
*vr4100:
*vr5000:
-\f
+
+:include:::mips3264r2.igen
:include:::m16.igen
+:include:::m16e.igen
:include:::mdmx.igen
+:include:::mips3d.igen
:include:::sb1.igen
:include:::tx.igen
:include:::vr.igen
-\f
+:include:::dsp.igen
+:include:::dsp2.igen
+:include:::smartmips.igen
+
projects / deliverable / binutils-gdb.git / blobdiff