* Inserted skeleton of R5900 COP2 simulation. Merged old vu[01].[ch] code

[deliverable/binutils-gdb.git] / sim / mips / mips.igen

diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen
index f84519d26349b7897a2c7a3467df01c5327b345c..603ec81f9fe89e3c8726cd05420a4cee003191f9 100644 (file)
--- a/sim/mips/mips.igen
+++ b/sim/mips/mips.igen
@@ -1,3 +1,5 @@
+// -*- C -*-
+//
 //    <insn> ::=
 //        <insn-word> { "+" <insn-word> }
 //        ":" <format-name>
@@ -12,14 +14,14 @@
 
 
 // IGEN config - mips16
-:option:16::insn-bit-size:16
-:option:16::hi-bit-nr:15
+// :option:16::insn-bit-size:16
+// :option:16::hi-bit-nr:15
 :option:16::insn-specifying-widths:true
 :option:16::gen-delayed-branch:false
 
 // IGEN config - mips32/64..
-:option:32::insn-bit-size:32
-:option:32::hi-bit-nr:31
+// :option:32::insn-bit-size:32
+// :option:32::hi-bit-nr:31
 :option:32::insn-specifying-widths:true
 :option:32::gen-delayed-branch:false
 
@@ -29,37 +31,48 @@
 
 
 // Models known by this simulator
-:model:::mipsI:mipsI:
-:model:::mipsII:mipsII:
-:model:::mipsIII:mipsIII:
-:model:::mipsIV:mipsIV:
+:model:::mipsI:mips3000:
+:model:::mipsII:mips6000:
+:model:::mipsIII:mips4000:
+:model:::mipsIV:mips8000:
 :model:::mips16:mips16:
 // start-sanitize-r5900
-:model:::r5900:r5900:
+:model:::r5900:mips5900:
 // end-sanitize-r5900
-:model:::r3900:r3900:
+:model:::r3900:mips3900:
 // start-sanitize-tx19
 :model:::tx19:tx19:
 // end-sanitize-tx19
+// start-sanitize-vr4320
+:model:::vr4320:mips4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
-:model:::vr5400:vr5400:
+:model:::vr5400:mips5400:
+:model:::mdmx:mdmx:
 // end-sanitize-vr5400
+:model:::vr5000:mips5000:
 
 
 
 // Pseudo instructions known by IGEN
 :internal::::illegal:
 {
-  sim_io_eprintf (SD, "Illegal instruction at address 0x%lx\n",
-                 (unsigned long) CIA);
-  sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIGILL);
+  SignalException (ReservedInstruction, 0);
 }
 
 
+// Pseudo instructions known by interp.c
+// For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
+000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
+"rsvd <OP>"
+{
+  SignalException (ReservedInstruction, instruction_0);
+}
+
 
 
 //
-// MIPS Architecture:
+// Mips Architecture:
 //
 //        CPU Instruction Set (mipsI - mipsIV)
 //
@@ -67,10 +80,11 @@
 
 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
 "add r<RD>, r<RS>, r<RT>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -90,10 +104,11 @@
 
 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
 "addi r<RT>, r<RS>, IMMEDIATE"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -112,11 +127,12 @@
 
 
 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
-"add r<RT>, r<RS>, IMMEDIATE"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+"add r<RT>, r<RS>, <IMMEDIATE>"
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -134,10 +150,11 @@
 
 
 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -156,10 +173,11 @@
 
 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
 "and r<RD>, r<RS>, r<RT>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -176,10 +194,12 @@
 
 
 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
-"and r<RT>, r<RS>, IMMEDIATE"
-*mipsI:
-*mipsII:
-*mipsIII:
+"and r<RT>, r<RS>, <IMMEDIATE>"
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -196,11 +216,12 @@
 
 
 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
-"beq r<RS>, r<RT>, OFFSET"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+"beq r<RS>, r<RT>, <OFFSET>"
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -213,8 +234,8 @@
 // end-sanitize-tx19
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
-  if (GPR[RS] == GPR[RT])
-    DELAY_SLOT (PC + offset);
+  if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
+    DELAY_SLOT (NIA + offset);
 }
 
 
@@ -223,6 +244,10 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -235,8 +260,8 @@
 // end-sanitize-tx19
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
-  if (GPR[RS] == GPR[RT])
-    DELAY_SLOT (PC + offset);
+  if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
+    DELAY_SLOT (NIA + offset);
   else
     NULLIFY_NEXT_INSTRUCTION ();
 }
@@ -244,10 +269,11 @@
 
 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
 "bgez r<RS>, <OFFSET>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -260,17 +286,18 @@
 // end-sanitize-tx19
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
-  if (GPR[RS] >= 0)
-    DELAY_SLOT (PC + offset);
+  if ((signed_word) GPR[RS] >= 0)
+    DELAY_SLOT (NIA + offset);
 }
 
 
 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
 "bgezal r<RS>, <OFFSET>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -284,8 +311,8 @@
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
   RA = (CIA + 8);
-  if (GPR[RS] >= 0)
-    DELAY_SLOT (PC + offset);
+  if ((signed_word) GPR[RS] >= 0)
+    DELAY_SLOT (NIA + offset);
 }
 
 
@@ -294,6 +321,10 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -309,8 +340,8 @@
   RA = (CIA + 8);
   /* NOTE: The branch occurs AFTER the next instruction has been
      executed */
-  if (GPR[RS] >= 0)
-    DELAY_SLOT (PC + offset);
+  if ((signed_word) GPR[RS] >= 0)
+    DELAY_SLOT (NIA + offset);
   else
     NULLIFY_NEXT_INSTRUCTION ();
 }
@@ -321,6 +352,10 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -333,8 +368,8 @@
 // end-sanitize-tx19
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
-  if (GPR[RS] >= 0)
-    DELAY_SLOT (PC + offset);
+  if ((signed_word) GPR[RS] >= 0)
+    DELAY_SLOT (NIA + offset);
   else
     NULLIFY_NEXT_INSTRUCTION ();
 }
@@ -342,10 +377,11 @@
 
 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
 "bgtz r<RS>, <OFFSET>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -358,8 +394,8 @@
 // end-sanitize-tx19
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
-  if (GPR[RS] > 0)
-    DELAY_SLOT (PC + offset);
+  if ((signed_word) GPR[RS] > 0)
+    DELAY_SLOT (NIA + offset);
 }
 
 
@@ -368,6 +404,10 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -382,8 +422,8 @@
   address_word offset = EXTEND16 (OFFSET) << 2;
   /* NOTE: The branch occurs AFTER the next instruction has been
      executed */
-  if (GPR[RS] > 0)
-    DELAY_SLOT (PC + offset);
+  if ((signed_word) GPR[RS] > 0)
+    DELAY_SLOT (NIA + offset);
   else
     NULLIFY_NEXT_INSTRUCTION ();
 }
@@ -391,10 +431,11 @@
 
 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
 "blez r<RS>, <OFFSET>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -409,8 +450,8 @@
   address_word offset = EXTEND16 (OFFSET) << 2;
   /* NOTE: The branch occurs AFTER the next instruction has been
      executed */
-  if (GPR[RS] <= 0)
-    DELAY_SLOT (PC + offset);
+  if ((signed_word) GPR[RS] <= 0)
+    DELAY_SLOT (NIA + offset);
 }
 
 
@@ -419,6 +460,10 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -431,8 +476,8 @@
 // end-sanitize-tx19
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
-  if (GPR[RS] <= 0)
-    DELAY_SLOT (PC + offset);
+  if ((signed_word) GPR[RS] <= 0)
+    DELAY_SLOT (NIA + offset);
   else
     NULLIFY_NEXT_INSTRUCTION ();
 }
@@ -440,10 +485,11 @@
 
 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
 "bltz r<RS>, <OFFSET>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -456,17 +502,18 @@
 // end-sanitize-tx19
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
-  if (GPR[RS] < 0)
-    DELAY_SLOT (PC + offset);
+  if ((signed_word) GPR[RS] < 0)
+    DELAY_SLOT (NIA + offset);
 }
 
 
 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
 "bltzal r<RS>, <OFFSET>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -482,8 +529,8 @@
   RA = (CIA + 8);
   /* NOTE: The branch occurs AFTER the next instruction has been
      executed */
-  if (GPR[RS] < 0)
-    DELAY_SLOT (PC + offset);
+  if ((signed_word) GPR[RS] < 0)
+    DELAY_SLOT (NIA + offset);
 }
 
 
@@ -492,6 +539,10 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -505,8 +556,8 @@
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
   RA = (CIA + 8);
-  if (GPR[RS] < 0)
-    DELAY_SLOT (PC + offset);
+  if ((signed_word) GPR[RS] < 0)
+    DELAY_SLOT (NIA + offset);
   else
     NULLIFY_NEXT_INSTRUCTION ();
 }
@@ -517,6 +568,10 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -531,8 +586,8 @@
   address_word offset = EXTEND16 (OFFSET) << 2;
   /* NOTE: The branch occurs AFTER the next instruction has been
      executed */
-  if (GPR[RS] < 0)
-    DELAY_SLOT (PC + offset);
+  if ((signed_word) GPR[RS] < 0)
+    DELAY_SLOT (NIA + offset);
   else
     NULLIFY_NEXT_INSTRUCTION ();
 }
@@ -540,10 +595,11 @@
 
 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
 "bne r<RS>, r<RT>, <OFFSET>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -556,8 +612,8 @@
 // end-sanitize-tx19
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
-  if (GPR[RS] != GPR[RT])
-    DELAY_SLOT (PC + offset);
+  if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
+    DELAY_SLOT (NIA + offset);
 }
 
 
@@ -566,6 +622,10 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -578,8 +638,8 @@
 // end-sanitize-tx19
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
-  if (GPR[RS] != GPR[RT])
-    DELAY_SLOT (PC + offset);
+  if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
+    DELAY_SLOT (NIA + offset);
   else
     NULLIFY_NEXT_INSTRUCTION ();
 }
@@ -587,10 +647,11 @@
 
 000000,20.CODE,001101:SPECIAL:32::BREAK
 "break"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -608,13 +669,7 @@
 
 0100,ZZ!0!1!3,26.COP_FUN:NORMAL:32::COPz
 "cop<ZZ> <COP_FUN>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
+*mipsI,mipsII,mipsIII,mipsIV:
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -631,6 +686,10 @@
 "dadd r<RD>, r<RS>, r<RT>"
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -642,9 +701,10 @@
 *tx19:
 // end-sanitize-tx19
 {
+  /* this check's for overflow */
   ALU64_BEGIN (GPR[RS]);
   ALU64_ADD (GPR[RT]);
-  ALU64_END (GPR[RT]);
+  ALU64_END (GPR[RD]);
 }
 
 
@@ -652,6 +712,10 @@
 "daddi r<RT>, r<RS>, <IMMEDIATE>"
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -673,6 +737,10 @@
 "daddu r<RT>, r<RS>, <IMMEDIATE>"
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -692,6 +760,10 @@
 "daddu r<RD>, r<RS>, r<RT>"
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -711,6 +783,10 @@
 "ddiv r<RS>, r<RT>"
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -751,6 +827,10 @@
 *mipsIII:
 *mipsIV:
 *r3900:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -778,10 +858,11 @@
 
 000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
 "div r<RS>, r<RT>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -802,7 +883,7 @@
        LO = EXTEND32 (0x80000000);
        HI = EXTEND32 (0);
       }
-    else if (d == -1 && d == 0x80000000)
+    else if (n == SIGNED32 (0x80000000) && d == -1)
       {
        LO = EXTEND32 (0x80000000);
        HI = EXTEND32 (0);
@@ -818,10 +899,11 @@
 
 000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
 "divu r<RS>, r<RT>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -851,111 +933,127 @@
 }
 
 
+:function:::void:do_dmult:int rs, int rt, int rd, int signed_p
+{
+  unsigned64 lo;
+  unsigned64 hi;
+  unsigned64 m00;
+  unsigned64 m01;
+  unsigned64 m10;
+  unsigned64 m11;
+  unsigned64 mid;
+  int sign;
+  unsigned64 op1 = GPR[rs];
+  unsigned64 op2 = GPR[rt];
+  CHECKHILO ("Multiplication");
+  /* make signed multiply unsigned */ 
+  sign = 0;
+  if (signed_p)
+    {
+      if (op1 < 0)
+       {
+         op1 = - op1;
+         ++sign;
+       }
+      if (op2 < 0)
+       {
+         op2 = - op2;
+         ++sign;
+       }
+    }
+  /* multuply out the 4 sub products */
+  m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
+  m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
+  m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
+  m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
+  /* add the products */
+  mid = ((unsigned64) VH4_8 (m00)
+        + (unsigned64) VL4_8 (m10)
+        + (unsigned64) VL4_8 (m01));
+  lo = U8_4 (mid, m00);
+  hi = (m11
+       + (unsigned64) VH4_8 (mid)
+       + (unsigned64) VH4_8 (m01)
+       + (unsigned64) VH4_8 (m10));
+  /* fix the sign */
+  if (sign & 1)
+    {
+      lo = -lo;
+      if (lo == 0)
+       hi = -hi;
+      else
+       hi = -hi - 1;
+    }
+  /* save the result HI/LO (and a gpr) */
+  LO = lo;
+  HI = hi;
+  if (rd != 0)
+    GPR[rd] = lo;
+}
+
+
 000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
 "dmult r<RS>, r<RT>"
-*mipsIII:
-*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
+*mipsIII,mipsIV:
 *r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 {
-  CHECKHILO ("Multiplication");
-  {
-    signed64 op1 = GPR[RS];
-    signed64 op2 = GPR[RT];
-    unsigned64 lo;
-    unsigned64 hi;
-    unsigned64 m00;
-    unsigned64 m01;
-    unsigned64 m10;
-    unsigned64 m11;
-    unsigned64 mid;
-    int sign = 0;
-    /* make it unsigned */
-    if (op1 < 0)
-      {
-       op1 = - op1;
-       ++sign;
-      }
-    if (op2 < 0)
-      {
-       op2 = - op2;
-       ++sign;
-      }
-    /* multuply out the 4 sub products */
-    m00 = (VL4_8 (op1) * VL4_8 (op2));
-    m10 = (VH4_8 (op1) * VL4_8 (op2));
-    m01 = (VL4_8 (op1) * VH4_8 (op2));
-    m11 = (VH4_8 (op1) * VH4_8 (op2));
-    /* add the products */
-    mid = VH4_8 (m00) + VL4_8 (m10) + VL4_8 (m01);
-    lo = U8_4 (mid, m00);
-    hi = m11 + VH4_8 (mid) + VH4_8 (m01) + VH4_8 (m10);
-    /* save the result */
-    if (sign & 1)
-      {
-       LO = -lo;
-       if (lo == 0)
-         HI = -hi;
-       else
-         HI = -hi - 1;
-      }
-    else
-      {
-       LO = lo;
-       HI = hi;
-      }
-  }
+  do_dmult (SD_, RS, RT, 0, 1);
 }
 
-
-000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
-"dmultu r<RS>, r<RT>"
-*mipsIII:
-*mipsIV:
+000000,5.RS,5.RT,5.RD,00000011100:SPECIAL:64::DMULT
+"dmult r<RS>, r<RT>":RD == 0
+"dmult r<RD>, r<RS>, r<RT>"
+*vr5000:
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
+{
+  do_dmult (SD_, RS, RT, RD, 1);
+}
+
+
+
+000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
+"dmultu r<RS>, r<RT>"
+*mipsIII,mipsIV:
 *r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 {
-  CHECKHILO ("Multiplication");
-  {
-    signed64 op1 = GPR[RS];
-    signed64 op2 = GPR[RT];
-    unsigned64 lo;
-    unsigned64 hi;
-    unsigned64 m00;
-    unsigned64 m01;
-    unsigned64 m10;
-    unsigned64 m11;
-    unsigned64 mid;
-    /* multuply out the 4 sub products */
-    m00 = (VL4_8 (op1) * VL4_8 (op2));
-    m10 = (VH4_8 (op1) * VL4_8 (op2));
-    m01 = (VL4_8 (op1) * VH4_8 (op2));
-    m11 = (VH4_8 (op1) * VH4_8 (op2));
-    /* add the products */
-    mid = VH4_8 (m00) + VL4_8 (m10) + VL4_8 (m01);
-    lo = U8_4 (mid, m00);
-    hi = m11 + VH4_8 (mid) + VH4_8 (m01) + VH4_8 (m10);
-    /* save the result */
-    LO = lo;
-    HI = hi;
-  }
+  do_dmult (SD_, RS, RT, 0, 0);
+}
+
+000000,5.RS,5.RT,5.RD,00000011101:SPECIAL:64::DMULTU
+"dmultu r<RD>, r<RS>, r<RT>":RD == 0
+"dmultu r<RS>, r<RT>"
+*vr5000:
+// start-sanitize-vr5400
+*vr5400:
+// end-sanitize-vr5400
+{
+  do_dmult (SD_, RS, RT, RD, 0);
 }
 
 
+
 00000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
-"dsll r<RD>, r<RT>, <SA>"
+"dsll r<RD>, r<RT>, <SHIFT>"
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -967,15 +1065,19 @@
 *tx19:
 // end-sanitize-tx19
 {
-  int s = SA;
+  int s = SHIFT;
   GPR[RD] = GPR[RT] << s;
 }
 
 
 00000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
-"dsll32 r<RD>, r<RT>, <SA>"
+"dsll32 r<RD>, r<RT>, <SHIFT>"
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -987,7 +1089,7 @@
 *tx19:
 // end-sanitize-tx19
 {
-  int s = 32 + SA;
+  int s = 32 + SHIFT;
   GPR[RD] = GPR[RT] << s;
 }
 
@@ -996,6 +1098,10 @@
 "dsllv r<RD>, r<RT>, r<RS>"
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -1013,9 +1119,13 @@
 
 
 00000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
-"dsra r<RD>, r<RT>, <SA>"
+"dsra r<RD>, r<RT>, <SHIFT>"
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -1027,15 +1137,19 @@
 *tx19:
 // end-sanitize-tx19
 {
-  int s = SA;
+  int s = SHIFT;
   GPR[RD] = ((signed64) GPR[RT]) >> s;
 }
 
 
 00000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
-"dsra32 r<RT>, r<RD>, <SA>"
+"dsra32 r<RT>, r<RD>, <SHIFT>"
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -1047,7 +1161,7 @@
 *tx19:
 // end-sanitize-tx19
 {
-  int s = 32 + SA;
+  int s = 32 + SHIFT;
   GPR[RD] = ((signed64) GPR[RT]) >> s;
 }
 
@@ -1056,6 +1170,10 @@
 "dsra32 r<RT>, r<RD>, r<RS>"
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -1073,9 +1191,13 @@
 
 
 00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
-"dsrav r<RD>, r<RT>, <SA>"
+"dsrav r<RD>, r<RT>, <SHIFT>"
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -1087,15 +1209,19 @@
 *tx19:
 // end-sanitize-tx19
 {
-  int s = SA;
+  int s = SHIFT;
   GPR[RD] = (unsigned64) GPR[RT] >> s;
 }
 
 
 00000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
-"dsrl32 r<RD>, r<RT>, <SA>"
+"dsrl32 r<RD>, r<RT>, <SHIFT>"
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -1107,7 +1233,7 @@
 *tx19:
 // end-sanitize-tx19
 {
-  int s = 32 + SA;
+  int s = 32 + SHIFT;
   GPR[RD] = (unsigned64) GPR[RT] >> s;
 }
 
@@ -1116,6 +1242,10 @@
 "dsrl32 r<RD>, r<RT>, r<RS>"
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -1136,6 +1266,10 @@
 "dsub r<RD>, r<RS>, r<RT>"
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -1157,6 +1291,10 @@
 "dsubu r<RD>, r<RS>, r<RT>"
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -1174,10 +1312,11 @@
 
 000010,26.INSTR_INDEX:NORMAL:32::J
 "j <INSTR_INDEX>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -1198,10 +1337,11 @@
 
 000011,26.INSTR_INDEX:NORMAL:32::JAL
 "jal <INSTR_INDEX>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -1224,10 +1364,11 @@
 000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
 "jalr r<RS>":RD == 31
 "jalr r<RD>, r<RS>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -1247,10 +1388,11 @@
 
 000000,5.RS,000000000000000001000:SPECIAL:32::JR
 "jr r<RS>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -1266,12 +1408,32 @@
 }
 
 
+:function:::void:do_load_byte:address_word gpr_base, int rt, signed16 offset
+{
+  address_word vaddr = offset + gpr_base;
+  address_word paddr;
+  int uncached;
+  if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
+    {
+      unsigned64 memval = 0;
+      address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+      unsigned int reverse = (ReverseEndian ? mask : 0);
+      unsigned int bigend = (BigEndianCPU ? mask : 0);
+      unsigned int byte;
+      paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
+      LoadMemory (&memval, NULL, uncached, AccessLength_BYTE, paddr, vaddr, isDATA, isREAL);
+      byte = ((vaddr & mask) ^ bigend);
+      GPR[rt] = EXTEND8 ((memval >> (8 * byte)));
+    }
+}
+
 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
 "lb r<RT>, <OFFSET>(r<BASE>)"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -1283,6 +1445,8 @@
 *tx19:
 // end-sanitize-tx19
 {
+  do_load_byte (SD_, GPR[BASE], RT, OFFSET);
+#if 0
   unsigned32 instruction = instruction_0;
   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
   int destreg = ((instruction >> 16) & 0x0000001F);
@@ -1308,15 +1472,17 @@
        }
     }
   }
+#endif
 }
 
 
 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
 "lbu r<RT>, <OFFSET>(r<BASE>)"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -1360,6 +1526,10 @@
 "ld r<RT>, <OFFSET>(r<BASE>)"
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -1400,12 +1570,13 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
 // start-sanitize-tx19
 *tx19:
@@ -1435,10 +1606,46 @@
 }
 
 
+// start-sanitize-sky
+110110,5.BASE,5.RT,16.OFFSET:NORMAL:64::LQC2
+"lqc2 r<RT>, <OFFSET>(r<BASE>)"
+*r5900:
+{
+  unsigned32 instruction = instruction_0;
+  signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
+  int destreg = ((instruction >> 16) & 0x0000001F);
+  signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
+  {
+    address_word vaddr = ((unsigned64)op1 + offset);
+    address_word paddr;
+    int uncached;
+    if ((vaddr & 0x0f) != 0)
+      SignalExceptionAddressLoad();
+    else
+      {
+       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
+         {
+           unsigned64 memval = 0;
+           unsigned64 memval1 = 0;
+           unsigned128 qw = U16_8(memval, memval1); /* XXX: check order */
+           /* XXX: block on VU0 pipeline if necessary */
+           LoadMemory(&memval,&memval1,uncached,AccessLength_QUADWORD,paddr,vaddr,isDATA,isREAL);
+           COP_LQ(((instruction >> 26) & 0x3),destreg,qw);;
+         }
+      }
+  }
+}
+// end-sanitize-sky
+
+
 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
 "ldl r<RT>, <OFFSET>(r<BASE>)"
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -1469,7 +1676,7 @@
          int byte;
          paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
          byte = ((vaddr & mask) ^ bigend);
-         if (!!ByteSwapMem)
+         if (!BigEndianMem)
            paddr &= ~mask;
          LoadMemory(&memval,&memval1,uncached,byte,paddr,vaddr,isDATA,isREAL);
          GPR[destreg] = ((memval << ((7 - byte) * 8)) | (GPR[destreg] & (((unsigned64)1 << ((7 - byte) * 8)) - 1)));
@@ -1483,6 +1690,10 @@
 "ldr r<RT>, <OFFSET>(r<BASE>)"
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -1513,7 +1724,7 @@
          int byte;
          paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
          byte = ((vaddr & mask) ^ bigend);
-         if (!ByteSwapMem)
+         if (BigEndianMem)
            paddr &= ~mask;
          LoadMemory(&memval,&memval1,uncached,(7 - byte),paddr,vaddr,isDATA,isREAL);
          {
@@ -1532,10 +1743,11 @@
 
 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
 "lh r<RT>, <OFFSET>(r<BASE>)"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -1580,10 +1792,11 @@
 
 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
 "lhu r<RT>, <OFFSET>(r<BASE>)"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -1631,6 +1844,10 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -1678,6 +1895,10 @@
 "lld r<RT>, <OFFSET>(r<BASE>)"
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -1716,10 +1937,11 @@
 
 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
 "lui r<RT>, <IMMEDIATE>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -1737,10 +1959,11 @@
 
 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
 "lw r<RT>, <OFFSET>(r<BASE>)"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -1785,10 +2008,11 @@
 
 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -1833,10 +2057,11 @@
 
 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
 "lwl r<RT>, <OFFSET>(r<BASE>)"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -1867,7 +2092,7 @@
          int byte;
          paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
          byte = ((vaddr & mask) ^ bigend);
-         if (!!ByteSwapMem)
+         if (!BigEndianMem)
            paddr &= ~mask;
          LoadMemory(&memval,&memval1,uncached,byte,paddr,vaddr,isDATA,isREAL);
          if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
@@ -1883,10 +2108,11 @@
 
 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
 "lwr r<RT>, <OFFSET>(r<BASE>)"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -1917,7 +2143,7 @@
          int byte;
          paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
          byte = ((vaddr & mask) ^ bigend);
-         if (!ByteSwapMem)
+         if (BigEndianMem)
            paddr &= ~mask;
          LoadMemory(&memval,&memval1,uncached,(3 - byte),paddr,vaddr,isDATA,isREAL);
          if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
@@ -1942,6 +2168,10 @@
 "lwu r<RT>, <OFFSET>(r<BASE>)"
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -1986,10 +2216,11 @@
 
 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
 "mfhi r<RD>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2002,16 +2233,19 @@
 // end-sanitize-tx19
 {
   GPR[RD] = HI;
+#if 0
   HIACCESS = 3;
+#endif
 }
 
 
 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
 "mflo r<RD>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2024,13 +2258,19 @@
 // end-sanitize-tx19
 {
   GPR[RD] = LO;
+#if 0
   LOACCESS = 3; /* 3rd instruction will be safe */
+#endif
 }
 
 
 000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN
 "movn r<RD>, r<RS>, r<RT>"
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2046,6 +2286,10 @@
 000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ
 "movz r<RD>, r<RS>, r<RT>"
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2060,10 +2304,11 @@
 
 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
 "mthi r<RS>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2075,19 +2320,24 @@
 *tx19:
 // end-sanitize-tx19
 {
+#if 0
   if (HIACCESS != 0)
     sim_io_eprintf (sd, "MT (move-to) over-writing HI register value\n");
+#endif
   HI = GPR[RS];
+#if 0
   HIACCESS = 3; /* 3rd instruction will be safe */
+#endif
 }
 
 
 000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
 "mtlo r<RS>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2099,19 +2349,36 @@
 *tx19:
 // end-sanitize-tx19
 {
+#if 0
   if (LOACCESS != 0)
     sim_io_eprintf (sd, "MT (move-to) over-writing LO register value\n");
+#endif
   LO = GPR[RS];
+#if 0
   LOACCESS = 3; /* 3rd instruction will be safe */
+#endif
 }
 
 
-000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
+000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
 "mult r<RS>, r<RT>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
+{
+  signed64 prod;
+  CHECKHILO ("Multiplication");
+  prod = (((signed64)(signed32) GPR[RS])
+         * ((signed64)(signed32) GPR[RT]));
+  LO = EXTEND32 (VL4_8 (prod));
+  HI = EXTEND32 (VH4_8 (prod));
+}
+
+
+000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
+"mult r<RD>, r<RS>, r<RT>"
+*vr5000:
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2129,15 +2396,28 @@
          * ((signed64)(signed32) GPR[RT]));
   LO = EXTEND32 (VL4_8 (prod));
   HI = EXTEND32 (VH4_8 (prod));
+  if (RD != 0)
+    GPR[RD] = LO;
 }
 
 
-000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
+000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU
 "multu r<RS>, r<RT>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
+{
+  unsigned64 prod;
+  CHECKHILO ("Multiplication");
+  prod = (((unsigned64)(unsigned32) GPR[RS])
+         * ((unsigned64)(unsigned32) GPR[RT]));
+  LO = EXTEND32 (VL4_8 (prod));
+  HI = EXTEND32 (VH4_8 (prod));
+}
+000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
+"multu r<RD>, r<RS>, r<RT>"
+*vr5000:
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2155,15 +2435,18 @@
          * ((unsigned64)(unsigned32) GPR[RT]));
   LO = EXTEND32 (VL4_8 (prod));
   HI = EXTEND32 (VH4_8 (prod));
+  if (RD != 0)
+    GPR[RD] = LO;
 }
 
 
 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
 "nor r<RD>, r<RS>, r<RT>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2181,10 +2464,11 @@
 
 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
 "or r<RD>, r<RS>, r<RT>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2202,10 +2486,11 @@
 
 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
 "ori r<RT>, r<RS>, <IMMEDIATE>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2223,6 +2508,10 @@
 
 110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2247,10 +2536,11 @@
 
 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
 "sb r<RT>, <OFFSET>(r<BASE>)"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2297,6 +2587,10 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2344,6 +2638,10 @@
 "scd r<RT>, <OFFSET>(r<BASE>)"
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2387,6 +2685,10 @@
 "sd r<RT>, <OFFSET>(r<BASE>)"
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2429,6 +2731,10 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2466,10 +2772,50 @@
 }
 
 
+// start-sanitize-sky
+111010,5.BASE,5.RT,16.OFFSET:NORMAL:64::SQC2
+"sqc2 r<RT>, <OFFSET>(r<BASE>)"
+*r5900:
+{
+  unsigned32 instruction = instruction_0;
+  signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
+  int destreg = ((instruction >> 16) & 0x0000001F);
+  signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
+  {
+    address_word vaddr = ((unsigned64)op1 + offset);
+    address_word paddr;
+    int uncached;
+    if ((vaddr & 0x0f) != 0)
+      SignalExceptionAddressStore();
+    else
+      {
+       if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
+         {
+           unsigned128 qw;
+           unsigned64 memval0 = 0;
+           unsigned64 memval1 = 0;
+           qw = COP_SQ(((instruction >> 26) & 0x3),destreg);
+           memval0 = *A8_16(& qw, 0);
+           memval1 = *A8_16(& qw, 1);
+           {
+             StoreMemory(uncached,AccessLength_WORD,memval0,memval1,paddr,vaddr,isREAL);
+           }
+         }
+      }
+  }
+}
+// end-sanitize-sky
+
+
+
 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
 "sdl r<RT>, <OFFSET>(r<BASE>)"
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2500,7 +2846,7 @@
          int byte;
          paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
          byte = ((vaddr & mask) ^ bigend);
-         if (!!ByteSwapMem)
+         if (!BigEndianMem)
            paddr &= ~mask;
          memval = (op2 >> (8 * (7 - byte)));
          StoreMemory(uncached,byte,memval,memval1,paddr,vaddr,isREAL);
@@ -2514,6 +2860,10 @@
 "sdr r<RT>, <OFFSET>(r<BASE>)"
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2525,41 +2875,31 @@
 *tx19:
 // end-sanitize-tx19
 {
-  unsigned32 instruction = instruction_0;
-  signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
-  signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
-  signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
-  {
-    address_word vaddr = ((unsigned64)op1 + offset);
-    address_word paddr;
-    int uncached;
-    {
-      if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
-       {
-         unsigned64 memval = 0;
-         unsigned64 memval1 = 0;
-         unsigned64 mask = 7;
-         unsigned int reverse = (ReverseEndian ? mask : 0);
-         unsigned int bigend = (BigEndianCPU ? mask : 0);
-         int byte;
-         paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
-         byte = ((vaddr & mask) ^ bigend);
-         if (!ByteSwapMem)
-           paddr &= ~mask;
-         memval = ((unsigned64) op2 << (byte * 8));
-         StoreMemory(uncached,(AccessLength_DOUBLEWORD - byte),memval,memval1,paddr,vaddr,isREAL);
-       }
-    }
-  }
+  address_word paddr;
+  int uncached;
+  unsigned64 memval;
+  unsigned64 mask = 7;
+  unsigned int reverse = (ReverseEndian ? mask : 0);
+  unsigned int bigend = (BigEndianCPU ? mask : 0);
+  int byte;
+  address_word vaddr = (GPR[BASE] + EXTEND16 (OFFSET));
+  AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL);
+  paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
+  if (BigEndianMem)
+    paddr &= ~mask;
+  byte = ((vaddr & mask) ^ bigend);
+  memval = (GPR[RT] << (byte * 8));
+  StoreMemory(uncached,(AccessLength_DOUBLEWORD - byte),memval,0,paddr,vaddr,isREAL);
 }
 
 
 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
 "sh r<RT>, <OFFSET>(r<BASE>)"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2606,10 +2946,11 @@
 
 00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
 "sll r<RD>, r<RT>, <SHIFT>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2629,10 +2970,11 @@
 
 000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
 "sllv r<RD>, r<RT>, r<RS>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2652,10 +2994,11 @@
 
 000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
 "slt r<RD>, r<RS>, r<RT>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2667,16 +3010,17 @@
 *tx19:
 // end-sanitize-tx19
 {
-  GPR[RD] = (GPR[RS] < GPR[RT]);
+  GPR[RD] = ((signed_word) GPR[RS] < (signed_word) GPR[RT]);
 }
 
 
 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
 "slti r<RT>, r<RS>, <IMMEDIATE>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2688,16 +3032,17 @@
 *tx19:
 // end-sanitize-tx19
 {
-  GPR[RT] = (GPR[RS] < EXTEND16 (IMMEDIATE));
+  GPR[RT] = ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE));
 }
 
 
 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2714,10 +3059,11 @@
 
 000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
 "sltu r<RD>, r<RS>, r<RT>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2735,10 +3081,11 @@
 
 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
 "sra r<RD>, r<RT>, <SHIFT>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2758,10 +3105,11 @@
 
 000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
 "srav r<RD>, r<RT>, r<RS>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2781,10 +3129,11 @@
 
 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
 "srl r<RD>, r<RT>, <SHIFT>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2804,10 +3153,11 @@
 
 000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
 "srlv r<RD>, r<RT>, r<RS>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2827,10 +3177,11 @@
 
 000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
 "sub r<RD>, r<RS>, r<RT>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2850,10 +3201,11 @@
 
 000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
 "subu r<RD>, r<RS>, r<RT>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2871,10 +3223,11 @@
 
 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
 "sw r<RT>, <OFFSET>(r<BASE>)"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2918,16 +3271,14 @@
 
 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
 // start-sanitize-tx19
 *tx19:
@@ -2965,10 +3316,11 @@
 
 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
 "swl r<RT>, <OFFSET>(r<BASE>)"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -2999,7 +3351,7 @@
          int byte;
          paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
          byte = ((vaddr & mask) ^ bigend);
-         if (!!ByteSwapMem)
+         if (!BigEndianMem)
            paddr &= ~mask;
          memval = (op2 >> (8 * (3 - byte)));
          if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
@@ -3014,10 +3366,11 @@
 
 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
 "swr r<RT>, <OFFSET>(r<BASE>)"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -3029,35 +3382,23 @@
 *tx19:
 // end-sanitize-tx19
 {
-  unsigned32 instruction = instruction_0;
-  signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
-  signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
-  signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
-  {
-    address_word vaddr = ((unsigned64)op1 + offset);
-    address_word paddr;
-    int uncached;
-    {
-      if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
-       {
-         unsigned64 memval = 0;
-         unsigned64 memval1 = 0;
-         unsigned64 mask = 3;
-         unsigned int reverse = (ReverseEndian ? mask : 0);
-         unsigned int bigend = (BigEndianCPU ? mask : 0);
-         int byte;
-         paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
-         byte = ((vaddr & mask) ^ bigend);
-         if (!ByteSwapMem)
-           paddr &= ~mask;
-         memval = ((unsigned64) op2 << (byte * 8));
-         if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2)) {
-           memval <<= 32;
-         }
-         StoreMemory(uncached,(AccessLength_WORD - byte),memval,memval1,paddr,vaddr,isREAL);
-       }
-    }
-  }
+  unsigned64 memval = 0;
+  unsigned64 mask = 3;
+  unsigned int reverse = (ReverseEndian ? mask : 0);
+  unsigned int bigend = (BigEndianCPU ? mask : 0);
+  int byte;
+  address_word paddr;
+  int uncached;
+  address_word vaddr = (GPR[BASE] + EXTEND16 (OFFSET));
+  AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL);
+  paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
+  if (BigEndianMem)
+    paddr &= ~mask;
+  byte = ((vaddr & mask) ^ bigend);
+  memval = (GPR[RT] << (byte * 8));
+  if ((vaddr & (1 << 2)) ^ (BigEndianCPU << 2))
+    memval <<= 32;
+  StoreMemory(uncached,(AccessLength_WORD - byte),memval,0,paddr,vaddr,isREAL);
 }
 
 
@@ -3067,6 +3408,10 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -3084,10 +3429,11 @@
 
 000000,20.CODE,001100:SPECIAL:32::SYSCALL
 "syscall <CODE>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -3108,6 +3454,10 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -3119,7 +3469,7 @@
 *tx19:
 // end-sanitize-tx19
 {
-  if (GPR[RS] == GPR[RT])
+  if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
     SignalException(Trap, instruction_0);
 }
 
@@ -3129,6 +3479,10 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -3140,7 +3494,7 @@
 *tx19:
 // end-sanitize-tx19
 {
-  if (GPR[RS] == EXTEND16 (IMMEDIATE))
+  if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
     SignalException(Trap, instruction_0);
 }
 
@@ -3150,6 +3504,10 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -3161,7 +3519,7 @@
 *tx19:
 // end-sanitize-tx19
 {
-  if (GPR[RS] >= GPR[RT])
+  if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
     SignalException(Trap, instruction_0);
 }
 
@@ -3171,6 +3529,10 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -3182,7 +3544,7 @@
 *tx19:
 // end-sanitize-tx19
 {
-  if (GPR[RS] >= EXTEND16 (IMMEDIATE))
+  if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
     SignalException(Trap, instruction_0);
 }
 
@@ -3192,6 +3554,10 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -3213,6 +3579,10 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -3234,6 +3604,10 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -3245,7 +3619,7 @@
 *tx19:
 // end-sanitize-tx19
 {
-  if (GPR[RS] < GPR[RT])
+  if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
     SignalException(Trap, instruction_0);
 }
 
@@ -3255,6 +3629,10 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -3266,7 +3644,7 @@
 *tx19:
 // end-sanitize-tx19
 {
-  if (GPR[RS] < EXTEND16 (IMMEDIATE))
+  if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
     SignalException(Trap, instruction_0);
 }
 
@@ -3276,6 +3654,10 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -3297,6 +3679,10 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -3318,6 +3704,10 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -3329,7 +3719,7 @@
 *tx19:
 // end-sanitize-tx19
 {
-  if (GPR[RS] != GPR[RT])
+  if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
     SignalException(Trap, instruction_0);
 }
 
@@ -3339,6 +3729,10 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -3350,17 +3744,18 @@
 *tx19:
 // end-sanitize-tx19
 {
-  if (GPR[RS] != EXTEND16 (IMMEDIATE))
+  if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
     SignalException(Trap, instruction_0);
 }
 
 
 000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
 "xor r<RD>, r<RS>, r<RT>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -3378,10 +3773,11 @@
 
 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
 "xori r<RT>, r<RS>, <IMMEDIATE>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -3416,6 +3812,16 @@
     }
 }
 
+:%s::::X:int x
+{
+  switch (x)
+    {
+    case 0: return "f";
+    case 1: return "t";
+    default: return "?";
+    }
+}
+
 :%s::::TF:int tf
 {
   if (tf)
@@ -3459,16 +3865,14 @@
 
 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
 "abs.%s<FMT> f<FD>, f<FS>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
 // start-sanitize-tx19
 *tx19:
@@ -3488,19 +3892,16 @@
 
 
 
-
-010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD
+010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
 // start-sanitize-tx19
 *tx19:
@@ -3520,124 +3921,140 @@
 }
 
 
-//
-// FIXME: This does not correctly resolve mipsI-mipsIV differences.
-//
+
 // BC1F
 // BC1FL
 // BC1T
 // BC1TL
-010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
-"bc1%s<TF>%s<ND> <OFFSET>":CC == 0
-"bc1%s<TF>%s<ND> <CC>, <OFFSET>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
+
+010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
+"bc1%s<TF>%s<ND> <OFFSET>"
+*mipsI,mipsII,mipsIII:
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
-  unsigned32 instruction = instruction_0;
-  signed_word offset = SIGNEXTEND((signed_word)(((instruction >> 0) & 0x0000FFFF) << 2),18);
-  int boolean = ((instruction >> 16) & 0x00000001);
-  int likely = ((instruction >> 17) & 0x00000001);
-  int condition_code = ((instruction >> 18) & 0x00000007);
-  {
-    if (condition_code != 0)
-      SignalException(ReservedInstruction,instruction);
-    else {
-      int condition = (PREVCOC1() == boolean);
-      /* NOTE: The branch occurs AFTER the next instruction has been executed */
-      if (condition) {
-       DELAY_SLOT (PC + offset);
-      }
-      else if (likely) {
-       NULLIFY_NEXT_INSTRUCTION ();
-      }
+  TRACE_BRANCH_INPUT (PREVCOC1());
+  if (PREVCOC1() == TF)
+    {
+      address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
+      TRACE_BRANCH_RESULT (dest);
+      DELAY_SLOT (dest);
+    }
+  else if (ND)
+    {
+      TRACE_BRANCH_RESULT (0);
+      NULLIFY_NEXT_INSTRUCTION ();
+    }
+  else
+    {
+      TRACE_BRANCH_RESULT (NIA);
     }
-  }
 }
 
-
-//
-// FIXME: This does not correctly differentiate between mips*
-//
-010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmt
-"c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
-"c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
-*mipsI:
-*mipsII:
-*mipsIII:
+010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
+"bc1%s<TF>%s<ND> <OFFSET>":CC == 0
+"bc1%s<TF>%s<ND> <CC>, <OFFSET>"
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
 {
-  unsigned32 instruction = instruction_0;
-  int cmpflags = ((instruction >> 0) & 0x0000000F);
-  int condition_code = ((instruction >> 8) & 0x00000007);
-  int fs = ((instruction >> 11) & 0x0000001F);
-  int ft = ((instruction >> 16) & 0x0000001F);
-  int format = ((instruction >> 21) & 0x00000007);
-  if (condition_code != 0)
+  if (GETFCC(CC) == TF)
     {
-      SignalException(ReservedInstruction,instruction);
+      DELAY_SLOT (NIA + (EXTEND16 (OFFSET) << 2));
     }
-  else
+  else if (ND)
     {
-      if ((format != fmt_single) && (format != fmt_double))
-       SignalException(ReservedInstruction,instruction);
-      else {
-       if (condition_code != 0)
-         SignalException(ReservedInstruction,instruction);
-       else
-         {
-           int ignore = 0;
-           int less = 0;
-           int equal = 0;
-           int unordered = 1;
-           unsigned64 ofs = ValueFPR(fs,format);
-           unsigned64 oft = ValueFPR(ft,format);
-           if (NaN(ofs,format) || NaN(oft,format)) {
-             if (FCSR & FP_ENABLE(IO)) {
-               FCSR |= FP_CAUSE(IO);
-               SignalExceptionFPE();
-               ignore = 1;
-             }
-           } else {
-             less = Less(ofs,oft,format);
-             equal = Equal(ofs,oft,format);
-             unordered = 0;
-           }
-           if (!ignore) {
-             int condition = (((cmpflags & (1 << 2)) && less) || ((cmpflags & (1 << 1)) && equal) || ((cmpflags & (1 << 0)) && unordered));
-             SETFCC(condition_code,condition);
+      NULLIFY_NEXT_INSTRUCTION ();
+    }
+}
+
+
+
+// C.EQ.S
+// C.EQ.D
+// ...
+
+:function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn
+{
+  if ((fmt != fmt_single) && (fmt != fmt_double))
+    SignalException (ReservedInstruction, insn);
+  else
+    {
+      int less;
+      int equal;
+      int unordered;
+      int condition;
+      unsigned64 ofs = ValueFPR (fs, fmt);
+      unsigned64 oft = ValueFPR (ft, fmt);
+      if (NaN (ofs, fmt) || NaN (oft, fmt))
+       {
+         if (FCSR & FP_ENABLE (IO))
+           {
+             FCSR |= FP_CAUSE (IO);
+             SignalExceptionFPE ();
            }
-         }
-      }
+         less = 0;
+         equal = 0;
+         unordered = 1;
+       }
+      else
+       {
+         less = Less (ofs, oft, fmt);
+         equal = Equal (ofs, oft, fmt);
+         unordered = 0;
+       }
+      condition = (((cond & (1 << 2)) && less)
+                  || ((cond & (1 << 1)) && equal)
+                  || ((cond & (1 << 0)) && unordered));
+      SETFCC (cc, condition);
     }
 }
 
+010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32::C.cond.fmt
+*mipsI,mipsII,mipsIII:
+"c.%s<COND>.%s<FMT> f<FS>, f<FT>":
+{
+  do_c_cond_fmt (SD_, FMT, FT, FS, 0, COND, instruction_0);
+}
+
+010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmt
+"c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
+"c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
+*mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
+// start-sanitize-vr5400
+*vr5400:
+// end-sanitize-vr5400
+*r3900:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+  do_c_cond_fmt (SD_, FMT, FT, FS, CC, COND, instruction_0);
+}
+
 
 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64::CEIL.L.fmt
 "ceil.l.%s<FMT> f<FD>, f<FS>"
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -3666,6 +4083,10 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -3692,11 +4113,37 @@
 
 // CFC1
 // CTC1
-01000100,x,10,kkkkk,vvvvv,00000000000:COP1S:32::CxC1
+010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
+"c%s<X>c1 r<RT>, f<FS>"
 *mipsI:
 *mipsII:
 *mipsIII:
+{
+  if (X)
+    {
+      if (FS == 0)
+       PENDING_FILL((FS + FCR0IDX),VL4_8(GPR[RT]));
+      else if (FS == 31)
+       PENDING_FILL((FS + FCR31IDX),VL4_8(GPR[RT]));
+      /* else NOP */
+      PENDING_FILL(COCIDX,0); /* special case */
+    }
+  else
+    { /* control from */
+      if (FS == 0)
+       PENDING_FILL(RT,SIGNEXTEND(FCR0,32));
+      else if (FS == 31)
+       PENDING_FILL(RT,SIGNEXTEND(FCR31,32));
+      /* else NOP */
+    }
+}
+010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
+"c%s<X>c1 r<RT>, f<FS>"
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -3708,26 +4155,42 @@
 *tx19:
 // end-sanitize-tx19
 {
-  unsigned32 instruction = instruction_0;
-  int fs = ((instruction >> 11) & 0x0000001F);
-  int ft = ((instruction >> 16) & 0x0000001F);
-  int to = ((instruction >> 23) & 0x00000001);
-  {
-    if (to) {
-      if (fs == 0) {
-       PENDING_FILL((fs + FCR0IDX),VL4_8(GPR[ft]));
-      } else if (fs == 31) {
-       PENDING_FILL((fs + FCR31IDX),VL4_8(GPR[ft]));
-      } /* else NOP */
-      PENDING_FILL(COCIDX,0); /* special case */
-    } else { /* control from */
-      if (fs == 0) {
-       PENDING_FILL(ft,SIGNEXTEND(FCR0,32));
-      } else if (fs == 31) {
-       PENDING_FILL(ft,SIGNEXTEND(FCR31,32));
-      } /* else NOP */
+  if (X)
+    {
+      /* control to */
+      TRACE_ALU_INPUT1 (GPR[RT]);
+      if (FS == 0)
+       {
+         FCR0 = VL4_8(GPR[RT]);
+         TRACE_ALU_RESULT (FCR0);
+       }
+      else if (FS == 31)
+       {
+         FCR31 = VL4_8(GPR[RT]);
+         SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
+         TRACE_ALU_RESULT (FCR31);
+       }
+      else
+       {
+         TRACE_ALU_RESULT0 ();
+       }
+      /* else NOP */
+    }
+  else
+    { /* control from */
+      if (FS == 0)
+       {
+         TRACE_ALU_INPUT1 (FCR0);
+         GPR[RT] = SIGNEXTEND (FCR0, 32);
+       }
+      else if (FS == 31)
+       {
+         TRACE_ALU_INPUT1 (FCR31);
+         GPR[RT] = SIGNEXTEND (FCR31, 32);
+       }
+      TRACE_ALU_RESULT (GPR[RT]);
+      /* else NOP */
     }
-  }
 }
 
 
@@ -3736,16 +4199,14 @@
 //
 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
 "cvt.d.%s<FMT> f<FD>, f<FS>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
 // start-sanitize-tx19
 *tx19:
@@ -3768,12 +4229,13 @@
 "cvt.l.%s<FMT> f<FD>, f<FS>"
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
 // start-sanitize-tx19
 *tx19:
@@ -3797,16 +4259,14 @@
 //
 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
 "cvt.s.%s<FMT> f<FD>, f<FS>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
 // start-sanitize-tx19
 *tx19:
@@ -3827,16 +4287,14 @@
 
 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
 "cvt.w.%s<FMT> f<FD>, f<FS>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
 // start-sanitize-tx19
 *tx19:
@@ -3857,16 +4315,14 @@
 
 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
 // start-sanitize-tx19
 *tx19:
@@ -3888,9 +4344,37 @@
 
 // DMFC1
 // DMTC1
-01000100,x,01,5.FT,vvvvv,00000000000:COP1S:64::DMxC1
+010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
+"dm%s<X>c1 r<RT>, f<FS>"
 *mipsIII:
+{
+  if (X)
+    {
+      if (SizeFGR() == 64)
+       PENDING_FILL((FS + FGRIDX),GPR[RT]);
+      else if ((FS & 0x1) == 0)
+       {
+         PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT]));
+         PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT]));
+       }
+    }
+  else
+    {
+      if (SizeFGR() == 64)
+       PENDING_FILL(RT,FGR[FS]);
+      else if ((FS & 0x1) == 0)
+       PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
+      else
+       PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
+    }
+}
+010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
+"dm%s<X>c1 r<RT>, f<FS>"
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -3902,31 +4386,22 @@
 *tx19:
 // end-sanitize-tx19
 {
-  unsigned32 instruction = instruction_0;
-  int fs = ((instruction >> 11) & 0x0000001F);
-  int ft = ((instruction >> 16) & 0x0000001F);
-  int to = ((instruction >> 23) & 0x00000001);
-  {
-    if (to) {
-      if (SizeFGR() == 64) {
-       PENDING_FILL((fs + FGRIDX),GPR[ft]);
-      } else
-       if ((fs & 0x1) == 0)
-         {
-           PENDING_FILL(((fs + 1) + FGRIDX),VH4_8(GPR[ft]));
-           PENDING_FILL((fs + FGRIDX),VL4_8(GPR[ft]));
-         }
-    } else {
-      if (SizeFGR() == 64) {
-       PENDING_FILL(ft,FGR[fs]);
-      } else
-       if ((fs & 0x1) == 0) {
-         PENDING_FILL(ft,(SET64HI(FGR[fs+1]) | FGR[fs]));
-       } else {
-         PENDING_FILL(ft,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
-       }
+  if (X)
+    {
+      if (SizeFGR() == 64)
+       StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
+      else if ((FS & 0x1) == 0)
+       StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]);
+    }
+  else
+    {
+      if (SizeFGR() == 64)
+       GPR[RT] = FGR[FS];
+      else if ((FS & 0x1) == 0)
+       GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
+      else
+       GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
     }
-  }
 }
 
 
@@ -3934,6 +4409,10 @@
 "floor.l.%s<FMT> f<FD>, f<FS>"
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -3963,6 +4442,10 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -3987,19 +4470,48 @@
 }
 
 
-// LDC1
-110101,5.BASE,5.FT,16.OFFSET:COP1:32::LDC1
+110101,5.BASE,5.FT,16.OFFSET:COP1:64::LDC1
+"ldc1 f<FT>, <OFFSET>(r<BASE>)"
+*mipsII:
+*mipsIII:
+*mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
+// start-sanitize-vr5400
+*vr5400:
+// end-sanitize-vr5400
+*r3900:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+  address_word vaddr = GPR[BASE] + EXTEND16 (OFFSET);
+  address_word paddr;
+  int uncached;
+  if ((vaddr & 7) != 0)
+    SignalExceptionAddressLoad();
+  else
+    {
+      unsigned64 memval;
+      AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL);
+      LoadMemory(&memval,0,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
+      COP_LD(((instruction_0 >> 26) & 0x3),FT,memval);;
+    }
+}
 
 
 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1
 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 {
   unsigned32 instruction = instruction_0;
   int destreg = ((instruction >> 6) & 0x0000001F);
@@ -4025,19 +4537,66 @@
 }
 
 
-// LWC1
-110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
+
+110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1 
+"lwc1 f<FT>, <OFFSET>(r<BASE>)"
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
+// start-sanitize-vr5400
+*vr5400:
+// end-sanitize-vr5400
+// start-sanitize-r5900
+*r5900:
+// end-sanitize-r5900
+*r3900:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+  unsigned32 instruction = instruction_0;
+  signed_word offset = EXTEND16 (OFFSET);
+  int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
+  signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
+  {
+    address_word vaddr = ((uword64)op1 + offset);
+    address_word paddr;
+    int uncached;
+    if ((vaddr & 3) != 0)
+      SignalExceptionAddressLoad();
+    else
+      {
+       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
+         {
+           uword64 memval = 0;
+           uword64 memval1 = 0;
+           uword64 mask = 0x7;
+           unsigned int shift = 2;
+           unsigned int reverse UNUSED = (ReverseEndian ? (mask >> shift) : 0);
+           unsigned int bigend UNUSED = (BigEndianCPU ? (mask >> shift) : 0);
+           unsigned int byte UNUSED;
+           paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
+           LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
+           byte = ((vaddr & mask) ^ (bigend << shift));
+           COP_LW(((instruction >> 26) & 0x3),destreg,(unsigned int)((memval >> (8 * byte)) & 0xFFFFFFFF));
+         }
+      }
+  }
+}
 
 
 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1
 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 {
   unsigned32 instruction = instruction_0;
   int destreg = ((instruction >> 6) & 0x0000001F);
@@ -4074,15 +4633,16 @@
 //
 // FIXME: Not correct for mips*
 //
-010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32::MADD.D
+010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
 "madd.d f<FD>, f<FR>, f<FS>, f<FT>"
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 {
   unsigned32 instruction = instruction_0;
   int destreg = ((instruction >> 6) & 0x0000001F);
@@ -4095,15 +4655,16 @@
 }
 
 
-010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32::MADD.S
+010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
 "madd.s f<FD>, f<FR>, f<FS>, f<FT>"
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 {
   unsigned32 instruction = instruction_0;
   int destreg = ((instruction >> 6) & 0x0000001F);
@@ -4117,53 +4678,56 @@
 
 
 // MFC1
+// MTC1
 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
-"m<X>c1 r<RT>, f<FS>"
+"m%s<X>c1 r<RT>, f<FS>"
 *mipsI:
 *mipsII:
 *mipsIII:
+{
+  if (X)
+    { /*MTC1*/
+      if (SizeFGR() == 64)
+       PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
+      else
+       PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
+    }
+  else /*MFC1*/
+    PENDING_FILL (RT, SIGNEXTEND(FGR[FS],32));
+}
+010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
+"m%s<X>c1 r<RT>, f<FS>"
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
 {
-  unsigned32 instruction = instruction_0;
-  int fs = ((instruction >> 11) & 0x0000001F);
-  int ft = ((instruction >> 16) & 0x0000001F);
-  int to = ((instruction >> 23) & 0x00000001);
-  {
-    if (to) {
-      if (SizeFGR() == 64) {
-       PENDING_FILL ((fs + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[ft])));
-      } else { 
-       PENDING_FILL ((fs + FGRIDX), VL4_8(GPR[ft]));
-      }
-    } else {
-      PENDING_FILL (ft, SIGNEXTEND(FGR[fs],32));
-    }
-  }
+  if (X)
+    /*MTC1*/
+    StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
+  else /*MFC1*/
+    GPR[RT] = SIGNEXTEND(FGR[FS],32);
 }
 
 
 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
 "mov.%s<FMT> f<FD>, f<FS>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
 // start-sanitize-tx19
 *tx19:
@@ -4183,6 +4747,10 @@
 000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf
 "mov%s<TF> r<RD>, r<RS>, <CC>"
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4199,6 +4767,10 @@
 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt
 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4219,6 +4791,10 @@
 
 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4246,6 +4822,10 @@
 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt
 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4267,6 +4847,10 @@
 010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D
 "msub.d f<FD>, f<FR>, f<FS>, f<FT>"
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4280,7 +4864,7 @@
   int ft = ((instruction >> 16) & 0x0000001F);
   int fr = ((instruction >> 21) & 0x0000001F);
   {
-    StoreFPR(destreg,fmt_double,(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
+    StoreFPR(destreg,fmt_double,Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
   }
 }
 
@@ -4289,6 +4873,10 @@
 010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S
 "msub.s f<FD>, f<FR>, f<FS>, f<FT>"
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4302,7 +4890,7 @@
   int ft = ((instruction >> 16) & 0x0000001F);
   int fr = ((instruction >> 21) & 0x0000001F);
   {
-   StoreFPR(destreg,fmt_single,(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
+   StoreFPR(destreg,fmt_single,Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
   }
 }
 
@@ -4312,16 +4900,14 @@
 
 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
 // start-sanitize-tx19
 *tx19:
@@ -4343,16 +4929,14 @@
 
 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
 "neg.%s<FMT> f<FD>, f<FS>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
 // start-sanitize-tx19
 *tx19:
@@ -4375,6 +4959,10 @@
 010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D
 "nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4394,6 +4982,10 @@
 010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S
 "nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4413,6 +5005,10 @@
 010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D
 "nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4432,6 +5028,10 @@
 010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S
 "nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4450,6 +5050,10 @@
 010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX
 "prefx <HINT>, r<INDEX>(r<BASE>)"
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4470,6 +5074,10 @@
 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt
 *mipsIV:
 "recip.%s<FMT> f<FD>, f<FS>"
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4491,6 +5099,10 @@
 "round.l.%s<FMT> f<FD>, f<FS>"
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4520,6 +5132,10 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4547,6 +5163,10 @@
 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt
 *mipsIV:
 "rsqrt.%s<FMT> f<FD>, f<FS>"
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4564,17 +5184,47 @@
 }
 
 
-// SDC1
+111101,5.BASE,5.FT,16.OFFSET:COP1:64::SDC1
+"sdc1 f<FT>, <OFFSET>(r<BASE>)"
+*mipsII:
+*mipsIII:
+*mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
+// start-sanitize-vr5400
+*vr5400:
+// end-sanitize-vr5400
+*r3900:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+  address_word vaddr = GPR[BASE] + EXTEND16 (OFFSET);
+  int uncached;
+  if ((vaddr & 7) != 0)
+    SignalExceptionAddressStore();
+  else
+    {
+      address_word paddr;
+      unsigned64 memval;
+      AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL);
+      memval = (unsigned64) COP_SD(((instruction_0 >> 26) & 0x3),FT);
+      StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,0,paddr,vaddr,isREAL);
+    }
+}
 
 
 010011,5.RS,5.RT,vvvvv,00000001001:COP1X:64::SDXC1
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 {
   unsigned32 instruction = instruction_0;
   int fs = ((instruction >> 11) & 0x0000001F);
@@ -4607,12 +5257,13 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
 // start-sanitize-tx19
 *tx19:
@@ -4633,16 +5284,14 @@
 
 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
 // start-sanitize-tx19
 *tx19:
@@ -4662,18 +5311,65 @@
 }
 
 
-// SWC1
+
+111001,5.BASE,5.FT,16.OFFSET:COP1:32::SWC1
+"swc1 f<FT>, <OFFSET>(r<BASE>)"
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
+// start-sanitize-vr5400
+*vr5400:
+// end-sanitize-vr5400
+// start-sanitize-r5900
+*r5900:
+// end-sanitize-r5900
+*r3900:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+  unsigned32 instruction = instruction_0;
+  signed_word offset = EXTEND16 (OFFSET);
+  int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
+  signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
+  {
+    address_word vaddr = ((uword64)op1 + offset);
+    address_word paddr;
+    int uncached;
+    if ((vaddr & 3) != 0)
+      SignalExceptionAddressStore();
+    else
+      {
+       if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
+         {
+           uword64 memval = 0;
+           uword64 memval1 = 0;
+           uword64 mask = 0x7;
+           unsigned int byte;
+           paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
+           byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
+           memval = (((uword64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
+           {
+             StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
+           }
+         }
+      }
+  }
+}
 
 
 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1
 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 {
   unsigned32 instruction = instruction_0;
   int fs = ((instruction >> 11) & 0x0000001F);
@@ -4709,6 +5405,10 @@
 "trunc.l.%s<FMT> f<FD>, f<FS>"
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4738,6 +5438,10 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4771,10 +5475,11 @@
 
 010000,01000,00000,16.OFFSET:COP0:32::BC0F
 "bc0f <OFFSET>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4785,10 +5490,11 @@
 
 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
 "bc0fl <OFFSET>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4799,10 +5505,7 @@
 
 010000,01000,00001,16.OFFSET:COP0:32::BC0T
 "bc0t <OFFSET>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -4811,10 +5514,11 @@
 
 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
 "bc0tl <OFFSET>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4826,6 +5530,10 @@
 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4853,10 +5561,11 @@
 
 010000,10000,000000000000000,111001:COP0:32::DI
 "di"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4867,10 +5576,11 @@
 
 010000,10000,000000000000000,111000:COP0:32::EI
 "ei"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4883,6 +5593,10 @@
 "eret"
 *mipsIII:
 *mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4893,38 +5607,46 @@
 
 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
 "mfc0 r<RT>, r<RD> # <REGX>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
-
+{
+  DecodeCoproc (instruction_0);
+}
 
 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
 "mtc0 r<RT>, r<RD> # <REGX>"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
+{
+  DecodeCoproc (instruction_0);
+}
 
 
 010000,10000,000000000000000,001000:COP0:32::TLBP
 "tlbp"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4935,10 +5657,11 @@
 
 010000,10000,000000000000000,000001:COP0:32::TLBR
 "tlbr"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4949,10 +5672,11 @@
 
 010000,10000,000000000000000,000010:COP0:32::TLBWI
 "tlbwi"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4963,10 +5687,11 @@
 
 010000,10000,000000000000000,000110:COP0:32::TLBWR
 "tlbwr"
-*mipsI:
-*mipsII:
-*mipsIII:
-*mipsIV:
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr5000:
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 *vr5400:
 // end-sanitize-vr5400
@@ -4975,9 +5700,13 @@
 // end-sanitize-r5900
 
 \f
-:include:::m16.igen
+:include:16::m16.igen
+// start-sanitize-vr4320
+:include::vr4320:vr4320.igen
+// end-sanitize-vr4320
 // start-sanitize-vr5400
 :include::vr5400:vr5400.igen
+:include:64,f::mdmx.igen
 // end-sanitize-vr5400
 // start-sanitize-r5900
 :include::r5900:r5900.igen
@@ -5081,4 +5810,4 @@
 //   }
 // }
 
-// start-sanitize-cygnus-never
+// end-sanitize-cygnus-never