Fix problems with finishing a dummy function call on simulators.

[deliverable/binutils-gdb.git] / sim / mn10300 / am33.igen

diff --git a/sim/mn10300/am33.igen b/sim/mn10300/am33.igen
index 06abf7b34eadbadf4ff93701260497533880b77b..5bc96aca6164efb19c08a24cc3870d144350a959 100644 (file)
--- a/sim/mn10300/am33.igen
+++ b/sim/mn10300/am33.igen
@@ -34,7 +34,7 @@
     case 4:
       return REG_MCVF;
     default:
-      abort ();
+      sim_engine_abort (SD, CPU, cia, "%s:%d: bad switch\n", __FILE__, __LINE__);
     }
 }
 
@@ -42,6 +42,7 @@
 8.0xf0+4.0x2,00,2.AN0:D0m:::mov
 "mov"
 *am33
+*am33_2
 {
   PC = cia;
   State.regs[REG_A0 + AN0] = State.regs[REG_USP];
@@ -52,6 +53,7 @@
 8.0xf0+4.0x2,01,2.AN0:D0n:::mov
 "mov"
 *am33
+*am33_2
 {
   PC = cia;
   State.regs[REG_A0 + AN0] = State.regs[REG_SSP];
@@ -62,6 +64,7 @@
 8.0xf0+4.0x2,10,2.AN0:D0o:::mov
 "mov"
 *am33
+*am33_2
 {
   PC = cia;
   State.regs[REG_A0 + AN0] = State.regs[REG_MSP];
@@ -72,6 +75,7 @@
 8.0xf0+4.0x2,11,2.AN0:D0p:::mov
 "mov"
 *am33
+*am33_2
 {
   PC = cia;
   State.regs[REG_A0 + AN0] = PC;
@@ -82,6 +86,7 @@
 8.0xf0+4.0x3,2.AM1,00:D0q:::mov
 "mov"
 *am33
+*am33_2
 {
   PC = cia;
   State.regs[REG_USP] = State.regs[REG_A0 + AM1];
@@ -91,6 +96,7 @@
 8.0xf0+4.0x3,2.AM1,01:D0r:::mov
 "mov"
 *am33
+*am33_2
 {
   PC = cia;
   State.regs[REG_SSP] = State.regs[REG_A0 + AM1];
@@ -100,6 +106,7 @@
 8.0xf0+4.0x3,2.AM1,10:D0s:::mov
 "mov"
 *am33
+*am33_2
 {
   PC = cia;
   State.regs[REG_MSP] = State.regs[REG_A0 + AM1];
@@ -110,8 +117,9 @@
 8.0xf0+4.0xe,IMM4:D0t:::syscall
 "syscall"
 *am33
+*am33_2
 {
-  unsigned int sp, next_pc;
+  unsigned32 sp, next_pc;
 
   PC = cia;
   sp = State.regs[REG_SP];
@@ -127,6 +135,7 @@
 8.0xf2+4.0xe,11,2.DN0:D0u:::mov
 "mov"
 *am33
+*am33_2
 {
   PC = cia;
   State.regs[REG_D0 + DN0] = PSW;
@@ -137,6 +146,7 @@
 8.0xf2+4.0xf,2.DM1,01:D0v:::mov
 "mov"
 *am33
+*am33_2
 {
   PC = cia;
   PSW = State.regs[REG_D0 + DM1];
@@ -146,6 +156,7 @@
 8.0xf5+00,2.AM1,4.RN0:D0w:::mov
 "mov"
 *am33
+*am33_2
 {
   int destreg = translate_rreg (SD_, RN0);
 
@@ -157,6 +168,7 @@
 8.0xf5+01,2.DM1,4.RN0:D0x:::mov
 "mov"
 *am33
+*am33_2
 {
   int destreg = translate_rreg (SD_, RN0);
 
@@ -168,6 +180,7 @@
 8.0xf5+10,4.RM1,2.AN0:D0y:::mov
 "mov"
 *am33
+*am33_2
 {
   int destreg = translate_rreg (SD_, RM1);
 
@@ -179,6 +192,7 @@
 8.0xf5+11,4.RM1,2.DN0:D0z:::mov
 "mov"
 *am33
+*am33_2
 {
   int destreg = translate_rreg (SD_, RM1);
 
@@ -191,9 +205,10 @@
 8.0xf8+8.0xce+8.REGS:D1a:::movm
 "movm"
 *am33
+*am33_2
 {
-  unsigned long usp = State.regs[REG_USP];
-  unsigned long mask;
+  unsigned32 usp = State.regs[REG_USP];
+  unsigned32 mask;
 
   PC = cia;
   mask = REGS;
@@ -241,8 +256,9 @@
       usp += 4;
     }
 
-  /* start-sanitize-am33 */
-  if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
+  if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
+      || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
+      )
     {
       if (mask & 0x1)
        {
@@ -274,7 +290,6 @@
          usp += 4;
        }
     }
-  /* end-sanitize-am33 */
 
   /* And make sure to update the stack pointer.  */
   State.regs[REG_USP] = usp;
@@ -284,11 +299,17 @@
 8.0xf8+8.0xcf+8.REGS:D1b:::movm
 "movm"
 *am33
+*am33_2
 {
-  unsigned long usp = State.regs[REG_USP];
-  unsigned long mask;
+  unsigned32 usp = State.regs[REG_USP];
+  unsigned32 mask;
 
-  if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
+  PC = cia;
+  mask = REGS;
+
+  if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33
+      || STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2
+      )
     {
       if (mask & 0x4)
        {
@@ -320,7 +341,6 @@
          /* Need to save MDQR, MCRH, MCRL, and MCVF */
        }
     }
-  /* end-sanitize-am33 */
 
   if (mask & 0x80)
     {
@@ -373,6 +393,7 @@
 8.0xfc+8.0xfc+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:4a:::and
 "and"
 *am33
+*am33_2
 {
   PC = cia;
   PSW &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
@@ -382,6 +403,7 @@
 8.0xfc+8.0xfd+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::or
 "or"
 *am33
+*am33_2
 {
   PC = cia;
   PSW |= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
@@ -391,6 +413,7 @@
 8.0xf9+8.0x08+4.RM2,4.RN0!RM2:D1g:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -405,6 +428,7 @@
 8.0xf9+8.0x18+4.RN0,4.RN2=RN0:D1:::ext
 "mov"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -420,6 +444,7 @@
 8.0xf9+8.0x28+4.RM2,4.RN0!RM2:D1:::extb
 "extb"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -433,6 +458,7 @@
 8.0xf9+8.0x38+4.RM2,4.RN0!RM2:D1:::extbu
 "extbu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -446,6 +472,7 @@
 8.0xf9+8.0x48+4.RM2,4.RN0!RM2:D1:::exth
 "exth"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -459,6 +486,7 @@
 8.0xf9+8.0x58+4.RM2,4.RN0!RM2:D1:::exthu
 "exthu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -472,6 +500,7 @@
 8.0xf9+8.0x68+4.RM2,4.RN0=RM2:D1:::clr
 "clr"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -486,6 +515,7 @@
 8.0xf9+8.0x78+4.RM2,4.RN0:D1b:::add
 "add"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -499,10 +529,11 @@
 8.0xf9+8.0x88+4.RM2,4.RN0:D1b:::addc
 "addc"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
   int z, c, n, v;
-  unsigned long reg1, reg2, sum;
+  unsigned32 reg1, reg2, sum;
 
   PC = cia;
   srcreg = translate_rreg (SD_, RM2);
@@ -528,6 +559,7 @@
 8.0xf9+8.0x98+4.RM2,4.RN0:D1b:::sub
 "sub"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -541,10 +573,11 @@
 8.0xf9+8.0xa8+4.RM2,4.RN0:D1b:::subc
 "subc"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
   int z, c, n, v;
-  unsigned long reg1, reg2, difference;
+  unsigned32 reg1, reg2, difference;
 
   PC = cia;
   srcreg = translate_rreg (SD_, RM2);
@@ -570,6 +603,7 @@
 8.0xf9+8.0xb8+4.RN0,4.RN2=RN0:D1:::inc
 "inc"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -582,18 +616,20 @@
 8.0xf9+8.0xc8+4.RN0,4.RN2=RN0:D1:::inc4
 "inc4"
 *am33
+*am33_2
 {
   int dstreg;
 
   PC = cia;
   dstreg = translate_rreg (SD_, RN0);
-  State.regs[dstreg] += 4;
+  genericAdd (4, dstreg);
 }
 
 // 1111 1001 1101 1000 Rm Rn; cmp Rm,Rn
 8.0xf9+8.0xd8+4.RM2,4.RN0:D1:::cmp
 "cmp"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2;
 
@@ -607,6 +643,7 @@
 8.0xf9+8.0xe8+4.XRM2,4.RN0:D1l:::mov
 "mov"
 *am33
+*am33_2
 {
   int dstreg, srcreg;
 
@@ -621,6 +658,7 @@
 8.0xf9+8.0xf8+4.RM2,4.XRN0:D1m:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -635,6 +673,7 @@
 8.0xf9+8.0x09+4.RM2,4.RN0:D1a:::and
 "and"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
   int z, n;
@@ -655,6 +694,7 @@
 8.0xf9+8.0x19+4.RM2,4.RN0:D1a:::or
 "or"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
   int z, n;
@@ -674,6 +714,7 @@
 8.0xf9+8.0x29+4.RM2,4.RN0:D1a:::xor
 "xor"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
   int z, n;
@@ -693,6 +734,7 @@
 8.0xf9+8.0x39+4.RM2,4.RN0=RM2:D1:::not
 "not"
 *am33
+*am33_2
 {
   int dstreg;
   int z, n;
@@ -711,9 +753,10 @@
 8.0xf9+8.0x49+4.RM2,4.RN0:D1a:::asr
 "asr"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
-  long temp;
+  signed32 temp;
   int c, z, n;
 
   PC = cia;
@@ -734,6 +777,7 @@
 8.0xf9+8.0x59+4.RM2,4.RN0:D1a:::lsr
 "lsr"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
   int z, n, c;
@@ -755,6 +799,7 @@
 8.0xf9+8.0x69+4.RM2,4.RN0:D1a:::asl
 "asl"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
   int z, n;
@@ -774,6 +819,7 @@
 8.0xf9+8.0x79+4.RM2,4.RN0=RM2:D1:::asl2
 "asl2"
 *am33
+*am33_2
 {
   int dstreg;
   int n, z;
@@ -792,10 +838,11 @@
 8.0xf9+8.0x89+4.RM2,4.RN0=RM2:D1:::ror
 "ror"
 *am33
+*am33_2
 {
   int dstreg;
   int c, n, z;
-  unsigned long value;
+  unsigned32 value;
 
   PC = cia;
   dstreg = translate_rreg (SD_, RN0);
@@ -816,10 +863,11 @@
 8.0xf9+8.0x99+4.RM2,4.RN0=RM2:D1:::rol
 "rol"
 *am33
+*am33_2
 {
   int dstreg;
   int c, n, z;
-  unsigned long value;
+  unsigned32 value;
 
   PC = cia;
   dstreg = translate_rreg (SD_, RN0);
@@ -840,9 +888,10 @@
 8.0xf9+8.0xa9+4.RM2,4.RN0:D1b:::mul
 "mul"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
-  unsigned long long temp;
+  unsigned64 temp;
   int n, z;
 
   PC = cia;
@@ -852,7 +901,7 @@
   temp = ((signed64)(signed32)State.regs[dstreg]
           *  (signed64)(signed32)State.regs[srcreg]);
   State.regs[dstreg] = temp & 0xffffffff;
-  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
+  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
   z = (State.regs[dstreg] == 0);
   n = (State.regs[dstreg] & 0x80000000) != 0;
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
@@ -863,9 +912,10 @@
 8.0xf9+8.0xb9+4.RM2,4.RN0:D1b:::mulu
 "mulu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
-  unsigned long long temp;
+  unsigned64 temp;
   int n, z;
 
   PC = cia;
@@ -886,9 +936,10 @@
 8.0xf9+8.0xc9+4.RM2,4.RN0:D1b:::div
 "div"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
-  long long temp;
+  signed64 temp;
   int n, z;
 
   PC = cia;
@@ -911,9 +962,10 @@
 8.0xf9+8.0xd9+4.RM2,4.RN0:D1b:::divu
 "divu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
-  unsigned long long temp;
+  unsigned64 temp;
   int n, z;
 
   PC = cia;
@@ -937,6 +989,7 @@
 8.0xf9+8.0x0a+4.RN2,4.RM0:D1h:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -950,6 +1003,7 @@
 8.0xf9+8.0x1a+4.RM2,4.RN0:D1i:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -963,6 +1017,7 @@
 8.0xf9+8.0x2a+4.RN2,4.RM0:D1g:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -976,6 +1031,7 @@
 8.0xf9+8.0x3a+4.RM2,4.RN0:D1i:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -989,6 +1045,7 @@
 8.0xf9+8.0x4a+4.RN2,4.RM0:D1g:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1002,6 +1059,7 @@
 8.0xf9+8.0x5a+4.RM2,4.RN0:D1i:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1015,6 +1073,7 @@
 8.0xf9+8.0x6a+4.RN2,4.RM0!RN2:D1y:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1026,9 +1085,10 @@
 }
 
 // 1111 1001 0111 1010 Rm Rn; mov Rm,(Rn+)
-8.0xf9+8.0x7a+4.RM2,4.RN0!RM2:D1z:::mov
+8.0xf9+8.0x7a+4.RM2,4.RN0:D1z:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1043,6 +1103,7 @@
 8.0xf9+8.0x8a+4.RN2,4.0000:D1j:::mov
 "mov"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -1055,6 +1116,7 @@
 8.0xf9+8.0x9a+4.RM2,4.0000:D1k:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -1067,6 +1129,7 @@
 8.0xf9+8.0xaa+4.RN2,4.0000:D1j:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -1079,6 +1142,7 @@
 8.0xf9+8.0xba+4.RM2,4.0000:D1k:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -1091,6 +1155,7 @@
 8.0xf9+8.0xca+4.RN2,4.0000:D1j:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -1103,6 +1168,7 @@
 8.0xf9+8.0xda+4.RM2,4.0000:D1k:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -1115,6 +1181,7 @@
 8.0xf9+8.0xea+4.RN2,4.RM0!RN2:D1y:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1126,9 +1193,10 @@
 }
 
 // 1111 1001 1111 1010 Rm Rn; movhu Rm,(Rn+)
-8.0xf9+8.0xfa+4.RM2,4.RN0!RM2:D1z:::movhu
+8.0xf9+8.0xfa+4.RM2,4.RN0:D1z:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1144,9 +1212,10 @@
 8.0xf9+8.0x0b+4.RM2,4.RN0:D1:::mac
 "mac"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2;
-  long long temp, sum;
+  signed64 temp, sum;
   int c, v;
 
   PC = cia;
@@ -1172,9 +1241,10 @@
 8.0xf9+8.0x1b+4.RM2,4.RN0:D1:::macu
 "macu"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2;
-  unsigned long long temp, sum;
+  unsigned64 temp, sum;
   int c, v;
 
   PC = cia;
@@ -1200,9 +1270,10 @@
 8.0xf9+8.0x2b+4.RM2,4.RN0:D1:::macb
 "macb"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2;
-  long temp, sum;
+  signed32 temp, sum;
   int v;
 
   PC = cia;
@@ -1223,9 +1294,10 @@
 8.0xf9+8.0x3b+4.RM2,4.RN0:D1:::macbu
 "macbu"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2;
-  long long temp, sum;
+  signed64 temp, sum;
   int v;
 
   PC = cia;
@@ -1246,9 +1318,10 @@
 8.0xf9+8.0x4b+4.RM2,4.RN0:D1:::mach
 "mach"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2;
-  long long temp, sum;
+  signed64 temp, sum;
   int c, v;
 
   PC = cia;
@@ -1274,9 +1347,10 @@
 8.0xf9+8.0x5b+4.RM2,4.RN0:D1:::machu
 "machu"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2;
-  long long temp, sum;
+  signed64 temp, sum;
   int c, v;
 
   PC = cia;
@@ -1302,9 +1376,10 @@
 8.0xf9+8.0x6b+4.RM2,4.RN0:D1:::dmach
 "dmach"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2;
-  long temp, temp2, sum;
+  signed32 temp, temp2, sum;
   int v;
 
   PC = cia;
@@ -1327,9 +1402,10 @@
 8.0xf9+8.0x7b+4.RM2,4.RN0:D1:::dmachu
 "dmachu"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2;
-  unsigned long temp, temp2, sum;
+  unsigned32 temp, temp2, sum;
   int v;
 
   PC = cia;
@@ -1352,9 +1428,10 @@
 8.0xf9+8.0x8b+4.RM2,4.RN0:D1:::dmulh
 "dmulh"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
-  long temp;
+  signed32 temp;
 
   PC = cia;
   srcreg = translate_rreg (SD_, RM2);
@@ -1372,9 +1449,10 @@
 8.0xf9+8.0x9b+4.RM2,4.RN0:D1:::dumachu
 "dmachu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
-  unsigned long temp;
+  unsigned32 temp;
 
   PC = cia;
   srcreg = translate_rreg (SD_, RM2);
@@ -1392,6 +1470,7 @@
 8.0xf9+8.0xab+4.RM2,4.RN0:D1:::sat16
 "sat16"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
   int value, z, n;
@@ -1419,6 +1498,7 @@
 8.0xf9+8.0xbb+4.RM2,4.RN0:D1:::mcste
 "mcste"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1432,7 +1512,7 @@
   /* 32bit saturation.  */
   if (State.regs[srcreg] == 0x20)
     {
-      long long tmp;
+      signed64 tmp;
 
       tmp = State.regs[REG_MCRH];
       tmp <<= 32;
@@ -1448,7 +1528,7 @@
   /* 16bit saturation */
   else if (State.regs[srcreg] == 0x10)
     {
-      long long tmp;
+      signed64 tmp;
 
       tmp = State.regs[REG_MCRH];
       tmp <<= 32;
@@ -1464,7 +1544,7 @@
   /* 8 bit saturation */
   else if (State.regs[srcreg] == 0x8)
     {
-      long long tmp;
+      signed64 tmp;
 
       tmp = State.regs[REG_MCRH];
       tmp <<= 32;
@@ -1480,7 +1560,7 @@
   /* 9 bit saturation */
   else if (State.regs[srcreg] == 0x9)
     {
-      long long tmp;
+      signed64 tmp;
 
       tmp = State.regs[REG_MCRH];
       tmp <<= 32;
@@ -1496,7 +1576,7 @@
   /* 9 bit saturation */
   else if (State.regs[srcreg] == 0x30)
     {
-      long long tmp;
+      signed64 tmp;
 
       tmp = State.regs[REG_MCRH];
       tmp <<= 32;
@@ -1516,6 +1596,7 @@
 8.0xf9+8.0xcb+4.RM2,4.RN0:D1:::swap
 "swap"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1533,6 +1614,7 @@
 8.0xf9+8.0xdb+4.RM2,4.RN0:D1:::swaph
 "swaph"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1550,6 +1632,7 @@
 8.0xf9+8.0xeb+4.RM2,4.RN0:D1:::swhw
 "swhw"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1565,6 +1648,7 @@
 8.0xf9+8.0xfb+4.RM2,4.RN0:D1:::bsch
 "bsch"
 *am33
+*am33_2
 {
   int temp, c, i;
   int srcreg, dstreg;
@@ -1579,6 +1663,7 @@
   if (start == -1)
     start = 31;
     
+  c = 0;
   for (i = start; i >= 0; i--)
     {
       if (temp & (1 << i))
@@ -1603,6 +1688,7 @@
 8.0xfb+8.0x08+4.RM2,4.RN0=RM2+8.IMM8:D2j:::mov
 "mov"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -1615,6 +1701,7 @@
 8.0xfb+8.0x18+4.RM2,4.RN0=RM2+8.IMM8:D2:::movu
 "movu"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -1627,6 +1714,7 @@
 8.0xfb+8.0x78+4.RM2,4.RN0=RM2+8.IMM8:D2d:::add
 "add"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -1639,10 +1727,11 @@
 8.0xfb+8.0x88+4.RM2,4.RN0=RM2+8.IMM8:D2d:::addc
 "addc"
 *am33
+*am33_2
 {
   int dstreg, imm;
   int z, c, n, v;
-  unsigned long reg1, reg2, sum;
+  unsigned32 reg2, sum;
 
   PC = cia;
   dstreg = translate_rreg (SD_, RN0);
@@ -1667,6 +1756,7 @@
 8.0xfb+8.0x98+4.RM2,4.RN0=RM2+8.IMM8:D2d:::sub
 "sub"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -1680,10 +1770,11 @@
 8.0xfb+8.0xa8+4.RM2,4.RN0=RM2+8.IMM8:D2d:::subc
 "subc"
 *am33
+*am33_2
 {
   int imm, dstreg;
   int z, c, n, v;
-  unsigned long reg1, reg2, difference;
+  unsigned32 reg2, difference;
 
   PC = cia;
   dstreg = translate_rreg (SD_, RN0);
@@ -1708,6 +1799,7 @@
 8.0xfb+8.0xd8+4.RM2,4.RN0=RM2+8.IMM8:D2b:::cmp
 "cmp"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -1720,6 +1812,7 @@
 8.0xfb+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM8:D2k:::mov
 "mov"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -1733,6 +1826,7 @@
 8.0xfb+8.0x09+4.RM2,4.RN0=RM2+8.IMM8:D2d:::and
 "and"
 *am33
+*am33_2
 {
   int dstreg;
   int z, n;
@@ -1751,6 +1845,7 @@
 8.0xfb+8.0x19+4.RM2,4.RN0=RM2+8.IMM8:D2d:::or
 "or"
 *am33
+*am33_2
 {
   int dstreg;
   int z, n;
@@ -1769,6 +1864,7 @@
 8.0xfb+8.0x29+4.RM2,4.RN0=RM2+8.IMM8:D2d:::xor
 "xor"
 *am33
+*am33_2
 {
   int dstreg;
   int z, n;
@@ -1787,9 +1883,10 @@
 8.0xfb+8.0x49+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asr
 "asr"
 *am33
+*am33_2
 {
   int dstreg;
-  long temp;
+  signed32 temp;
   int c, z, n;
 
   PC = cia;
@@ -1809,6 +1906,7 @@
 8.0xfb+8.0x59+4.RM2,4.RN0=RM2+8.IMM8:D2a:::lsr
 "lsr"
 *am33
+*am33_2
 {
   int dstreg;
   int z, n, c;
@@ -1828,8 +1926,9 @@
 8.0xfb+8.0x69+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asl
 "asl"
 *am33
+*am33_2
 {
-  int srcreg, dstreg;
+  int dstreg;
   int z, n;
 
   PC = cia;
@@ -1846,9 +1945,10 @@
 8.0xfb+8.0xa9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mul
 "mul"
 *am33
+*am33_2
 {
   int dstreg;
-  unsigned long long temp;
+  unsigned64 temp;
   int z, n;
 
   PC = cia;
@@ -1857,7 +1957,7 @@
   temp = ((signed64)(signed32)State.regs[dstreg]
           *  (signed64)(signed32)EXTEND8 (IMM8));
   State.regs[dstreg] = temp & 0xffffffff;
-  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
+  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
   z = (State.regs[dstreg] == 0);
   n = (State.regs[dstreg] & 0x80000000) != 0;
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
@@ -1868,9 +1968,10 @@
 8.0xfb+8.0xb9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mulu
 "mulu"
 *am33
+*am33_2
 {
   int dstreg;
-  unsigned long long temp;
+  unsigned64 temp;
   int z, n;
 
   PC = cia;
@@ -1890,6 +1991,7 @@
 8.0xfb+8.0xe9+4.RN2,4.RM0=RN2+8.IMM8:D2l:::btst
 "btst"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -1902,6 +2004,7 @@
 8.0xfb+8.0x0a+4.RN2,4.RM0+8.IMM8:D2l:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1914,6 +2017,8 @@
 // 1111 1011 0001 1010 Rn Rm IMM8; mov Rm,(d8,Rn)
 8.0xfb+8.0x1a+4.RM2,4.RN0+8.IMM8:D2m:::mov
 "mov"
+*am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1926,6 +2031,8 @@
 // 1111 1011 0010 1010 Rn Rm IMM8; movbu (d8,Rm),Rn
 8.0xfb+8.0x2a+4.RN2,4.RM0+8.IMM8:D2l:::movbu
 "movbu"
+*am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1938,6 +2045,8 @@
 // 1111 1011 0011 1010 Rn Rm IMM8; movbu Rm,(d8,Rn)
 8.0xfb+8.0x3a+4.RM2,4.RN0+8.IMM8:D2m:::movbu
 "movbu"
+*am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1950,6 +2059,8 @@
 // 1111 1011 0100 1010 Rn Rm IMM8; movhu (d8,Rm),Rn
 8.0xfb+8.0x4a+4.RN2,4.RM0+8.IMM8:D2l:::movhu
 "movhu"
+*am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1962,6 +2073,8 @@
 // 1111 1011 0101 1010 Rn Rm IMM8; movhu Rm,(d8,Rn)
 8.0xfb+8.0x5a+4.RM2,4.RN0+8.IMM8:D2m:::movhu
 "movhu"
+*am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1975,6 +2088,7 @@
 8.0xfb+8.0x6a+4.RN2,4.RM0!RN2+8.IMM8:D2y:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -1986,8 +2100,10 @@
 }
 
 // 1111 1011 0111 1010 Rn Rm IMM8; mov Rm,(d8,Rn+)
-8.0xfb+8.0x7a+4.RM2,4.RN0!RM2+8.IMM8:D2z:::mov
+8.0xfb+8.0x7a+4.RM2,4.RN0+8.IMM8:D2z:::mov
 "mov"
+*am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -2002,73 +2118,86 @@
 // 1111 1011 1000 1010 Rn 0000 IMM8; mov (d8,sp),Rn
 8.0xfb+8.0x8a+4.RN2,4.0x0+8.IMM8:D2n:::mov
 "mov"
+*am33
+*am33_2
 {
   int dstreg;
 
   PC = cia;
   dstreg = translate_rreg (SD_, RN2);
-  State.regs[dstreg] = load_word (State.regs[REG_SP] + EXTEND8 (IMM8));
+  State.regs[dstreg] = load_word (State.regs[REG_SP] + IMM8);
 }
 
-// 1111 1011 1001 1010 Rm 0000 IMM8; mov Rm,(d8,Rn)
+// 1111 1011 1001 1010 Rm 0000 IMM8; mov Rm,(d8,sp)
 8.0xfb+8.0x9a+4.RM2,4.0x0+8.IMM8:D2o:::mov
 "mov"
+*am33
+*am33_2
 {
   int srcreg;
 
   PC = cia;
   srcreg = translate_rreg (SD_, RM2);
-  store_word (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
+  store_word (State.regs[REG_SP] + IMM8, State.regs[srcreg]);
 }
 
 // 1111 1011 1010 1010 Rn Rm IMM8; movbu (d8,sp),Rn
 8.0xfb+8.0xaa+4.RN2,4.0x0+8.IMM8:D2n:::movbu
 "movbu"
+*am33
+*am33_2
 {
   int dstreg;
 
   PC = cia;
   dstreg = translate_rreg (SD_, RN2);
-  State.regs[dstreg] = load_byte (State.regs[REG_SP] + EXTEND8 (IMM8));
+  State.regs[dstreg] = load_byte (State.regs[REG_SP] + IMM8);
 }
 
-// 1111 1011 1011 1010 Rn Rm IMM8; movbu Rm,(sp,Rn)
+// 1111 1011 1011 1010 Rn Rm IMM8; movbu Rm,(d8,sp)
 8.0xfb+8.0xba+4.RM2,4.0x0+8.IMM8:D2o:::movbu
 "movbu"
+*am33
+*am33_2
 {
   int srcreg;
 
   PC = cia;
   srcreg = translate_rreg (SD_, RM2);
-  store_byte (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
+  store_byte (State.regs[REG_SP] + IMM8, State.regs[srcreg]);
 }
 
 // 1111 1011 1100 1010 Rn Rm IMM8; movhu (d8,sp),Rn
 8.0xfb+8.0xca+4.RN2,4.0x0+8.IMM8:D2n:::movhu
 "movhu"
+*am33
+*am33_2
 {
   int dstreg;
 
   PC = cia;
   dstreg = translate_rreg (SD_, RN2);
-  State.regs[dstreg] = load_half (State.regs[REG_SP] + EXTEND8 (IMM8));
+  State.regs[dstreg] = load_half (State.regs[REG_SP] + IMM8);
 }
 
 // 1111 1011 1101 1010 Rn Rm IMM8; movhu Rm,(d8,sp)
 8.0xfb+8.0xda+4.RM2,4.0x0+8.IMM8:D2o:::movhu
 "movhu"
+*am33
+*am33_2
 {
   int srcreg;
 
   PC = cia;
   srcreg = translate_rreg (SD_, RM2);
-  store_half (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
+  store_half (State.regs[REG_SP] + IMM8, State.regs[srcreg]);
 }
 
 // 1111 1011 1110 1010 Rn Rm IMM8; movhu (d8,Rm+),Rn
 8.0xfb+8.0xea+4.RN2,4.RM0!RN2+8.IMM8:D2y:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -2080,8 +2209,10 @@
 }
 
 // 1111 1011 1111 1010 Rn Rm IMM8; movhu Rm,(d8,Rn+)
-8.0xfb+8.0xfa+4.RM2,4.RN0!RM2+8.IMM8:D2z:::movhu
+8.0xfb+8.0xfa+4.RM2,4.RN0+8.IMM8:D2z:::movhu
 "movhu"
+*am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -2096,9 +2227,11 @@
 // 1111 1011 0000 1011 Rn Rn IMM8; mac imm8,Rn
 8.0xfb+8.0x0b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mac
 "mac"
+*am33
+*am33_2
 {
   int srcreg;
-  long long temp, sum;
+  signed64 temp, sum;
   int c, v;
 
   PC = cia;
@@ -2122,9 +2255,11 @@
 // 1111 1011 0001 1011 Rn Rn IMM8; macu imm8,Rn
 8.0xfb+8.0x1b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macu
 "macu"
+*am33
+*am33_2
 {
   int srcreg;
-  long long temp, sum;
+  signed64 temp, sum;
   int c, v;
 
   PC = cia;
@@ -2148,9 +2283,11 @@
 // 1111 1011 0010 1011 Rn Rn IMM8; macb imm8,Rn
 8.0xfb+8.0x2b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macb
 "macb"
+*am33
+*am33_2
 {
   int srcreg;
-  long long temp, sum;
+  signed64 temp, sum;
   int c, v;
 
   PC = cia;
@@ -2174,9 +2311,11 @@
 // 1111 1011 0011 1011 Rn Rn IMM8; macbu imm8,Rn
 8.0xfb+8.0x3b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macbu
 "macbu"
+*am33
+*am33_2
 {
   int srcreg;
-  long long temp, sum;
+  signed64 temp, sum;
   int c, v;
 
   PC = cia;
@@ -2200,9 +2339,11 @@
 // 1111 1011 0100 1011 Rn Rn IMM8; mach imm8,Rn
 8.0xfb+8.0x4b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mach
 "mach"
+*am33
+*am33_2
 {
   int srcreg;
-  long long temp, sum;
+  signed64 temp, sum;
   int c, v;
 
   PC = cia;
@@ -2226,9 +2367,11 @@
 // 1111 1011 0101 1011 Rn Rn IMM8; machu imm8,Rn
 8.0xfb+8.0x5b+4.RN2,4.RN0=RN2+8.IMM8:D2:::machu
 "machu"
+*am33
+*am33_2
 {
   int srcreg;
-  long long temp, sum;
+  signed64 temp, sum;
   int c, v;
 
   PC = cia;
@@ -2252,6 +2395,8 @@
 // 1111 1011 1011 1011 Rn Rn IMM8; mcste imm8,Rn
 8.0xfb+8.0xbb+4.RN2,4.RN0=RN2+8.IMM8:D2:::mcste
 "mcste"
+*am33
+*am33_2
 {
   int dstreg;
 
@@ -2264,7 +2409,7 @@
   /* 32bit saturation.  */
   if (IMM8 == 0x20)
     {
-      long long tmp;
+      signed64 tmp;
 
       tmp = State.regs[REG_MCRH];
       tmp <<= 32;
@@ -2280,7 +2425,7 @@
   /* 16bit saturation */
   else if (IMM8 == 0x10)
     {
-      long long tmp;
+      signed64 tmp;
 
       tmp = State.regs[REG_MCRH];
       tmp <<= 32;
@@ -2296,7 +2441,7 @@
   /* 8 bit saturation */
   else if (IMM8 == 0x8)
     {
-      long long tmp;
+      signed64 tmp;
 
       tmp = State.regs[REG_MCRH];
       tmp <<= 32;
@@ -2312,7 +2457,7 @@
   /* 9 bit saturation */
   else if (IMM8 == 0x9)
     {
-      long long tmp;
+      signed64 tmp;
 
       tmp = State.regs[REG_MCRH];
       tmp <<= 32;
@@ -2328,7 +2473,7 @@
   /* 9 bit saturation */
   else if (IMM8 == 0x30)
     {
-      long long tmp;
+      signed64 tmp;
 
       tmp = State.regs[REG_MCRH];
       tmp <<= 32;
@@ -2348,9 +2493,10 @@
 8.0xfb+8.0x7c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::add
 "add"
 *am33
+*am33_2
 {
   int z, c, n, v;
-  unsigned long sum, source1, source2;
+  unsigned32 sum, source1, source2;
   int srcreg1, srcreg2, dstreg;
 
   PC = cia;
@@ -2378,9 +2524,10 @@
 8.0xfb+8.0x8c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::addc
 "addc"
 *am33
+*am33_2
 {
   int z, c, n, v;
-  unsigned long sum, source1, source2;
+  unsigned32 sum, source1, source2;
   int srcreg1, srcreg2, dstreg;
 
   PC = cia;
@@ -2408,9 +2555,10 @@
 8.0xfb+8.0x9c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::sub
 "sub"
 *am33
+*am33_2
 {
   int z, c, n, v;
-  unsigned long difference, source1, source2;
+  unsigned32 difference, source1, source2;
   int srcreg1, srcreg2, dstreg;
 
   PC = cia;
@@ -2425,7 +2573,7 @@
 
   z = (difference == 0);
   n = (difference & 0x80000000);
-  c = (source1 > source1);
+  c = (source1 > source2);
   v = ((source1 & 0x80000000) == (source2 & 0x80000000)
        && (source1 & 0x80000000) != (difference & 0x80000000));
 
@@ -2438,9 +2586,10 @@
 8.0xfb+8.0xac+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::subc
 "subc"
 *am33
+*am33_2
 {
   int z, c, n, v;
-  unsigned long difference, source1, source2;
+  unsigned32 difference, source1, source2;
   int srcreg1, srcreg2, dstreg;
 
   PC = cia;
@@ -2468,6 +2617,7 @@
 8.0xfb+8.0x0d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::and
 "and"
 *am33
+*am33_2
 {
   int z, n;
   int srcreg1, srcreg2, dstreg;
@@ -2490,6 +2640,7 @@
 8.0xfb+8.0x1d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::or
 "or"
 *am33
+*am33_2
 {
   int z, n;
   int srcreg1, srcreg2, dstreg;
@@ -2512,6 +2663,7 @@
 8.0xfb+8.0x2d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::xor
 "xor"
 *am33
+*am33_2
 {
   int z, n;
   int srcreg1, srcreg2, dstreg;
@@ -2534,9 +2686,10 @@
 8.0xfb+8.0x4d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asr
 "asr"
 *am33
+*am33_2
 {
   int z, c, n;
-  long temp;
+  signed32 temp;
   int srcreg1, srcreg2, dstreg;
 
   PC = cia;
@@ -2560,6 +2713,7 @@
 8.0xfb+8.0x5d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::lsr
 "lsr"
 *am33
+*am33_2
 {
   int z, c, n;
   int srcreg1, srcreg2, dstreg;
@@ -2583,6 +2737,7 @@
 8.0xfb+8.0x6d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asl
 "asl"
 *am33
+*am33_2
 {
   int z, n;
   int srcreg1, srcreg2, dstreg;
@@ -2592,7 +2747,7 @@
   srcreg2 = translate_rreg (SD_, RN0);
   dstreg = translate_rreg (SD_, RD0);
 
-  State.regs[dstreg] = State.regs[srcreg2] << State.regs[srcreg1];;
+  State.regs[dstreg] = State.regs[srcreg2] << State.regs[srcreg1];
 
   z = (State.regs[dstreg] == 0);
   n = (State.regs[dstreg] & 0x80000000);
@@ -2605,9 +2760,10 @@
 8.0xfb+8.0xad+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mul
 "mul"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
-  signed long long temp;
+  signed64 temp;
   int n, z;
 
   PC = cia;
@@ -2618,11 +2774,11 @@
 
   temp = ((signed64)(signed32)State.regs[srcreg1]
           *  (signed64)(signed32)State.regs[srcreg2]);
-  State.regs[dstreg1] = temp & 0xffffffff;
-  State.regs[dstreg2] = (temp & 0xffffffff00000000LL) >> 32;;
+  State.regs[dstreg2] = temp & 0xffffffff;
+  State.regs[dstreg1] = (temp & 0xffffffff00000000LL) >> 32;
 
   z = (State.regs[dstreg1] == 0) && (State.regs[dstreg2] == 0);
-  n = (State.regs[dstreg2] & 0x80000000);
+  n = (State.regs[dstreg1] & 0x80000000);
 
   PSW &= ~(PSW_Z | PSW_N);
   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
@@ -2632,9 +2788,10 @@
 8.0xfb+8.0xbd+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mulu
 "mulu"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
-  signed long long temp;
+  signed64 temp;
   int n, z;
 
   PC = cia;
@@ -2645,11 +2802,11 @@
 
   temp = ((unsigned64)State.regs[srcreg1]
           *  (unsigned64)State.regs[srcreg2]);
-  State.regs[dstreg1] = temp & 0xffffffff;
-  State.regs[dstreg2] = (temp & 0xffffffff00000000LL) >> 32;;
+  State.regs[dstreg2] = temp & 0xffffffff;
+  State.regs[dstreg1] = (temp & 0xffffffff00000000LL) >> 32;
 
   z = (State.regs[dstreg1] == 0) && (State.regs[dstreg2] == 0);
-  n = (State.regs[dstreg2] & 0x80000000);
+  n = (State.regs[dstreg1] & 0x80000000);
 
   PSW &= ~(PSW_Z | PSW_N);
   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
@@ -2659,6 +2816,7 @@
 8.0xfb+8.0x0e+4.RN2,4.0x0+8.IMM8:D2p:::mov
 "mov"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -2671,6 +2829,7 @@
 8.0xfb+8.0x1e+4.RM2,4.0x0+8.IMM8:D2q:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -2683,6 +2842,7 @@
 8.0xfb+8.0x2e+4.RN2,4.0x0+8.IMM8:D2p:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -2695,6 +2855,7 @@
 8.0xfb+8.0x3e+4.RM2,4.0x0+8.IMM8:D2q:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -2707,6 +2868,7 @@
 8.0xfb+8.0x4e+4.RN2,4.0x0+8.IMM8:D2p:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -2719,6 +2881,7 @@
 8.0xfb+8.0x5e+4.RM2,4.0x0+8.IMM8:D2q:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -2731,12 +2894,13 @@
 8.0xfb+8.0x8e+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM0);
-  srcreg1 = translate_rreg (SD_, RI0);
+  srcreg2 = translate_rreg (SD_, RI0);
   dstreg = translate_rreg (SD_, RN0);
   State.regs[dstreg] = load_word (State.regs[srcreg1] + State.regs[srcreg2]);
 }
@@ -2745,6 +2909,7 @@
 8.0xfb+8.0x9e+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg1, dstreg2;
 
@@ -2759,12 +2924,13 @@
 8.0xfb+8.0xae+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM0);
-  srcreg1 = translate_rreg (SD_, RI0);
+  srcreg2 = translate_rreg (SD_, RI0);
   dstreg = translate_rreg (SD_, RN0);
   State.regs[dstreg] = load_byte (State.regs[srcreg1] + State.regs[srcreg2]);
 }
@@ -2773,6 +2939,7 @@
 8.0xfb+8.0xbe+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int srcreg, dstreg1, dstreg2;
 
@@ -2787,12 +2954,13 @@
 8.0xfb+8.0xce+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM0);
-  srcreg1 = translate_rreg (SD_, RI0);
+  srcreg2 = translate_rreg (SD_, RI0);
   dstreg = translate_rreg (SD_, RN0);
   State.regs[dstreg] = load_half (State.regs[srcreg1] + State.regs[srcreg2]);
 }
@@ -2801,6 +2969,7 @@
 8.0xfb+8.0xde+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg, dstreg1, dstreg2;
 
@@ -2815,10 +2984,11 @@
 8.0xfb+8.0x0f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mac
 "mac"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
-  signed long long temp;
-  unsigned long sum;
+  signed64 temp;
+  unsigned32 sum;
   int c, v;
 
   PC = cia;
@@ -2851,10 +3021,11 @@
 8.0xfb+8.0x1f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::macu
 "macu"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
-  signed long long temp;
-  unsigned long sum;
+  signed64 temp;
+  unsigned32 sum;
   int c, v;
 
   PC = cia;
@@ -2887,9 +3058,10 @@
 8.0xfb+8.0x2f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macb
 "macb"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg;
-  long temp, sum;
+  signed32 temp, sum;
   int v;
 
   PC = cia;
@@ -2915,9 +3087,10 @@
 8.0xfb+8.0x3f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macbu
 "macbu"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg;
-  long temp, sum;
+  signed32 temp, sum;
   int v;
 
   PC = cia;
@@ -2943,9 +3116,10 @@
 8.0xfb+8.0x4f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mach
 "mach"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
-  long long temp, sum;
+  signed64 temp, sum;
   int v;
 
   PC = cia;
@@ -2973,9 +3147,10 @@
 8.0xfb+8.0x5f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::machu
 "machu"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
-  long long temp, sum;
+  signed64 temp, sum;
   int v;
 
   PC = cia;
@@ -3003,9 +3178,10 @@
 8.0xfb+8.0x6f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmach
 "dmach"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg;
-  long temp, temp2, sum;
+  signed32 temp, temp2, sum;
   int v;
 
   PC = cia;
@@ -3033,9 +3209,10 @@
 8.0xfb+8.0x7f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmachu
 "dmachu"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg;
-  long temp, temp2, sum;
+  signed32 temp, temp2, sum;
   int v;
 
   PC = cia;
@@ -3063,9 +3240,10 @@
 8.0xfb+8.0x8f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulh
 "dmulh"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
-  signed long long temp;
+  signed64 temp;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM2);
@@ -3085,9 +3263,10 @@
 8.0xfb+8.0x9f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulhu
 "dmulhu"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
-  signed long long temp;
+  signed64 temp;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM2);
@@ -3107,6 +3286,7 @@
 8.0xfb+8.0xaf+4.RM2,4.RN0+8.0x0:D2:::sat24
 "sat24"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
   int value, n, z;
@@ -3134,6 +3314,7 @@
 8.0xfb+8.0xff+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::bsch
 "bsch"
 *am33
+*am33_2
 {
   int temp, c, i;
   int srcreg1, srcreg2, dstreg;
@@ -3148,7 +3329,8 @@
   start = (State.regs[srcreg2] & 0x1f) - 1;
   if (start == -1)
     start = 31;
-    
+
+  c = 0;    
   for (i = start; i >= 0; i--)
     {
       if (temp & (1 << i))
@@ -3172,6 +3354,7 @@
 8.0xfd+8.0x08+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::mov
 "mov"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -3184,6 +3367,7 @@
 8.0xfd+8.0x18+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4k:::movu
 "movu"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -3196,6 +3380,7 @@
 8.0xfd+8.0x78+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4c:::add
 "add"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -3208,9 +3393,10 @@
 8.0xfd+8.0x88+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::addc
 "addc"
 *am33
+*am33_2
 {
   int dstreg, z, n, c, v;
-  unsigned long sum, imm, reg2;
+  unsigned32 sum, imm, reg2;
 
   PC = cia;
   dstreg = translate_rreg (SD_, RN0);
@@ -3235,6 +3421,7 @@
 8.0xfd+8.0x98+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::sub
 "sub"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -3247,9 +3434,10 @@
 8.0xfd+8.0xa8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::subc
 "subc"
 *am33
+*am33_2
 {
   int dstreg, z, n, c, v;
-  unsigned long difference, imm, reg2;
+  unsigned32 difference, imm, reg2;
 
   PC = cia;
   dstreg = translate_rreg (SD_, RN0);
@@ -3274,6 +3462,7 @@
 8.0xfd+8.0xd8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::cmp
 "cmp"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -3286,6 +3475,7 @@
 8.0xfd+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM24A+8.IMM24B+8.IMM24C:D4o:::mov
 "mov"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -3299,6 +3489,7 @@
 8.0xfd+8.0x09+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::and
 "and"
 *am33
+*am33_2
 {
   int dstreg;
   int z,n;
@@ -3317,6 +3508,7 @@
 8.0xfd+8.0x19+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::or
 "or"
 *am33
+*am33_2
 {
   int dstreg;
   int z,n;
@@ -3335,6 +3527,7 @@
 8.0xfd+8.0x29+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::xor
 "xor"
 *am33
+*am33_2
 {
   int dstreg;
   int z,n;
@@ -3353,9 +3546,10 @@
 8.0xfd+8.0x49+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asr
 "asr"
 *am33
+*am33_2
 {
   int dstreg;
-  long temp;
+  signed32 temp;
   int c, z, n;
 
   PC = cia;
@@ -3376,6 +3570,7 @@
 8.0xfd+8.0x59+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::lsr
 "lsr"
 *am33
+*am33_2
 {
   int dstreg;
   int z, n, c;
@@ -3395,8 +3590,9 @@
 8.0xfd+8.0x69+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asl
 "asl"
 *am33
+*am33_2
 {
-  int srcreg, dstreg;
+  int dstreg;
   int z, n;
 
   PC = cia;
@@ -3413,9 +3609,10 @@
 8.0xfd+8.0xa9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mul
 "mul"
 *am33
+*am33_2
 {
   int dstreg;
-  unsigned long long temp;
+  unsigned64 temp;
   int z, n;
 
   PC = cia;
@@ -3424,7 +3621,7 @@
   temp = ((signed64)(signed32)State.regs[dstreg]
           *  (signed64)(signed32)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)));
   State.regs[dstreg] = temp & 0xffffffff;
-  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
+  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
   z = (State.regs[dstreg] == 0);
   n = (State.regs[dstreg] & 0x80000000) != 0;
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
@@ -3435,9 +3632,10 @@
 8.0xfd+8.0xb9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mulu
 "mulu"
 *am33
+*am33_2
 {
   int dstreg;
-  unsigned long long temp;
+  unsigned64 temp;
   int z, n;
 
   PC = cia;
@@ -3446,7 +3644,7 @@
   temp = ((unsigned64)State.regs[dstreg]
           *  (unsigned64)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)));
   State.regs[dstreg] = temp & 0xffffffff;
-  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
+  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
   z = (State.regs[dstreg] == 0);
   n = (State.regs[dstreg] & 0x80000000) != 0;
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
@@ -3457,6 +3655,7 @@
 8.0xfd+8.0xe9+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::btst
 "btst"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -3469,6 +3668,7 @@
 8.0xfd+8.0x0a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -3484,6 +3684,7 @@
 8.0xfd+8.0x1a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -3498,6 +3699,7 @@
 8.0xfd+8.0x2a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -3513,6 +3715,7 @@
 8.0xfd+8.0x3a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -3527,6 +3730,7 @@
 8.0xfd+8.0x4a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -3542,6 +3746,7 @@
 8.0xfd+8.0x5a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -3556,6 +3761,7 @@
 8.0xfd+8.0x6a+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -3567,9 +3773,10 @@
 }
 
 // 1111 1101 0111 1010 Rm Rn IMM24; mov Rm,(d24,Rn+)
-8.0xfd+8.0x7a+4.RM2,4.RN0!RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mov
+8.0xfd+8.0x7a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -3585,53 +3792,55 @@
 8.0xfd+8.0x8a+4.RN2,4.0x0+IMM24A+8.IMM24B+8.IMM24C:D4r:::mov
 "mov"
 *am33
+*am33_2
 {
   int dstreg;
 
   PC = cia;
   dstreg = translate_rreg (SD_, RN2);
   State.regs[dstreg] = load_word (State.regs[REG_SP]
-                                 + EXTEND24 (FETCH24 (IMM24A,
-                                                      IMM24B, IMM24C)));
+                                 + FETCH24 (IMM24A, IMM24B, IMM24C));
 }
 
 // 1111 1101 1001 1010 Rm 0000 IMM24; mov Rm,(d24,sp)
 8.0xfd+8.0x9a+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg;
 
   PC = cia;
   srcreg = translate_rreg (SD_, RM2);
-  store_word (State.regs[REG_SP] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
+  store_word (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
              State.regs[srcreg]);
 }
 
-// 1111 1101 1010 1010 Rn 0000 IMM24; movbu (d24,Rm),Rn
+// 1111 1101 1010 1010 Rn 0000 IMM24; movbu (d24,sp),Rn
 8.0xfd+8.0xaa+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int dstreg;
 
   PC = cia;
   dstreg = translate_rreg (SD_, RN2);
   State.regs[dstreg] = load_byte (State.regs[REG_SP]
-                                 + EXTEND24 (FETCH24 (IMM24A,
-                                                      IMM24B, IMM24C)));
+                                 + FETCH24 (IMM24A, IMM24B, IMM24C));
 }
 
 // 1111 1101 1011 1010 Rm 0000 IMM24; movbu Rm,(d24,sp)
 8.0xfd+8.0xba+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int srcreg;
 
   PC = cia;
   srcreg = translate_rreg (SD_, RM2);
-  store_byte (State.regs[REG_SP] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
+  store_byte (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
              State.regs[srcreg]);
 }
 
@@ -3639,26 +3848,27 @@
 8.0xfd+8.0xca+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int dstreg;
 
   PC = cia;
   dstreg = translate_rreg (SD_, RN2);
   State.regs[dstreg] = load_half (State.regs[REG_SP]
-                                 + EXTEND24 (FETCH24 (IMM24A,
-                                                      IMM24B, IMM24C)));
+                                 + FETCH24 (IMM24A, IMM24B, IMM24C));
 }
 
 // 1111 1101 1101 1010 Rm Rn IMM24; movhu Rm,(d24,sp)
 8.0xfd+8.0xda+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg;
 
   PC = cia;
   srcreg = translate_rreg (SD_, RM2);
-  store_half (State.regs[REG_SP] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
+  store_half (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
              State.regs[srcreg]);
 }
 
@@ -3666,6 +3876,7 @@
 8.0xfd+8.0xea+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -3677,9 +3888,10 @@
 }
 
 // 1111 1101 1111 1010 Rm Rn IMM24; movhu Rm,(d24,Rn+)
-8.0xfd+8.0xfa+4.RM2,4.RN0!RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::movhu
+8.0xfd+8.0xfa+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -3694,9 +3906,10 @@
 8.0xfd+8.0x0b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mac
 "mac"
 *am33
+*am33_2
 {
   int srcreg;
-  long long temp, sum;
+  signed64 temp, sum;
   int c, v;
 
   PC = cia;
@@ -3721,9 +3934,10 @@
 8.0xfd+8.0x1b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macu
 "macu"
 *am33
+*am33_2
 {
   int srcreg;
-  long long temp, sum;
+  signed64 temp, sum;
   int c, v;
 
   PC = cia;
@@ -3748,9 +3962,10 @@
 8.0xfd+8.0x2b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macb
 "macb"
 *am33
+*am33_2
 {
   int srcreg;
-  long long temp, sum;
+  signed64 temp, sum;
   int c, v;
 
   PC = cia;
@@ -3775,9 +3990,10 @@
 8.0xfd+8.0x3b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macbu
 "macbu"
 *am33
+*am33_2
 {
   int srcreg;
-  long long temp, sum;
+  signed64 temp, sum;
   int c, v;
 
   PC = cia;
@@ -3802,9 +4018,10 @@
 8.0xfd+8.0x4b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mach
 "mach"
 *am33
+*am33_2
 {
   int srcreg;
-  long long temp, sum;
+  signed64 temp, sum;
   int c, v;
 
   PC = cia;
@@ -3829,9 +4046,10 @@
 8.0xfd+8.0x5b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::machu
 "machu"
 *am33
+*am33_2
 {
   int srcreg;
-  long long temp, sum;
+  signed64 temp, sum;
   int c, v;
 
   PC = cia;
@@ -3856,6 +4074,7 @@
 8.0xfd+8.0x0e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::mov
 "mov"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -3868,6 +4087,7 @@
 8.0xfd+8.0x1e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4v:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -3881,6 +4101,7 @@
 8.0xfd+8.0x2e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -3893,6 +4114,7 @@
 8.0xfd+8.0x3e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -3906,6 +4128,7 @@
 8.0xfd+8.0x4e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -3918,6 +4141,7 @@
 8.0xfd+8.0x5e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -3931,6 +4155,7 @@
 8.0xfe+8.0x08+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mov
 "mov"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -3943,6 +4168,7 @@
 8.0xfe+8.0x18+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movu
 "movu"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -3955,6 +4181,7 @@
 8.0xfe+8.0x78+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::add
 "add"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -3967,9 +4194,10 @@
 8.0xfe+8.0x88+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::addc
 "addc"
 *am33
+*am33_2
 {
   int dstreg;
-  unsigned int imm, reg2, sum;
+  unsigned32 imm, reg2, sum;
   int z, n, c, v;
 
   PC = cia;
@@ -3995,6 +4223,7 @@
 8.0xfe+8.0x98+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::sub
 "sub"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -4007,9 +4236,10 @@
 8.0xfe+8.0xa8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::subc
 "subc"
 *am33
+*am33_2
 {
   int dstreg;
-  unsigned int imm, reg2, difference;
+  unsigned32 imm, reg2, difference;
   int z, n, c, v;
 
   PC = cia;
@@ -4035,6 +4265,7 @@
 8.0xfe+8.0xd8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::cmp
 "cmp"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -4047,6 +4278,7 @@
 8.0xfe+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::mov
 "mov"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -4060,6 +4292,7 @@
 8.0xfe+8.0x09+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::and
 "and"
 *am33
+*am33_2
 {
   int dstreg;
   int z,n;
@@ -4078,6 +4311,7 @@
 8.0xfe+8.0x19+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::or
 "or"
 *am33
+*am33_2
 {
   int dstreg;
   int z,n;
@@ -4096,6 +4330,7 @@
 8.0xfe+8.0x29+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::xor
 "xor"
 *am33
+*am33_2
 {
   int dstreg;
   int z,n;
@@ -4114,9 +4349,10 @@
 8.0xfe+8.0x49+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asr
 "asr"
 *am33
+*am33_2
 {
   int dstreg;
-  long temp;
+  signed32 temp;
   int c, z, n;
 
   PC = cia;
@@ -4136,6 +4372,7 @@
 8.0xfe+8.0x59+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::lsr
 "lsr"
 *am33
+*am33_2
 {
   int dstreg;
   int z, n, c;
@@ -4155,8 +4392,9 @@
 8.0xfe+8.0x69+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asl
 "asl"
 *am33
+*am33_2
 {
-  int srcreg, dstreg;
+  int dstreg;
   int z, n;
 
   PC = cia;
@@ -4173,9 +4411,10 @@
 8.0xfe+8.0xa9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mul
 "mul"
 *am33
+*am33_2
 {
   int dstreg;
-  unsigned long long temp;
+  unsigned64 temp;
   int z, n;
 
   PC = cia;
@@ -4184,7 +4423,7 @@
   temp = ((signed64)(signed32)State.regs[dstreg]
           *  (signed64)(signed32)(FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)));
   State.regs[dstreg] = temp & 0xffffffff;
-  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
+  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
   z = (State.regs[dstreg] == 0);
   n = (State.regs[dstreg] & 0x80000000) != 0;
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
@@ -4195,9 +4434,10 @@
 8.0xfe+8.0xb9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mulu
 "mulu"
 *am33
+*am33_2
 {
   int dstreg;
-  unsigned long long temp;
+  unsigned64 temp;
   int z, n;
 
   PC = cia;
@@ -4206,7 +4446,7 @@
   temp = ((unsigned64)State.regs[dstreg]
           *  (unsigned64) (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)));
   State.regs[dstreg] = temp & 0xffffffff;
-  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
+  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
   z = (State.regs[dstreg] == 0);
   n = (State.regs[dstreg] & 0x80000000) != 0;
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
@@ -4217,6 +4457,7 @@
 8.0xfe+8.0xe9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::btst
 "btst"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -4229,6 +4470,7 @@
 8.0xfe+8.0x0a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -4243,6 +4485,7 @@
 8.0xfe+8.0x1a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5g:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -4257,6 +4500,7 @@
 8.0xfe+8.0x2a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -4271,6 +4515,7 @@
 8.0xfe+8.0x3a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -4285,6 +4530,7 @@
 8.0xfe+8.0x4a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -4299,6 +4545,7 @@
 8.0xfe+8.0x5a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -4313,6 +4560,7 @@
 8.0xfe+8.0x6a+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -4324,9 +4572,10 @@
 }
 
 // 1111 1110 0111 1010 Rm Rn IMM32; mov Rm,(d32,Rn+)
-8.0xfe+8.0x7a+4.RM2,4.RN0!RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5z:::mov
+8.0xfe+8.0x7a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5z:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -4342,6 +4591,7 @@
 8.0xfe+8.0x8a+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::mov
 "mov"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -4355,6 +4605,7 @@
 8.0xfe+8.0x9a+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -4368,6 +4619,7 @@
 8.0xfe+8.0xaa+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -4381,6 +4633,7 @@
 8.0xfe+8.0xba+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -4394,6 +4647,7 @@
 8.0xfe+8.0xca+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -4407,6 +4661,7 @@
 8.0xfe+8.0xda+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -4421,6 +4676,7 @@
 8.0xfe+8.0xea+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -4432,9 +4688,10 @@
 }
 
 // 1111 1110 1111 1010 Rm Rn IMM32; movhu Rm,(d32,Rn+)
-8.0xfe+8.0xfa+4.RM2,4.RN0!RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::movhu
+8.0xfe+8.0xfa+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -4450,9 +4707,10 @@
 8.0xfe+8.0x0b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mac
 "mac"
 *am33
+*am33_2
 {
   int srcreg, imm;
-  long long temp, sum;
+  signed64 temp, sum;
   int c, v;
 
   PC = cia;
@@ -4478,9 +4736,10 @@
 8.0xfe+8.0x1b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macu
 "macu"
 *am33
+*am33_2
 {
   int srcreg, imm;
-  long long temp, sum;
+  signed64 temp, sum;
   int c, v;
 
   PC = cia;
@@ -4506,9 +4765,10 @@
 8.0xfe+8.0x2b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macb
 "macb"
 *am33
+*am33_2
 {
   int srcreg, imm;
-  long temp, sum;
+  signed32 temp, sum;
   int v;
 
   PC = cia;
@@ -4529,9 +4789,10 @@
 8.0xfe+8.0x3b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macbu
 "macbu"
 *am33
+*am33_2
 {
   int srcreg, imm;
-  long temp, sum;
+  signed32 temp, sum;
   int v;
 
   PC = cia;
@@ -4552,9 +4813,10 @@
 8.0xfe+8.0x4b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mach
 "mach"
 *am33
+*am33_2
 {
   int srcreg, imm;
-  long temp, sum;
+  signed32 temp, sum;
   int v;
 
   PC = cia;
@@ -4575,9 +4837,10 @@
 8.0xfe+8.0x5b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::machu
 "machu"
 *am33
+*am33_2
 {
   int srcreg, imm;
-  long temp, sum;
+  signed32 temp, sum;
   int v;
 
   PC = cia;
@@ -4598,9 +4861,10 @@
 8.0xfe+8.0x6b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmach
 "dmach"
 *am33
+*am33_2
 {
   int srcreg, imm;
-  long temp, temp2, sum;
+  signed32 temp, temp2, sum;
   int v;
 
   PC = cia;
@@ -4623,9 +4887,10 @@
 8.0xfe+8.0x7b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmachu
 "dmachu"
 *am33
+*am33_2
 {
   int srcreg, imm;
-  long temp, temp2, sum;
+  signed32 temp, temp2, sum;
   int v;
 
   PC = cia;
@@ -4648,9 +4913,10 @@
 8.0xfe+8.0x8b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulh
 "dmulh"
 *am33
+*am33_2
 {
   int imm, dstreg;
-  long temp;
+  signed32 temp;
 
   PC = cia;
   dstreg = translate_rreg (SD_, RN0);
@@ -4668,9 +4934,10 @@
 8.0xfe+8.0x9b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulhu
 "dmulhu"
 *am33
+*am33_2
 {
   int imm, dstreg;
-  long temp;
+  signed32 temp;
 
   PC = cia;
   dstreg = translate_rreg (SD_, RN0);
@@ -4688,6 +4955,7 @@
 8.0xfe+8.0x0e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5h:::mov
 "mov"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -4700,6 +4968,7 @@
 8.0xfe+8.0x1e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::mov
 "mov"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -4712,6 +4981,7 @@
 8.0xfe+8.0x2e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5i:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -4724,6 +4994,7 @@
 8.0xfe+8.0x3e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movbu
 "movbu"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -4736,6 +5007,7 @@
 8.0xfe+8.0x4e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5j:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int dstreg;
 
@@ -4748,6 +5020,7 @@
 8.0xfe+8.0x5e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movhu
 "movhu"
 *am33
+*am33_2
 {
   int srcreg;
 
@@ -4757,11 +5030,13 @@
 }
 
 // 1111 0111 0000 0000 Rm1 Rn1 Rm2 Rn2; add_add Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x00+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_add
+8.0xf7+8.0x00+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_add
 "add_add"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -4769,32 +5044,38 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += State.regs[srcreg1];
+  result1 = State.regs[dstreg1] + State.regs[srcreg1];
   State.regs[dstreg2] += State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0001 0000 Rm1 Rn1 imm4 Rn2; add_add Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x10+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_add
+8.0xf7+8.0x10+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_add
 "add_add"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += State.regs[srcreg1];
+  result1 = State.regs[dstreg1] + State.regs[srcreg1];
   State.regs[dstreg2] += EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0010 0000 Rm1 Rn1 Rm2 Rn2; add_sub Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x20+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_sub
+8.0xf7+8.0x20+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_sub
 "add_sub"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -4802,30 +5083,35 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += State.regs[srcreg1];
+  result1 = State.regs[dstreg1] + State.regs[srcreg1];
   State.regs[dstreg2] -= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0011 0000 Rm1 Rn1 imm4 Rn2; add_sub Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x30+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_sub
+8.0xf7+8.0x30+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_sub
 "add_sub"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += State.regs[srcreg1];
+  result1 = State.regs[dstreg1] + State.regs[srcreg1];
   State.regs[dstreg2] -= EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0100 0000 Rm1 Rn1 Rm2 Rn2; add_cmp Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x40+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_cmp
+8.0xf7+8.0x40+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_cmp
 "add_cmp"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
 
@@ -4835,14 +5121,15 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += State.regs[srcreg1];
   genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+  State.regs[dstreg1] += State.regs[srcreg1];
 }
 
 // 1111 0111 0101 0000 Rm1 Rn1 imm4 Rn2; add_cmp Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x50+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_cmp
+8.0xf7+8.0x50+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_cmp
 "add_cmp"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
 
@@ -4851,16 +5138,18 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += State.regs[srcreg1];
   genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+  State.regs[dstreg1] += State.regs[srcreg1];
 }
   
 // 1111 0111 0110 0000 Rm1 Rn1 Rm2 Rn2; add_mov Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x60+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_mov
+8.0xf7+8.0x60+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_mov
 "add_mov"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -4868,32 +5157,38 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += State.regs[srcreg1];
+  result1 = State.regs[dstreg1] + State.regs[srcreg1];
   State.regs[dstreg2] = State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0111 0000 Rm1 Rn1 imm4 Rn2; add_mov Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x70+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_mov
+8.0xf7+8.0x70+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_mov
 "add_mov"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += State.regs[srcreg1];
+  result1 = State.regs[dstreg1] + State.regs[srcreg1];
   State.regs[dstreg2] = EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1000 0000 Rm1 Rn1 Rm2 Rn2; add_asr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x80+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_asr
+8.0xf7+8.0x80+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_asr
 "add_asr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -4902,18 +5197,21 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += State.regs[srcreg1];
+  result1 = State.regs[dstreg1] + State.regs[srcreg1];
   temp = State.regs[dstreg2];
   temp >>= State.regs[srcreg2];
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1001 0000 Rm1 Rn1 imm4 Rn2; add_asr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x90+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_asr
+8.0xf7+8.0x90+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_asr
 "add_asr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -4921,18 +5219,21 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += State.regs[srcreg1];
+  result1 = State.regs[dstreg1] + State.regs[srcreg1];
   temp = State.regs[dstreg2];
   temp >>= IMM4;
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1010 0000 Rm1 Rn1 Rm2 Rn2; add_lsr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xa0+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_lsr
+8.0xf7+8.0xa0+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_lsr
 "add_lsr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -4940,34 +5241,39 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += State.regs[srcreg1];
+  result1 = State.regs[dstreg1] + State.regs[srcreg1];
   State.regs[dstreg2] >>= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1011 0000 Rm1 Rn1 imm4 Rn2; add_lsr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xb0+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_lsr
+8.0xf7+8.0xb0+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_lsr
 "add_lsr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  signed int temp;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += State.regs[srcreg1];
+  result1 = State.regs[dstreg1] + State.regs[srcreg1];
   State.regs[dstreg2] >>= IMM4;
+  State.regs[dstreg1] = result1;
 }
   
   
 // 1111 0111 1100 0000 Rm1 Rn1 Rm2 Rn2; add_asl Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xc0+4.RM1,4.RN1+4.RM2,4.RN2:D2:::add_asl
+8.0xf7+8.0xc0+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_asl
 "add_asl"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -4975,31 +5281,35 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += State.regs[srcreg1];
+  result1 = State.regs[dstreg1] + State.regs[srcreg1];
   State.regs[dstreg2] <<= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1101 0000 Rm1 Rn1 imm4 Rn2; add_asl Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xd0+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::add_asl
+8.0xf7+8.0xd0+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_asl
 "add_asl"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  signed int temp;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += State.regs[srcreg1];
+  result1 = State.regs[dstreg1] + State.regs[srcreg1];
   State.regs[dstreg2] <<= IMM4;
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0000 0001 Rm1 Rn1 Rm2 Rn2; cmp_add Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x01+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_add
+8.0xf7+8.0x01+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_add
 "cmp_add"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
 
@@ -5014,9 +5324,10 @@
 }
 
 // 1111 0111 0001 0001 Rm1 Rn1 imm4 Rn2; cmp_add Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x11+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_add
+8.0xf7+8.0x11+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_add
 "cmp_add"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
 
@@ -5030,9 +5341,10 @@
 }
   
 // 1111 0111 0010 0001 Rm1 Rn1 Rm2 Rn2; cmp_sub Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x21+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_sub
+8.0xf7+8.0x21+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_sub
 "cmp_sub"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
 
@@ -5047,9 +5359,10 @@
 }
 
 // 1111 0111 0011 0001 Rm1 Rn1 imm4 Rn2; cmp_sub Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x31+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_sub
+8.0xf7+8.0x31+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_sub
 "cmp_sub"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
 
@@ -5063,9 +5376,10 @@
 }
   
 // 1111 0111 0110 0001 Rm1 Rn1 Rm2 Rn2; cmp_mov Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x61+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_mov
+8.0xf7+8.0x61+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_mov
 "cmp_mov"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
 
@@ -5080,9 +5394,10 @@
 }
 
 // 1111 0111 0111 0001 Rm1 Rn1 imm4 Rn2; cmp_mov Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x71+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_mov
+8.0xf7+8.0x71+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_mov
 "cmp_mov"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
 
@@ -5096,9 +5411,10 @@
 }
   
 // 1111 0111 1000 0001 Rm1 Rn1 Rm2 Rn2; cmp_asr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x81+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_asr
+8.0xf7+8.0x81+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_asr
 "cmp_asr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
   signed int temp;
@@ -5116,9 +5432,10 @@
 }
 
 // 1111 0111 1001 0001 Rm1 Rn1 imm4 Rn2; cmp_asr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x91+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_asr
+8.0xf7+8.0x91+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_asr
 "cmp_asr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
   signed int temp;
@@ -5135,9 +5452,10 @@
 }
 
 // 1111 0111 1010 0001 Rm1 Rn1 Rm2 Rn2; cmp_lsr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xa1+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_lsr
+8.0xf7+8.0xa1+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_lsr
 "cmp_lsr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
 
@@ -5152,12 +5470,12 @@
 }
 
 // 1111 0111 1011 0001 Rm1 Rn1 imm4 Rn2; cmp_lsr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xb1+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_lsr
+8.0xf7+8.0xb1+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_lsr
 "cmp_lsr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  signed int temp;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -5170,9 +5488,10 @@
   
   
 // 1111 0111 1100 0001 Rm1 Rn1 Rm2 Rn2; cmp_asl Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xc1+4.RM1,4.RN1+4.RM2,4.RN2:D2:::cmp_asl
+8.0xf7+8.0xc1+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_asl
 "cmp_asl"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
 
@@ -5187,12 +5506,12 @@
 }
 
 // 1111 0111 1101 0001 Rm1 Rn1 imm4 Rn2; cmp_asl Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xd1+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::cmp_asl
+8.0xf7+8.0xd1+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_asl
 "cmp_asl"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  signed int temp;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -5204,11 +5523,13 @@
 }
 
 // 1111 0111 0000 0010 Rm1 Rn1 Rm2 Rn2; sub_add Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x02+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_add
+8.0xf7+8.0x02+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_add
 "sub_add"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -5216,32 +5537,38 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] - State.regs[srcreg1];
   State.regs[dstreg2] += State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0001 0010 Rm1 Rn1 imm4 Rn2; sub_add Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x12+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_add
+8.0xf7+8.0x12+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_add
 "sub_add"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] - State.regs[srcreg1];
   State.regs[dstreg2] += EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0010 0010 Rm1 Rn1 Rm2 Rn2; sub_sub Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x22+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_sub
+8.0xf7+8.0x22+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_sub
 "sub_sub"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -5249,30 +5576,35 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] - State.regs[srcreg1];
   State.regs[dstreg2] -= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0011 0010 Rm1 Rn1 imm4 Rn2; sub_sub Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x32+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_sub
+8.0xf7+8.0x32+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_sub
 "sub_sub"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] - State.regs[srcreg1];
   State.regs[dstreg2] -= EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0100 0010 Rm1 Rn1 Rm2 Rn2; sub_cmp Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x42+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_cmp
+8.0xf7+8.0x42+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_cmp
 "sub_cmp"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
 
@@ -5282,14 +5614,15 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= State.regs[srcreg1];
   genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+  State.regs[dstreg1] -= State.regs[srcreg1];
 }
 
 // 1111 0111 0101 0010 Rm1 Rn1 imm4 Rn2; sub_cmp Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x52+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_cmp
+8.0xf7+8.0x52+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_cmp
 "sub_cmp"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
 
@@ -5298,16 +5631,18 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= State.regs[srcreg1];
   genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+  State.regs[dstreg1] -= State.regs[srcreg1];
 }
   
 // 1111 0111 0110 0010 Rm1 Rn1 Rm2 Rn2; sub_mov Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x62+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_mov
+8.0xf7+8.0x62+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_mov
 "sub_mov"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -5315,32 +5650,38 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] - State.regs[srcreg1];
   State.regs[dstreg2] = State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0111 0010 Rm1 Rn1 imm4 Rn2; sub_mov Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x72+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_mov
+8.0xf7+8.0x72+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_mov
 "sub_mov"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] - State.regs[srcreg1];
   State.regs[dstreg2] = EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1000 0010 Rm1 Rn1 Rm2 Rn2; sub_asr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x82+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_asr
+8.0xf7+8.0x82+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_asr
 "sub_asr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -5349,18 +5690,21 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] - State.regs[srcreg1];
   temp = State.regs[dstreg2];
   temp >>= State.regs[srcreg2];
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1001 0010 Rm1 Rn1 imm4 Rn2; sub_asr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x92+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_asr
+8.0xf7+8.0x92+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_asr
 "sub_asr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -5368,18 +5712,21 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] - State.regs[srcreg1];
   temp = State.regs[dstreg2];
   temp >>= IMM4;
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1010 0010 Rm1 Rn1 Rm2 Rn2; sub_lsr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xa2+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_lsr
+8.0xf7+8.0xa2+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_lsr
 "sub_lsr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -5387,34 +5734,39 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] - State.regs[srcreg1];
   State.regs[dstreg2] >>= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1011 0010 Rm1 Rn1 imm4 Rn2; sub_lsr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xb2+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_lsr
+8.0xf7+8.0xb2+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_lsr
 "sub_lsr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  signed int temp;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] - State.regs[srcreg1];
   State.regs[dstreg2] >>= IMM4;
+  State.regs[dstreg1] = result1;
 }
   
   
 // 1111 0111 1100 0010 Rm1 Rn1 Rm2 Rn2; sub_asl Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xc2+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sub_asl
+8.0xf7+8.0xc2+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_asl
 "sub_asl"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -5422,33 +5774,38 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] - State.regs[srcreg1];
   State.regs[dstreg2] <<= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1101 0010 Rm1 Rn1 imm4 Rn2; sub_asl Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xd2+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sub_asl
+8.0xf7+8.0xd2+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_asl
 "sub_asl"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  signed int temp;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] - State.regs[srcreg1];
   State.regs[dstreg2] <<= IMM4;
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0000 0011 Rm1 Rn1 Rm2 Rn2; mov_add Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x03+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_add
+8.0xf7+8.0x03+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_add
 "mov_add"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -5456,32 +5813,38 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = State.regs[srcreg1];
+  result1 = State.regs[srcreg1];
   State.regs[dstreg2] += State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0001 0011 Rm1 Rn1 imm4 Rn2; mov_add Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x13+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_add
+8.0xf7+8.0x13+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_add
 "mov_add"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = State.regs[srcreg1];
+  result1 = State.regs[srcreg1];
   State.regs[dstreg2] += EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0010 0011 Rm1 Rn1 Rm2 Rn2; mov_sub Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x23+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_sub
+8.0xf7+8.0x23+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_sub
 "mov_sub"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -5489,30 +5852,35 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = State.regs[srcreg1];
+  result1 = State.regs[srcreg1];
   State.regs[dstreg2] -= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0011 0011 Rm1 Rn1 imm4 Rn2; mov_sub Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x33+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_sub
+8.0xf7+8.0x33+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_sub
 "mov_sub"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = State.regs[srcreg1];
+  result1 = State.regs[srcreg1];
   State.regs[dstreg2] -= EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0100 0011 Rm1 Rn1 Rm2 Rn2; mov_cmp Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x43+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_cmp
+8.0xf7+8.0x43+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_cmp
 "mov_cmp"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
 
@@ -5522,14 +5890,15 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = State.regs[srcreg1];
   genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+  State.regs[dstreg1] = State.regs[srcreg1];
 }
 
 // 1111 0111 0101 0011 Rm1 Rn1 imm4 Rn2; mov_cmp Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x53+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_cmp
+8.0xf7+8.0x53+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_cmp
 "mov_cmp"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
 
@@ -5538,16 +5907,18 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = State.regs[srcreg1];
   genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+  State.regs[dstreg1] = State.regs[srcreg1];
 }
   
 // 1111 0111 0110 0011 Rm1 Rn1 Rm2 Rn2; mov_mov Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x63+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_mov
+8.0xf7+8.0x63+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_mov
 "mov_mov"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -5555,32 +5926,38 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = State.regs[srcreg1];
+  result1 = State.regs[srcreg1];
   State.regs[dstreg2] = State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0111 0011 Rm1 Rn1 imm4 Rn2; mov_mov Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x73+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_mov
+8.0xf7+8.0x73+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_mov
 "mov_mov"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = State.regs[srcreg1];
+  result1 = State.regs[srcreg1];
   State.regs[dstreg2] = EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1000 0011 Rm1 Rn1 Rm2 Rn2; mov_asr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x83+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_asr
+8.0xf7+8.0x83+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_asr
 "mov_asr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -5589,18 +5966,21 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = State.regs[srcreg1];
+  result1 = State.regs[srcreg1];
   temp = State.regs[dstreg2];
   temp >>= State.regs[srcreg2];
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1001 0011 Rm1 Rn1 imm4 Rn2; mov_asr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x93+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_asr
+8.0xf7+8.0x93+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_asr
 "mov_asr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -5608,18 +5988,21 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = State.regs[srcreg1];
+  result1 = State.regs[srcreg1];
   temp = State.regs[dstreg2];
   temp >>= IMM4;
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1010 0011 Rm1 Rn1 Rm2 Rn2; mov_lsr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xa3+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_lsr
+8.0xf7+8.0xa3+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_lsr
 "mov_lsr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -5627,34 +6010,39 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = State.regs[srcreg1];
+  result1 = State.regs[srcreg1];
   State.regs[dstreg2] >>= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1011 0011 Rm1 Rn1 imm4 Rn2; mov_lsr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xb3+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_lsr
+8.0xf7+8.0xb3+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_lsr
 "mov_lsr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  signed int temp;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = State.regs[srcreg1];
+  result1 = State.regs[srcreg1];
   State.regs[dstreg2] >>= IMM4;
+  State.regs[dstreg1] = result1;
 }
   
   
 // 1111 0111 1100 0011 Rm1 Rn1 Rm2 Rn2; mov_asl Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xc3+4.RM1,4.RN1+4.RM2,4.RN2:D2:::mov_asl
+8.0xf7+8.0xc3+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_asl
 "mov_asl"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -5662,93 +6050,109 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = State.regs[srcreg1];
+  result1 = State.regs[srcreg1];
   State.regs[dstreg2] <<= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1101 0011 Rm1 Rn1 imm4 Rn2; mov_asl Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xd3+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::mov_asl
+8.0xf7+8.0xd3+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_asl
 "mov_asl"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  signed int temp;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = State.regs[srcreg1];
+  result1 = State.regs[srcreg1];
   State.regs[dstreg2] <<= IMM4;
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0000 0100 imm4 Rn1 Rm2 Rn2; add_add imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x04+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_add
+8.0xf7+8.0x04+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_add
 "add_add"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg2 = translate_rreg (SD_, RM2);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
   State.regs[dstreg2] += State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0001 0100 imm4 Rn1 imm4 Rn2; add_add imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x14+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_add
+8.0xf7+8.0x14+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_add
 "add_add"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
   State.regs[dstreg2] += EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0010 0100 imm4 Rn1 Rm2 Rn2; add_sub imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x24+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_sub
+8.0xf7+8.0x24+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_sub
 "add_sub"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg2 = translate_rreg (SD_, RM2);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
   State.regs[dstreg2] -= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0011 0100 imm4 Rn1 imm4 Rn2; add_sub imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x34+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_sub
+8.0xf7+8.0x34+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_sub
 "add_sub"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
   State.regs[dstreg2] -= EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0100 0100 imm4 Rn1 Rm2 Rn2; add_cmp imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x44+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_cmp
+8.0xf7+8.0x44+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_cmp
 "add_cmp"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
 
@@ -5757,14 +6161,15 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += EXTEND4 (IMM4A);
   genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+  State.regs[dstreg1] += EXTEND4 (IMM4A);
 }
 
 // 1111 0111 0101 0100 imm4 Rn1 imm4 Rn2; add_cmp imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x54+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_cmp
+8.0xf7+8.0x54+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_cmp
 "add_cmp"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
 
@@ -5772,47 +6177,55 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += EXTEND4 (IMM4A);
   genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+  State.regs[dstreg1] += EXTEND4 (IMM4A);
 }
   
 // 1111 0111 0110 0100 imm4 Rn1 Rm2 Rn2; add_mov imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x64+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_mov
+8.0xf7+8.0x64+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_mov
 "add_mov"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg2 = translate_rreg (SD_, RM2);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
   State.regs[dstreg2] = State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0111 0100 imm4 Rn1 imm4 Rn2; add_mov imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x74+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_mov
+8.0xf7+8.0x74+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_mov
 "add_mov"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
   State.regs[dstreg2] = EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1000 0100 imm4 Rn1 Rm2 Rn2; add_asr imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x84+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_asr
+8.0xf7+8.0x84+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_asr
 "add_asr"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -5820,99 +6233,114 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
   temp = State.regs[dstreg2];
   temp >>= State.regs[srcreg2];
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1001 0100 imm4 Rn1 imm4 Rn2; add_asr imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x94+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_asr
+8.0xf7+8.0x94+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_asr
 "add_asr"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
   temp = State.regs[dstreg2];
   temp >>= IMM4;
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1010 0100 imm4 Rn1 Rm2 Rn2; add_lsr imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0xa4+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_lsr
+8.0xf7+8.0xa4+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_lsr
 "add_lsr"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg2 = translate_rreg (SD_, RM2);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
   State.regs[dstreg2] >>= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1011 0100 imm4 Rn1 imm4 Rn2; add_lsr imm4, Rn1, imm4, Rn2
-8.0xf7+8.0xb4+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_lsr
+8.0xf7+8.0xb4+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_lsr
 "add_lsr"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
-  signed int temp;
+  int result1;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
   State.regs[dstreg2] >>= IMM4;
+  State.regs[dstreg1] = result1;
 }
   
   
 // 1111 0111 1100 0100 imm4 Rn1 Rm2 Rn2; add_asl imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0xc4+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::add_asl
+8.0xf7+8.0xc4+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_asl
 "add_asl"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg2 = translate_rreg (SD_, RM2);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
   State.regs[dstreg2] <<= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1101 0100 imm4 Rn1 imm4 Rn2; add_asl imm4, Rn1, imm4, Rn2
-8.0xf7+8.0xd4+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::add_asl
+8.0xf7+8.0xd4+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_asl
 "add_asl"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
-  signed int temp;
+  int result1;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] += EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
   State.regs[dstreg2] <<= IMM4;
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0000 0101 imm4 Rn1 Rm2 Rn2; cmp_add imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x05+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_add
+8.0xf7+8.0x05+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_add
 "cmp_add"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
 
@@ -5926,9 +6354,10 @@
 }
 
 // 1111 0111 0001 0101 imm4 Rn1 imm4 Rn2; cmp_add imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x15+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_add
+8.0xf7+8.0x15+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_add
 "cmp_add"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
 
@@ -5941,9 +6370,10 @@
 }
   
 // 1111 0111 0010 0101 imm4 Rn1 Rm2 Rn2; cmp_sub imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x25+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_sub
+8.0xf7+8.0x25+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_sub
 "cmp_sub"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
 
@@ -5957,9 +6387,10 @@
 }
 
 // 1111 0111 0011 0101 imm4 Rn1 imm4 Rn2; cmp_sub imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x35+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_sub
+8.0xf7+8.0x35+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_sub
 "cmp_sub"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
 
@@ -5972,9 +6403,10 @@
 }
   
 // 1111 0111 0110 0101 imm4 Rn1 Rm2 Rn2; cmp_mov imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x65+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_mov
+8.0xf7+8.0x65+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_mov
 "cmp_mov"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
 
@@ -5988,9 +6420,10 @@
 }
 
 // 1111 0111 0111 0101 imm4 Rn1 imm4 Rn2; cmp_mov imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x75+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_mov
+8.0xf7+8.0x75+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_mov
 "cmp_mov"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
 
@@ -6003,9 +6436,10 @@
 }
   
 // 1111 0111 1000 0101 imm4 Rn1 Rm2 Rn2; cmp_asr imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x85+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_asr
+8.0xf7+8.0x85+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_asr
 "cmp_asr"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
   signed int temp;
@@ -6022,9 +6456,10 @@
 }
 
 // 1111 0111 1001 0101 imm4 Rn1 imm4 Rn2; cmp_asr imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x95+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_asr
+8.0xf7+8.0x95+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_asr
 "cmp_asr"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
   signed int temp;
@@ -6040,9 +6475,10 @@
 }
   
 // 1111 0111 1010 0101 imm4 Rn1 Rm2 Rn2; cmp_lsr imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0xa5+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_lsr
+8.0xf7+8.0xa5+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_lsr
 "cmp_lsr"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
 
@@ -6056,12 +6492,12 @@
 }
 
 // 1111 0111 1011 0101 imm4 Rn1 imm4 Rn2; cmp_lsr imm4, Rn1, imm4, Rn2
-8.0xf7+8.0xb5+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_lsr
+8.0xf7+8.0xb5+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_lsr
 "cmp_lsr"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
-  signed int temp;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
@@ -6073,9 +6509,10 @@
   
   
 // 1111 0111 1100 0101 imm4 Rn1 Rm2 Rn2; cmp_asl imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0xc5+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::cmp_asl
+8.0xf7+8.0xc5+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_asl
 "cmp_asl"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
 
@@ -6089,12 +6526,12 @@
 }
 
 // 1111 0111 1101 0101 imm4 Rn1 imm4 Rn2; cmp_asl imm4, Rn1, imm4, Rn2
-8.0xf7+8.0xd5+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::cmp_asl
+8.0xf7+8.0xd5+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_asl
 "cmp_asl"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
-  signed int temp;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
@@ -6105,71 +6542,84 @@
 }
 
 // 1111 0111 0000 0110 imm4 Rn1 Rm2 Rn2; sub_add imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x06+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_add
+8.0xf7+8.0x06+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_add
 "sub_add"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg2 = translate_rreg (SD_, RM2);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
   State.regs[dstreg2] += State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0001 0110 imm4 Rn1 imm4 Rn2; sub_add imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x16+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_add
+8.0xf7+8.0x16+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_add
 "sub_add"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
   State.regs[dstreg2] += EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0010 0110 imm4 Rn1 Rm2 Rn2; sub_sub imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x26+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_sub
+8.0xf7+8.0x26+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_sub
 "sub_sub"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg2 = translate_rreg (SD_, RM2);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
   State.regs[dstreg2] -= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0011 0110 imm4 Rn1 imm4 Rn2; sub_sub imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x36+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_sub
+8.0xf7+8.0x36+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_sub
 "sub_sub"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
   State.regs[dstreg2] -= EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0100 0110 imm4 Rn1 Rm2 Rn2; sub_cmp imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x46+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_cmp
+8.0xf7+8.0x46+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_cmp
 "sub_cmp"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
 
@@ -6178,14 +6628,15 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= EXTEND4 (IMM4A);
   genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+  State.regs[dstreg1] -= EXTEND4 (IMM4A);
 }
 
 // 1111 0111 0101 0110 imm4 Rn1 imm4 Rn2; sub_cmp imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x56+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_cmp
+8.0xf7+8.0x56+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_cmp
 "sub_cmp"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
 
@@ -6193,47 +6644,55 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= EXTEND4 (IMM4A);
   genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+  State.regs[dstreg1] -= EXTEND4 (IMM4A);
 }
   
 // 1111 0111 0110 0110 imm4 Rn1 Rm2 Rn2; sub_mov imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x66+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_mov
+8.0xf7+8.0x66+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_mov
 "sub_mov"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg2 = translate_rreg (SD_, RM2);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
   State.regs[dstreg2] = State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0111 0110 imm4 Rn1 imm4 Rn2; sub_mov imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x76+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_mov
+8.0xf7+8.0x76+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_mov
 "sub_mov"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
   State.regs[dstreg2] = EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1000 0110 imm4 Rn1 Rm2 Rn2; sub_asr imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x86+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_asr
+8.0xf7+8.0x86+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_asr
 "sub_asr"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -6241,161 +6700,188 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
   temp = State.regs[dstreg2];
   temp >>= State.regs[srcreg2];
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1001 0110 imm4 Rn1 imm4 Rn2; sub_asr imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x96+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_asr
+8.0xf7+8.0x96+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_asr
 "sub_asr"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
   temp = State.regs[dstreg2];
   temp >>= IMM4;
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1010 0110 imm4 Rn1 Rm2 Rn2; sub_lsr imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0xa6+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_lsr
+8.0xf7+8.0xa6+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_lsr
 "sub_lsr"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg2 = translate_rreg (SD_, RM2);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
   State.regs[dstreg2] >>= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1011 0110 imm4 Rn1 imm4 Rn2; sub_lsr imm4, Rn1, imm4, Rn2
-8.0xf7+8.0xb6+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_lsr
+8.0xf7+8.0xb6+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_lsr
 "sub_lsr"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
-  signed int temp;
+  int result1;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
   State.regs[dstreg2] >>= IMM4;
+  State.regs[dstreg1] = result1;
 }
   
   
 // 1111 0111 1100 0110 imm4 Rn1 Rm2 Rn2; sub_asl imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0xc6+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::sub_asl
+8.0xf7+8.0xc6+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_asl
 "sub_asl"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg2 = translate_rreg (SD_, RM2);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
   State.regs[dstreg2] <<= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1101 0110 imm4 Rn1 imm4 Rn2; sub_asl imm4, Rn1, imm4, Rn2
-8.0xf7+8.0xd6+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::sub_asl
+8.0xf7+8.0xd6+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_asl
 "sub_asl"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
-  signed int temp;
+  int result1;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] -= EXTEND4 (IMM4A);
+  result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
   State.regs[dstreg2] <<= IMM4;
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0000 0111 imm4 Rn1 Rm2 Rn2; mov_add imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x07+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_add
+8.0xf7+8.0x07+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_add
 "mov_add"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg2 = translate_rreg (SD_, RM2);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = EXTEND4 (IMM4A);
+  result1 = EXTEND4 (IMM4A);
   State.regs[dstreg2] += State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0001 0111 imm4 Rn1 imm4 Rn2; mov_add imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x17+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_add
+8.0xf7+8.0x17+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_add
 "mov_add"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = EXTEND4 (IMM4A);
+  result1 = EXTEND4 (IMM4A);
   State.regs[dstreg2] += EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0010 0111 imm4 Rn1 Rm2 Rn2; mov_sub imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x27+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_sub
+8.0xf7+8.0x27+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_sub
 "mov_sub"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg2 = translate_rreg (SD_, RM2);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = EXTEND4 (IMM4A);
+  result1 = EXTEND4 (IMM4A);
   State.regs[dstreg2] -= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0011 0111 imm4 Rn1 imm4 Rn2; mov_sub imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x37+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_sub
+8.0xf7+8.0x37+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_sub
 "mov_sub"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = EXTEND4 (IMM4A);
+  result1 = EXTEND4 (IMM4A);
   State.regs[dstreg2] -= EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0100 0111 imm4 Rn1 Rm2 Rn2; mov_cmp imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x47+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_cmp
+8.0xf7+8.0x47+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_cmp
 "mov_cmp"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
 
@@ -6404,14 +6890,15 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = EXTEND4 (IMM4A);
   genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+  State.regs[dstreg1] = EXTEND4 (IMM4A);
 }
 
 // 1111 0111 0101 0111 imm4 Rn1 imm4 Rn2; mov_cmp imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x57+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_cmp
+8.0xf7+8.0x57+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_cmp
 "mov_cmp"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
 
@@ -6419,47 +6906,55 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = EXTEND4 (IMM4A);
   genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+  State.regs[dstreg1] = EXTEND4 (IMM4A);
 }
   
 // 1111 0111 0110 0111 imm4 Rn1 Rm2 Rn2; mov_mov imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x67+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_mov
+8.0xf7+8.0x67+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_mov
 "mov_mov"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg2 = translate_rreg (SD_, RM2);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = EXTEND4 (IMM4A);
+  result1 = EXTEND4 (IMM4A);
   State.regs[dstreg2] = State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0111 0111 imm4 Rn1 imm4 Rn2; mov_mov imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x77+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_mov
+8.0xf7+8.0x77+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_mov
 "mov_mov"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = EXTEND4 (IMM4A);
+  result1 = EXTEND4 (IMM4A);
   State.regs[dstreg2] = EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1000 0111 imm4 Rn1 Rm2 Rn2; mov_asr imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0x87+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_asr
+8.0xf7+8.0x87+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_asr
 "mov_asr"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -6467,101 +6962,117 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = EXTEND4 (IMM4A);
+  result1 = EXTEND4 (IMM4A);
   temp = State.regs[dstreg2];
   temp >>= State.regs[srcreg2];
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1001 0111 imm4 Rn1 imm4 Rn2; mov_asr imm4, Rn1, imm4, Rn2
-8.0xf7+8.0x97+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_asr
+8.0xf7+8.0x97+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_asr
 "mov_asr"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = EXTEND4 (IMM4A);
+  result1 = EXTEND4 (IMM4A);
   temp = State.regs[dstreg2];
   temp >>= IMM4;
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1010 0111 imm4 Rn1 Rm2 Rn2; mov_lsr imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0xa7+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_lsr
+8.0xf7+8.0xa7+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_lsr
 "mov_lsr"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg2 = translate_rreg (SD_, RM2);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = EXTEND4 (IMM4A);
+  result1 = EXTEND4 (IMM4A);
   State.regs[dstreg2] >>= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1011 0111 imm4 Rn1 imm4 Rn2; mov_lsr imm4, Rn1, imm4, Rn2
-8.0xf7+8.0xb7+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_lsr
+8.0xf7+8.0xb7+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_lsr
 "mov_lsr"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
-  signed int temp;
+  int result1;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = EXTEND4 (IMM4A);
+  result1 = EXTEND4 (IMM4A);
   State.regs[dstreg2] >>= IMM4;
+  State.regs[dstreg1] = result1;
 }
   
   
 // 1111 0111 1100 0111 imm4 Rn1 Rm2 Rn2; mov_asl imm4, Rn1, Rm2, Rn2
-8.0xf7+8.0xc7+4.IMM4A,4.RN1+4.RM2,4.RN2:D2c:::mov_asl
+8.0xf7+8.0xc7+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_asl
 "mov_asl"
 *am33
+*am33_2
 {
   int srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg2 = translate_rreg (SD_, RM2);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = EXTEND4 (IMM4A);
+  result1 = EXTEND4 (IMM4A);
   State.regs[dstreg2] <<= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1101 0111 imm4 Rn1 imm4 Rn2; mov_asl imm4, Rn1, imm4, Rn2
-8.0xf7+8.0xd7+4.IMM4A,4.RN1+4.IMM4,4.RN2:D2d:::mov_asl
+8.0xf7+8.0xd7+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_asl
 "mov_asl"
 *am33
+*am33_2
 {
   int dstreg1, dstreg2;
-  signed int temp;
+  int result1;
 
   PC = cia;
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = EXTEND4 (IMM4A);
+  result1 = EXTEND4 (IMM4A);
   State.regs[dstreg2] <<= IMM4;
+  State.regs[dstreg1] = result1;
 }
  
 // 1111 0111 0000 1000 Rm1 Rn1 Rm2 Rn2; and_add Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x08+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_add
+8.0xf7+8.0x08+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_add
 "and_add"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -6569,32 +7080,38 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] &= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] & State.regs[srcreg1];
   State.regs[dstreg2] += State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0001 1000 Rm1 Rn1 imm4 Rn2; and_add Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x18+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_add
+8.0xf7+8.0x18+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_add
 "and_add"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] &= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] & State.regs[srcreg1];
   State.regs[dstreg2] += EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0010 1000 Rm1 Rn1 Rm2 Rn2; and_sub Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x28+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_sub
+8.0xf7+8.0x28+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_sub
 "and_sub"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -6602,30 +7119,35 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] &= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] & State.regs[srcreg1];
   State.regs[dstreg2] -= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0011 1000 Rm1 Rn1 imm4 Rn2; and_sub Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x38+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_sub
+8.0xf7+8.0x38+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_sub
 "and_sub"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] &= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] & State.regs[srcreg1];
   State.regs[dstreg2] -= EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0100 1000 Rm1 Rn1 Rm2 Rn2; and_cmp Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x48+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_cmp
+8.0xf7+8.0x48+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_cmp
 "and_cmp"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
 
@@ -6635,14 +7157,15 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] &= State.regs[srcreg1];
   genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+  State.regs[dstreg1] &= State.regs[srcreg1];
 }
 
 // 1111 0111 0101 1000 Rm1 Rn1 imm4 Rn2; and_cmp Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x58+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_cmp
+8.0xf7+8.0x58+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_cmp
 "and_cmp"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
 
@@ -6651,16 +7174,18 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] &= State.regs[srcreg1];
   genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+  State.regs[dstreg1] &= State.regs[srcreg1];
 }
   
 // 1111 0111 0110 1000 Rm1 Rn1 Rm2 Rn2; and_mov Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x68+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_mov
+8.0xf7+8.0x68+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_mov
 "and_mov"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -6668,32 +7193,38 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] &= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] & State.regs[srcreg1];
   State.regs[dstreg2] = State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0111 1000 Rm1 Rn1 imm4 Rn2; and_mov Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x78+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_mov
+8.0xf7+8.0x78+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_mov
 "and_mov"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] &= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] & State.regs[srcreg1];
   State.regs[dstreg2] = EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1000 1000 Rm1 Rn1 Rm2 Rn2; and_asr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x88+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_asr
+8.0xf7+8.0x88+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_asr
 "and_asr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -6702,18 +7233,21 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] &= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] & State.regs[srcreg1];
   temp = State.regs[dstreg2];
   temp >>= State.regs[srcreg2];
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1001 1000 Rm1 Rn1 imm4 Rn2; and_asr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x98+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_asr
+8.0xf7+8.0x98+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_asr
 "and_asr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -6721,18 +7255,21 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] &= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] & State.regs[srcreg1];
   temp = State.regs[dstreg2];
   temp >>= IMM4;
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1010 1000 Rm1 Rn1 Rm2 Rn2; and_lsr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xa8+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_lsr
+8.0xf7+8.0xa8+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_lsr
 "and_lsr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -6740,34 +7277,39 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] &= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] & State.regs[srcreg1];
   State.regs[dstreg2] >>= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1011 1000 Rm1 Rn1 imm4 Rn2; and_lsr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xb8+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_lsr
+8.0xf7+8.0xb8+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_lsr
 "and_lsr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  signed int temp;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] &= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] & State.regs[srcreg1];
   State.regs[dstreg2] >>= IMM4;
+  State.regs[dstreg1] = result1;
 }
   
   
 // 1111 0111 1100 1000 Rm1 Rn1 Rm2 Rn2; and_asl Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xc8+4.RM1,4.RN1+4.RM2,4.RN2:D2:::and_asl
+8.0xf7+8.0xc8+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_asl
 "and_asl"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -6775,34 +7317,38 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] &= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] & State.regs[srcreg1];
   State.regs[dstreg2] <<= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1101 1000 Rm1 Rn1 imm4 Rn2; and_asl Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xd8+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::and_asl
+8.0xf7+8.0xd8+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_asl
 "and_asl"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  signed int temp;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] &= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] & State.regs[srcreg1];
   State.regs[dstreg2] <<= IMM4;
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0000 1001 Rm1 Rn1 Rm2 Rn2; dmach_add Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x09+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_add
+8.0xf7+8.0x09+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_add
 "dmach_add"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
-  long temp, temp2, sum;
+  signed32 temp, temp2, sum;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -6816,17 +7362,18 @@
            * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
-  State.regs[dstreg1] = sum;
   State.regs[dstreg2] += State.regs[srcreg2];
+  State.regs[dstreg1] = sum;
 }
 
 // 1111 0111 0001 1001 Rm1 Rn1 imm4 Rn2; dmach_add Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x19+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_add
+8.0xf7+8.0x19+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_add
 "dmach_add"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  long temp, temp2, sum;
+  signed32 temp, temp2, sum;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -6839,17 +7386,18 @@
            * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
-  State.regs[dstreg1] = sum;
   State.regs[dstreg2] += EXTEND4 (IMM4);
+  State.regs[dstreg1] = sum;
 }
   
 // 1111 0111 0010 1001 Rm1 Rn1 Rm2 Rn2; dmach_sub Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x29+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_sub
+8.0xf7+8.0x29+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_sub
 "dmach_sub"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
-  long temp, temp2, sum;
+  signed32 temp, temp2, sum;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -6863,17 +7411,18 @@
            * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
-  State.regs[dstreg1] = sum;
   State.regs[dstreg2] -= State.regs[srcreg2];
+  State.regs[dstreg1] = sum;
 }
 
 // 1111 0111 0011 1001 Rm1 Rn1 imm4 Rn2; dmach_sub Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x39+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_sub
+8.0xf7+8.0x39+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_sub
 "dmach_sub"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  long temp, temp2, sum;
+  signed32 temp, temp2, sum;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -6886,17 +7435,18 @@
            * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
-  State.regs[dstreg1] = sum;
   State.regs[dstreg2] -= EXTEND4 (IMM4);
+  State.regs[dstreg1] = sum;
 }
   
 // 1111 0111 0100 1001 Rm1 Rn1 Rm2 Rn2; dmach_cmp Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x49+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_cmp
+8.0xf7+8.0x49+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_cmp
 "dmach_cmp"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
-  long temp, temp2, sum;
+  signed32 temp, temp2, sum;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -6910,17 +7460,18 @@
            * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
-  State.regs[dstreg1] = sum;
   genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+  State.regs[dstreg1] = sum;
 }
 
 // 1111 0111 0101 1001 Rm1 Rn1 imm4 Rn2; dmach_cmp Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x59+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_cmp
+8.0xf7+8.0x59+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_cmp
 "dmach_cmp"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  long temp, temp2, sum;
+  signed32 temp, temp2, sum;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -6933,17 +7484,18 @@
            * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
-  State.regs[dstreg1] = sum;
   genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+  State.regs[dstreg1] = sum;
 }
   
 // 1111 0111 0110 1001 Rm1 Rn1 Rm2 Rn2; dmach_mov Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x69+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_mov
+8.0xf7+8.0x69+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_mov
 "dmach_mov"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
-  long temp, temp2, sum;
+  signed32 temp, temp2, sum;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -6957,17 +7509,18 @@
            * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
-  State.regs[dstreg1] = sum;
   State.regs[dstreg2] = State.regs[srcreg2];
+  State.regs[dstreg1] = sum;
 }
 
 // 1111 0111 0111 1001 Rm1 Rn1 imm4 Rn2; dmach_mov Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x79+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_mov
+8.0xf7+8.0x79+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_mov
 "dmach_mov"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  long temp, temp2, sum;
+  signed32 temp, temp2, sum;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -6980,17 +7533,18 @@
            * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
-  State.regs[dstreg1] = sum;
   State.regs[dstreg2] = EXTEND4 (IMM4);
+  State.regs[dstreg1] = sum;
 }
   
 // 1111 0111 1000 1001 Rm1 Rn1 Rm2 Rn2; dmach_asr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x89+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_asr
+8.0xf7+8.0x89+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_asr
 "dmach_asr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
-  long temp, temp2, sum;
+  signed32 temp, temp2, sum;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7004,19 +7558,20 @@
            * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
-  State.regs[dstreg1] = sum;
   temp = State.regs[dstreg2];
   temp >>= State.regs[srcreg2];
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = sum;
 }
 
 // 1111 0111 1001 1001 Rm1 Rn1 imm4 Rn2; dmach_asr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x99+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_asr
+8.0xf7+8.0x99+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_asr
 "dmach_asr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  long temp, temp2, sum;
+  signed32 temp, temp2, sum;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7029,19 +7584,20 @@
            * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
-  State.regs[dstreg1] = sum;
   temp = State.regs[dstreg2];
   temp >>= IMM4;
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = sum;
 }
   
 // 1111 0111 1010 1001 Rm1 Rn1 Rm2 Rn2; dmach_lsr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xa9+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_lsr
+8.0xf7+8.0xa9+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_lsr
 "dmach_lsr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
-  long temp, temp2, sum;
+  signed32 temp, temp2, sum;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7055,34 +7611,43 @@
            * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
-  State.regs[dstreg1] = sum;
   State.regs[dstreg2] >>= State.regs[srcreg2];
+  State.regs[dstreg1] = sum;
 }
 
 // 1111 0111 1011 1001 Rm1 Rn1 imm4 Rn2; dmach_lsr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xb9+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_lsr
+8.0xf7+8.0xb9+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_lsr
 "dmach_lsr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  long temp, temp2, sum;
+  signed32 temp, temp2, sum;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
+  temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
+          * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
+  temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
+           * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+  sum = temp + temp2 + State.regs[REG_MCRL];
+
   State.regs[dstreg2] >>= IMM4;
+  State.regs[dstreg1] = sum;
 }
   
   
 // 1111 0111 1100 1001 Rm1 Rn1 Rm2 Rn2; dmach_asl Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xc9+4.RM1,4.RN1+4.RM2,4.RN2:D2:::dmach_asl
+8.0xf7+8.0xc9+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_asl
 "dmach_asl"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
-  long temp, temp2, sum;
+  signed32 temp, temp2, sum;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7096,17 +7661,18 @@
            * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
-  State.regs[dstreg1] = sum;
   State.regs[dstreg2] <<= State.regs[srcreg2];
+  State.regs[dstreg1] = sum;
 }
 
 // 1111 0111 1101 1001 Rm1 Rn1 imm4 Rn2; dmach_asl Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xd9+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::dmach_asl
+8.0xf7+8.0xd9+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_asl
 "dmach_asl"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  long temp, temp2, sum;
+  signed32 temp, temp2, sum;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7119,16 +7685,18 @@
            * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
-  State.regs[dstreg1] = sum;
   State.regs[dstreg2] <<= IMM4;
+  State.regs[dstreg1] = sum;
 }
 
 // 1111 0111 0000 1010 Rm1 Rn1 Rm2 Rn2; xor_add Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x0a+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_add
+8.0xf7+8.0x0a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_add
 "xor_add"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7136,32 +7704,38 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] ^= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
   State.regs[dstreg2] += State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0001 1010 Rm1 Rn1 imm4 Rn2; xor_add Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x1a+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_add
+8.0xf7+8.0x1a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_add
 "xor_add"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] ^= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
   State.regs[dstreg2] += EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0010 1010 Rm1 Rn1 Rm2 Rn2; xor_sub Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x2a+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_sub
+8.0xf7+8.0x2a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_sub
 "xor_sub"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7169,30 +7743,35 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] ^= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
   State.regs[dstreg2] -= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0011 1010 Rm1 Rn1 imm4 Rn2; xor_sub Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x3a+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_sub
+8.0xf7+8.0x3a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_sub
 "xor_sub"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] ^= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
   State.regs[dstreg2] -= EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0100 1010 Rm1 Rn1 Rm2 Rn2; xor_cmp Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x4a+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_cmp
+8.0xf7+8.0x4a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_cmp
 "xor_cmp"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
 
@@ -7202,14 +7781,15 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] ^= State.regs[srcreg1];
   genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+  State.regs[dstreg1] ^= State.regs[srcreg1];
 }
 
 // 1111 0111 0101 1010 Rm1 Rn1 imm4 Rn2; xor_cmp Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x5a+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_cmp
+8.0xf7+8.0x5a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_cmp
 "xor_cmp"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
 
@@ -7218,16 +7798,18 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] ^= State.regs[srcreg1];
   genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+  State.regs[dstreg1] ^= State.regs[srcreg1];
 }
   
 // 1111 0111 0110 1010 Rm1 Rn1 Rm2 Rn2; xor_mov Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x6a+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_mov
+8.0xf7+8.0x6a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_mov
 "xor_mov"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7235,32 +7817,38 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] ^= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
   State.regs[dstreg2] = State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0111 1010 Rm1 Rn1 imm4 Rn2; xor_mov Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x7a+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_mov
+8.0xf7+8.0x7a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_mov
 "xor_mov"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] ^= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
   State.regs[dstreg2] = EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1000 1010 Rm1 Rn1 Rm2 Rn2; xor_asr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x8a+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_asr
+8.0xf7+8.0x8a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_asr
 "xor_asr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -7269,18 +7857,21 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] ^= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
   temp = State.regs[dstreg2];
   temp >>= State.regs[srcreg2];
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1001 1010 Rm1 Rn1 imm4 Rn2; xor_asr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x9a+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_asr
+8.0xf7+8.0x9a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_asr
 "xor_asr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -7288,18 +7879,21 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] ^= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
   temp = State.regs[dstreg2];
   temp >>= IMM4;
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1010 1010 Rm1 Rn1 Rm2 Rn2; xor_lsr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xaa+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_lsr
+8.0xf7+8.0xaa+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_lsr
 "xor_lsr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7307,34 +7901,39 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] ^= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
   State.regs[dstreg2] >>= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1011 1010 Rm1 Rn1 imm4 Rn2; xor_lsr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xba+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_lsr
+8.0xf7+8.0xba+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_lsr
 "xor_lsr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  signed int temp;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] ^= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
   State.regs[dstreg2] >>= IMM4;
+  State.regs[dstreg1] = result1;
 }
   
   
 // 1111 0111 1100 1010 Rm1 Rn1 Rm2 Rn2; xor_asl Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xca+4.RM1,4.RN1+4.RM2,4.RN2:D2:::xor_asl
+8.0xf7+8.0xca+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_asl
 "xor_asl"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7342,33 +7941,38 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] ^= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
   State.regs[dstreg2] <<= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1101 1010 Rm1 Rn1 imm4 Rn2; xor_asl Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xda+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::xor_asl
+8.0xf7+8.0xda+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_asl
 "xor_asl"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  signed int temp;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] ^= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
   State.regs[dstreg2] <<= IMM4;
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0000 1011 Rm1 Rn1 Rm2 Rn2; swhw_add Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x0b+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_add
+8.0xf7+8.0x0b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_add
 "swhw_add"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7376,33 +7980,39 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] ^= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
   State.regs[dstreg2] += State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0001 1011 Rm1 Rn1 imm4 Rn2; swhw_add Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x1b+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_add
+8.0xf7+8.0x1b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_add
 "swhw_add"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
-                         | ((State.regs[srcreg1] >> 16) & 0xffff));
+  result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+               | ((State.regs[srcreg1] >> 16) & 0xffff));
   State.regs[dstreg2] += EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0010 1011 Rm1 Rn1 Rm2 Rn2; swhw_sub Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x2b+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_sub
+8.0xf7+8.0x2b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_sub
 "swhw_sub"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7410,32 +8020,37 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
-                         | ((State.regs[srcreg1] >> 16) & 0xffff));
+  result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+               | ((State.regs[srcreg1] >> 16) & 0xffff));
   State.regs[dstreg2] -= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0011 1011 Rm1 Rn1 imm4 Rn2; swhw_sub Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x3b+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_sub
+8.0xf7+8.0x3b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_sub
 "swhw_sub"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
-                         | ((State.regs[srcreg1] >> 16) & 0xffff));
+  result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+               | ((State.regs[srcreg1] >> 16) & 0xffff));
   State.regs[dstreg2] -= EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0100 1011 Rm1 Rn1 Rm2 Rn2; swhw_cmp Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x4b+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_cmp
+8.0xf7+8.0x4b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_cmp
 "swhw_cmp"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
 
@@ -7445,15 +8060,16 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
+  genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
   State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
                          | ((State.regs[srcreg1] >> 16) & 0xffff));
-  genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
 }
 
 // 1111 0111 0101 1011 Rm1 Rn1 imm4 Rn2; swhw_cmp Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x5b+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_cmp
+8.0xf7+8.0x5b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_cmp
 "swhw_cmp"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
 
@@ -7462,17 +8078,19 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
+  genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
   State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
                          | ((State.regs[srcreg1] >> 16) & 0xffff));
-  genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
 }
   
 // 1111 0111 0110 1011 Rm1 Rn1 Rm2 Rn2; swhw_mov Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x6b+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_mov
+8.0xf7+8.0x6b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_mov
 "swhw_mov"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7480,34 +8098,40 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
-                         | ((State.regs[srcreg1] >> 16) & 0xffff));
+  result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+               | ((State.regs[srcreg1] >> 16) & 0xffff));
   State.regs[dstreg2] = State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0111 1011 Rm1 Rn1 imm4 Rn2; swhw_mov Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x7b+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_mov
+8.0xf7+8.0x7b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_mov
 "swhw_mov"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
-                         | ((State.regs[srcreg1] >> 16) & 0xffff));
+  result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+               | ((State.regs[srcreg1] >> 16) & 0xffff));
   State.regs[dstreg2] = EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1000 1011 Rm1 Rn1 Rm2 Rn2; swhw_asr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x8b+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_asr
+8.0xf7+8.0x8b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_asr
 "swhw_asr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -7516,19 +8140,22 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
-                         | ((State.regs[srcreg1] >> 16) & 0xffff));
+  result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+               | ((State.regs[srcreg1] >> 16) & 0xffff));
   temp = State.regs[dstreg2];
   temp >>= State.regs[srcreg2];
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1001 1011 Rm1 Rn1 imm4 Rn2; swhw_asr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x9b+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_asr
+8.0xf7+8.0x9b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_asr
 "swhw_asr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -7536,19 +8163,22 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
-                         | ((State.regs[srcreg1] >> 16) & 0xffff));
+  result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+               | ((State.regs[srcreg1] >> 16) & 0xffff));
   temp = State.regs[dstreg2];
   temp >>= IMM4;
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1010 1011 Rm1 Rn1 Rm2 Rn2; swhw_lsr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xab+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_lsr
+8.0xf7+8.0xab+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_lsr
 "swhw_lsr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7556,36 +8186,41 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
-                         | ((State.regs[srcreg1] >> 16) & 0xffff));
+  result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+               | ((State.regs[srcreg1] >> 16) & 0xffff));
   State.regs[dstreg2] >>= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1011 1011 Rm1 Rn1 imm4 Rn2; swhw_lsr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xbb+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_lsr
+8.0xf7+8.0xbb+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_lsr
 "swhw_lsr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  signed int temp;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
-                         | ((State.regs[srcreg1] >> 16) & 0xffff));
+  result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+               | ((State.regs[srcreg1] >> 16) & 0xffff));
   State.regs[dstreg2] >>= IMM4;
+  State.regs[dstreg1] = result1;
 }
   
   
 // 1111 0111 1100 1011 Rm1 Rn1 Rm2 Rn2; swhw_asl Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xcb+4.RM1,4.RN1+4.RM2,4.RN2:D2:::swhw_asl
+8.0xf7+8.0xcb+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_asl
 "swhw_asl"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7593,35 +8228,40 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
-                         | ((State.regs[srcreg1] >> 16) & 0xffff));
+  result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+               | ((State.regs[srcreg1] >> 16) & 0xffff));
   State.regs[dstreg2] <<= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1101 1011 Rm1 Rn1 imm4 Rn2; swhw_asl Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xdb+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::swhw_asl
+8.0xf7+8.0xdb+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_asl
 "swhw_asl"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  signed int temp;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
-                         | ((State.regs[srcreg1] >> 16) & 0xffff));
+  result1 = (((State.regs[srcreg1] & 0xffff) << 16)
+               | ((State.regs[srcreg1] >> 16) & 0xffff));
   State.regs[dstreg2] <<= IMM4;
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0000 1100 Rm1 Rn1 Rm2 Rn2; or_add Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x0c+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_add
+8.0xf7+8.0x0c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_add
 "or_add"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7629,32 +8269,38 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] |= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] | State.regs[srcreg1];
   State.regs[dstreg2] += State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0001 1100 Rm1 Rn1 imm4 Rn2; or_add Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x1c+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_add
+8.0xf7+8.0x1c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_add
 "or_add"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] |= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] | State.regs[srcreg1];
   State.regs[dstreg2] += EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0010 1100 Rm1 Rn1 Rm2 Rn2; or_sub Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x2c+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_sub
+8.0xf7+8.0x2c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_sub
 "or_sub"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7662,30 +8308,35 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] |= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] | State.regs[srcreg1];
   State.regs[dstreg2] -= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0011 1100 Rm1 Rn1 imm4 Rn2; or_sub Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x3c+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_sub
+8.0xf7+8.0x3c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_sub
 "or_sub"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] |= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] | State.regs[srcreg1];
   State.regs[dstreg2] -= EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0100 1100 Rm1 Rn1 Rm2 Rn2; or_cmp Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x4c+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_cmp
+8.0xf7+8.0x4c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_cmp
 "or_cmp"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
 
@@ -7695,14 +8346,15 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] |= State.regs[srcreg1];
   genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
+  State.regs[dstreg1] |= State.regs[srcreg1];
 }
 
 // 1111 0111 0101 1100 Rm1 Rn1 imm4 Rn2; or_cmp Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x5c+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_cmp
+8.0xf7+8.0x5c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_cmp
 "or_cmp"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
 
@@ -7711,16 +8363,18 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] |= State.regs[srcreg1];
   genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
+  State.regs[dstreg1] |= State.regs[srcreg1];
 }
   
 // 1111 0111 0110 1100 Rm1 Rn1 Rm2 Rn2; or_mov Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x6c+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_mov
+8.0xf7+8.0x6c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_mov
 "or_mov"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7728,32 +8382,38 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] |= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] | State.regs[srcreg1];
   State.regs[dstreg2] = State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0111 1100 Rm1 Rn1 imm4 Rn2; or_mov Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x7c+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_mov
+8.0xf7+8.0x7c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_mov
 "or_mov"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] |= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] | State.regs[srcreg1];
   State.regs[dstreg2] = EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1000 1100 Rm1 Rn1 Rm2 Rn2; or_asr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x8c+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_asr
+8.0xf7+8.0x8c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_asr
 "or_asr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -7762,18 +8422,21 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] |= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] | State.regs[srcreg1];
   temp = State.regs[dstreg2];
   temp >>= State.regs[srcreg2];
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1001 1100 Rm1 Rn1 imm4 Rn2; or_asr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x9c+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_asr
+8.0xf7+8.0x9c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_asr
 "or_asr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -7781,18 +8444,21 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] |= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] | State.regs[srcreg1];
   temp = State.regs[dstreg2];
   temp >>= IMM4;
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1010 1100 Rm1 Rn1 Rm2 Rn2; or_lsr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xac+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_lsr
+8.0xf7+8.0xac+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_lsr
 "or_lsr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7800,34 +8466,39 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] |= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] | State.regs[srcreg1];
   State.regs[dstreg2] >>= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1011 1100 Rm1 Rn1 imm4 Rn2; or_lsr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xbc+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_lsr
+8.0xf7+8.0xbc+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_lsr
 "or_lsr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  signed int temp;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] |= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] | State.regs[srcreg1];
   State.regs[dstreg2] >>= IMM4;
+  State.regs[dstreg1] = result1;
 }
   
   
 // 1111 0111 1100 1100 Rm1 Rn1 Rm2 Rn2; or_asl Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xcc+4.RM1,4.RN1+4.RM2,4.RN2:D2:::or_asl
+8.0xf7+8.0xcc+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_asl
 "or_asl"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7835,33 +8506,38 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] |= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] | State.regs[srcreg1];
   State.regs[dstreg2] <<= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1101 1100 Rm1 Rn1 imm4 Rn2; or_asl Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xdc+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::or_asl
+8.0xf7+8.0xdc+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_asl
 "or_asl"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  signed int temp;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  State.regs[dstreg1] |= State.regs[srcreg1];
+  result1 = State.regs[dstreg1] | State.regs[srcreg1];
   State.regs[dstreg2] <<= IMM4;
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0000 1101 Rm1 Rn1 Rm2 Rn2; sat16_add Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x0d+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_add
+8.0xf7+8.0x0d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_add
 "sat16_add"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7870,21 +8546,24 @@
   dstreg2 = translate_rreg (SD_, RN2);
 
   if (State.regs[srcreg1] >= 0x7fff)
-    State.regs[dstreg1] = 0x7fff;
+    result1 = 0x7fff;
   else if (State.regs[srcreg1] <= 0xffff8000)
-    State.regs[dstreg1] = 0xffff8000;
+    result1 = 0xffff8000;
   else
-    State.regs[dstreg1] = State.regs[srcreg1];
+    result1 = State.regs[srcreg1];
 
   State.regs[dstreg2] += State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0001 1101 Rm1 Rn1 imm4 Rn2; sat16_add Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x1d+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_add
+8.0xf7+8.0x1d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_add
 "sat16_add"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7892,21 +8571,24 @@
   dstreg2 = translate_rreg (SD_, RN2);
 
   if (State.regs[srcreg1] >= 0x7fff)
-    State.regs[dstreg1] = 0x7fff;
+    result1 = 0x7fff;
   else if (State.regs[srcreg1] <= 0xffff8000)
-    State.regs[dstreg1] = 0xffff8000;
+    result1 = 0xffff8000;
   else
-    State.regs[dstreg1] = State.regs[srcreg1];
+    result1 = State.regs[srcreg1];
 
   State.regs[dstreg2] += EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0010 1101 Rm1 Rn1 Rm2 Rn2; sat16_sub Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x2d+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_sub
+8.0xf7+8.0x2d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_sub
 "sat16_sub"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7915,21 +8597,24 @@
   dstreg2 = translate_rreg (SD_, RN2);
 
   if (State.regs[srcreg1] >= 0x7fff)
-    State.regs[dstreg1] = 0x7fff;
+    result1 = 0x7fff;
   else if (State.regs[srcreg1] <= 0xffff8000)
-    State.regs[dstreg1] = 0xffff8000;
+    result1 = 0xffff8000;
   else
-    State.regs[dstreg1] = State.regs[srcreg1];
+    result1 = State.regs[srcreg1];
 
   State.regs[dstreg2] -= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0011 1101 Rm1 Rn1 imm4 Rn2; sat16_sub Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x3d+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_sub
+8.0xf7+8.0x3d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_sub
 "sat16_sub"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7937,19 +8622,21 @@
   dstreg2 = translate_rreg (SD_, RN2);
 
   if (State.regs[srcreg1] >= 0x7fff)
-    State.regs[dstreg1] = 0x7fff;
+    result1 = 0x7fff;
   else if (State.regs[srcreg1] <= 0xffff8000)
-    State.regs[dstreg1] = 0xffff8000;
+    result1 = 0xffff8000;
   else
-    State.regs[dstreg1] = State.regs[srcreg1];
+    result1 = State.regs[srcreg1];
 
   State.regs[dstreg2] -= EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 0100 1101 Rm1 Rn1 Rm2 Rn2; sat16_cmp Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x4d+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_cmp
+8.0xf7+8.0x4d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_cmp
 "sat16_cmp"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
 
@@ -7959,20 +8646,20 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
+  genericCmp (State.regs[dstreg2], State.regs[dstreg1]);
   if (State.regs[srcreg1] >= 0x7fff)
     State.regs[dstreg1] = 0x7fff;
   else if (State.regs[srcreg1] <= 0xffff8000)
     State.regs[dstreg1] = 0xffff8000;
   else
     State.regs[dstreg1] = State.regs[srcreg1];
-
-  genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
 }
 
 // 1111 0111 0101 1101 Rm1 Rn1 imm4 Rn2; sat16_cmp Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x5d+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_cmp
+8.0xf7+8.0x5d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_cmp
 "sat16_cmp"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
 
@@ -7981,22 +8668,23 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
+  genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
   if (State.regs[srcreg1] >= 0x7fff)
     State.regs[dstreg1] = 0x7fff;
   else if (State.regs[srcreg1] <= 0xffff8000)
     State.regs[dstreg1] = 0xffff8000;
   else
     State.regs[dstreg1] = State.regs[srcreg1];
-
-  genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
 }
   
 // 1111 0111 0110 1101 Rm1 Rn1 Rm2 Rn2; sat16_mov Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x6d+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_mov
+8.0xf7+8.0x6d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_mov
 "sat16_mov"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -8005,21 +8693,24 @@
   dstreg2 = translate_rreg (SD_, RN2);
 
   if (State.regs[srcreg1] >= 0x7fff)
-    State.regs[dstreg1] = 0x7fff;
+    result1 = 0x7fff;
   else if (State.regs[srcreg1] <= 0xffff8000)
-    State.regs[dstreg1] = 0xffff8000;
+    result1 = 0xffff8000;
   else
-    State.regs[dstreg1] = State.regs[srcreg1];
+    result1 = State.regs[srcreg1];
 
   State.regs[dstreg2] = State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 0111 1101 Rm1 Rn1 imm4 Rn2; sat16_mov Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x7d+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_mov
+8.0xf7+8.0x7d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_mov
 "sat16_mov"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -8027,21 +8718,24 @@
   dstreg2 = translate_rreg (SD_, RN2);
 
   if (State.regs[srcreg1] >= 0x7fff)
-    State.regs[dstreg1] = 0x7fff;
+    result1 = 0x7fff;
   else if (State.regs[srcreg1] <= 0xffff8000)
-    State.regs[dstreg1] = 0xffff8000;
+    result1 = 0xffff8000;
   else
-    State.regs[dstreg1] = State.regs[srcreg1];
+    result1 = State.regs[srcreg1];
 
   State.regs[dstreg2] = EXTEND4 (IMM4);
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1000 1101 Rm1 Rn1 Rm2 Rn2; sat16_asr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0x8d+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_asr
+8.0xf7+8.0x8d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_asr
 "sat16_asr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -8051,23 +8745,26 @@
   dstreg2 = translate_rreg (SD_, RN2);
 
   if (State.regs[srcreg1] >= 0x7fff)
-    State.regs[dstreg1] = 0x7fff;
+    result1 = 0x7fff;
   else if (State.regs[srcreg1] <= 0xffff8000)
-    State.regs[dstreg1] = 0xffff8000;
+    result1 = 0xffff8000;
   else
-    State.regs[dstreg1] = State.regs[srcreg1];
+    result1 = State.regs[srcreg1];
 
   temp = State.regs[dstreg2];
   temp >>= State.regs[srcreg2];
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1001 1101 Rm1 Rn1 imm4 Rn2; sat16_asr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0x9d+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_asr
+8.0xf7+8.0x9d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_asr
 "sat16_asr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
+  int result1;
   signed int temp;
 
   PC = cia;
@@ -8076,23 +8773,26 @@
   dstreg2 = translate_rreg (SD_, RN2);
 
   if (State.regs[srcreg1] >= 0x7fff)
-    State.regs[dstreg1] = 0x7fff;
+    result1 = 0x7fff;
   else if (State.regs[srcreg1] <= 0xffff8000)
-    State.regs[dstreg1] = 0xffff8000;
+    result1 = 0xffff8000;
   else
-    State.regs[dstreg1] = State.regs[srcreg1];
+    result1 = State.regs[srcreg1];
 
   temp = State.regs[dstreg2];
   temp >>= IMM4;
   State.regs[dstreg2] = temp;
+  State.regs[dstreg1] = result1;
 }
   
 // 1111 0111 1010 1101 Rm1 Rn1 Rm2 Rn2; sat16_lsr Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xad+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_lsr
+8.0xf7+8.0xad+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_lsr
 "sat16_lsr"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -8101,22 +8801,24 @@
   dstreg2 = translate_rreg (SD_, RN2);
 
   if (State.regs[srcreg1] >= 0x7fff)
-    State.regs[dstreg1] = 0x7fff;
+    result1 = 0x7fff;
   else if (State.regs[srcreg1] <= 0xffff8000)
-    State.regs[dstreg1] = 0xffff8000;
+    result1 = 0xffff8000;
   else
-    State.regs[dstreg1] = State.regs[srcreg1];
+    result1 = State.regs[srcreg1];
 
   State.regs[dstreg2] >>= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1011 1101 Rm1 Rn1 imm4 Rn2; sat16_lsr Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xbd+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_lsr
+8.0xf7+8.0xbd+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_lsr
 "sat16_lsr"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  signed int temp;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -8124,22 +8826,25 @@
   dstreg2 = translate_rreg (SD_, RN2);
 
   if (State.regs[srcreg1] >= 0x7fff)
-    State.regs[dstreg1] = 0x7fff;
+    result1 = 0x7fff;
   else if (State.regs[srcreg1] <= 0xffff8000)
-    State.regs[dstreg1] = 0xffff8000;
+    result1 = 0xffff8000;
   else
-    State.regs[dstreg1] = State.regs[srcreg1];
+    result1 = State.regs[srcreg1];
 
   State.regs[dstreg2] >>= IMM4;
+  State.regs[dstreg1] = result1;
 }
   
   
 // 1111 0111 1100 1101 Rm1 Rn1 Rm2 Rn2; sat16_asl Rm1, Rn1, Rm2, Rn2
-8.0xf7+8.0xcd+4.RM1,4.RN1+4.RM2,4.RN2:D2:::sat16_asl
+8.0xf7+8.0xcd+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_asl
 "sat16_asl"
 *am33
+*am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -8148,22 +8853,24 @@
   dstreg2 = translate_rreg (SD_, RN2);
 
   if (State.regs[srcreg1] >= 0x7fff)
-    State.regs[dstreg1] = 0x7fff;
+    result1 = 0x7fff;
   else if (State.regs[srcreg1] <= 0xffff8000)
-    State.regs[dstreg1] = 0xffff8000;
+    result1 = 0xffff8000;
   else
-    State.regs[dstreg1] = State.regs[srcreg1];
+    result1 = State.regs[srcreg1];
 
   State.regs[dstreg2] <<= State.regs[srcreg2];
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1101 1101 Rm1 Rn1 imm4 Rn2; sat16_asl Rm1, Rn1, imm4, Rn2
-8.0xf7+8.0xdd+4.RM1,4.RN1+4.IMM4,4.RN2:D2b:::sat16_asl
+8.0xf7+8.0xdd+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_asl
 "sat16_asl"
 *am33
+*am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  signed int temp;
+  int result1;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -8171,19 +8878,21 @@
   dstreg2 = translate_rreg (SD_, RN2);
 
   if (State.regs[srcreg1] >= 0x7fff)
-    State.regs[dstreg1] = 0x7fff;
+    result1 = 0x7fff;
   else if (State.regs[srcreg1] <= 0xffff8000)
-    State.regs[dstreg1] = 0xffff8000;
+    result1 = 0xffff8000;
   else
-    State.regs[dstreg1] = State.regs[srcreg1];
+    result1 = State.regs[srcreg1];
 
   State.regs[dstreg2] <<= IMM4;
+  State.regs[dstreg1] = result1;
 }
 
 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0000; mov_llt (Rm+,imm4),Rn
-8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x0:D2:::mov_llt
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x0:D2:::mov_llt
 "mov_llt"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -8202,9 +8911,10 @@
 }
 
 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0001; mov_lgt (Rm+,imm4),Rn
-8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x1:D2:::mov_lgt
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x1:D2:::mov_lgt
 "mov_lgt"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -8224,9 +8934,10 @@
 }
 
 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0010; mov_lge (Rm+,imm4),Rn
-8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x2:D2:::mov_lge
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x2:D2:::mov_lge
 "mov_lge"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -8245,9 +8956,10 @@
 }
 
 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0011; mov_lle (Rm+,imm4),Rn
-8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x3:D2:::mov_lle
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x3:D2:::mov_lle
 "mov_lle"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -8267,9 +8979,10 @@
 }
 
 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0100; mov_lcs (Rm+,imm4),Rn
-8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x4:D2:::mov_lcs
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x4:D2:::mov_lcs
 "mov_lcs"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -8288,9 +9001,10 @@
 }
 
 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0101; mov_lhi (Rm+,imm4),Rn
-8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x5:D2:::mov_lhi
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x5:D2:::mov_lhi
 "mov_lhi"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -8309,9 +9023,10 @@
 }
 
 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0110; mov_lcc (Rm+,imm4),Rn
-8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x6:D2:::mov_lcc
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x6:D2:::mov_lcc
 "mov_lcc"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -8330,9 +9045,10 @@
 }
 
 // 1111 0111 1110 0000 Rm1 Rn1 imm4 0111; mov_lls (Rm+,imm4),Rn
-8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x7:D2:::mov_lls
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x7:D2:::mov_lls
 "mov_lls"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -8351,9 +9067,10 @@
 }
 
 // 1111 0111 1110 0000 Rm1 Rn1 imm4 1000; mov_leq (Rm+,imm4),Rn
-8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x8:D2:::mov_leq
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x8:D2:::mov_leq
 "mov_leq"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -8372,9 +9089,10 @@
 }
 
 // 1111 0111 1110 0000 Rm1 Rn1 imm4 1001; mov_lne (Rm+,imm4),Rn
-8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0x9:D2:::mov_lne
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x9:D2:::mov_lne
 "mov_lne"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -8393,9 +9111,10 @@
 }
 
 // 1111 0111 1110 0000 Rm1 Rn1 imm4 1010; mov_lra (Rm+,imm4),Rn
-8.0xf7+8.0xe0+4.RN,4.RM+4.IMM4,4.0xa:D2:::mov_lra
+8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0xa:D2:::mov_lra
 "mov_lra"
 *am33
+*am33_2
 {
   int srcreg, dstreg;
 
@@ -8409,3 +9128,5 @@
   State.regs[REG_PC] = State.regs[REG_LAR] - 4;
   nia = PC;
 }
+
+:include::am33_2:am33-2.igen