sim: replace CIA_{GET,SET} with CPU_PC_{GET,SET}

[deliverable/binutils-gdb.git] / sim / mn10300 / dv-mn103cpu.c

diff --git a/sim/mn10300/dv-mn103cpu.c b/sim/mn10300/dv-mn103cpu.c
index e5540eeafebb1a52533b5505eb41c19f4ff7e73b..e9dd2f65191d8c77c57ec66ede8331b556a0a3af 100644 (file)
--- a/sim/mn10300/dv-mn103cpu.c
+++ b/sim/mn10300/dv-mn103cpu.c
@@ -227,31 +227,31 @@ deliver_mn103cpu_interrupt (struct hw *me,
   else if (controller->pending_nmi)
     {
       controller->pending_nmi = 0;
-      store_word (SP - 4, CIA_GET (cpu));
+      store_word (SP - 4, CPU_PC_GET (cpu));
       store_half (SP - 8, PSW);
       PSW &= ~PSW_IE;
       SP = SP - 8;
-      CIA_SET (cpu, 0x40000008);
+      CPU_PC_SET (cpu, 0x40000008);
       HW_TRACE ((me, "nmi pc=0x%08lx psw=0x%04x sp=0x%08lx",
-                (long) CIA_GET (cpu), (unsigned) PSW, (long) SP));
+                (long) CPU_PC_GET (cpu), (unsigned) PSW, (long) SP));
     }
   else if ((controller->pending_level < EXTRACT_PSW_LM)
           && (PSW & PSW_IE))
     {
       /* Don't clear pending level.  Request continues to be pending
          until the interrupt controller clears/changes it */
-      store_word (SP - 4, CIA_GET (cpu));
+      store_word (SP - 4, CPU_PC_GET (cpu));
       store_half (SP - 8, PSW);
       PSW &= ~PSW_IE;
       PSW &= ~PSW_LM;
       PSW |= INSERT_PSW_LM (controller->pending_level);
       SP = SP - 8;
-      CIA_SET (cpu, 0x40000000 + controller->interrupt_vector[controller->pending_level]);
+      CPU_PC_SET (cpu, 0x40000000 + controller->interrupt_vector[controller->pending_level]);
       HW_TRACE ((me, "port-out ack %d", controller->pending_level));
       hw_port_event (me, ACK_PORT, controller->pending_level);
       HW_TRACE ((me, "int level=%d pc=0x%08lx psw=0x%04x sp=0x%08lx",
                 controller->pending_level,
-                (long) CIA_GET (cpu), (unsigned) PSW, (long) SP));
+                (long) CPU_PC_GET (cpu), (unsigned) PSW, (long) SP));
     }
 
   if (controller->pending_level < 7) /* FIXME */