Fix sim breakage

[deliverable/binutils-gdb.git] / sim / moxie / interp.c

diff --git a/sim/moxie/interp.c b/sim/moxie/interp.c
index 9c98021a59235eb466508f7b42868ef8dd10b869..a3f238a00669b2e93ce071a6da976a04459d694a 100644 (file)
--- a/sim/moxie/interp.c
+++ b/sim/moxie/interp.c
@@ -1,5 +1,5 @@
 /* Simulator for the moxie processor
-   Copyright (C) 2008-2012 Free Software Foundation, Inc.
+   Copyright (C) 2008-2014 Free Software Foundation, Inc.
    Contributed by Anthony Green
 
 This file is part of GDB, the GNU debugger.
@@ -17,6 +17,8 @@ GNU General Public License for more details.
 You should have received a copy of the GNU General Public License
 along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
 
+#include "config.h"
+#include <fcntl.h>
 #include <signal.h>
 #include <stdlib.h>
 #include "sysdep.h"
@@ -155,12 +157,6 @@ set_initial_gprs ()
     cpu.asregs.sregs[i] = 0;
 }
 
-static void
-interrupt ()
-{
-  cpu.asregs.exception = SIGINT;
-}
-
 /* Write a 1 byte value to memory.  */
 
 static void INLINE 
@@ -256,11 +252,9 @@ sim_resume (sd, step, siggnal)
   word pc, opc;
   unsigned long long insts;
   unsigned short inst;
-  void (* sigsave)();
   sim_cpu *scpu = STATE_CPU (sd, 0); /* FIXME */
   address_word cia = CIA_GET (scpu);
 
-  sigsave = signal (SIGINT, interrupt);
   cpu.asregs.exception = step ? SIGTRAP: 0;
   pc = cpu.asregs.regs[PC_REGNO];
   insts = cpu.asregs.insts;
@@ -288,69 +282,69 @@ sim_resume (sd, step, siggnal)
                  {
                    TRACE("beq");
                    if (cpu.asregs.cc & CC_EQ)
-                     pc += INST2OFFSET(inst) - 2;
+                     pc += INST2OFFSET(inst);
                  }
                  break;
                case 0x01: /* bne */
                  {
                    TRACE("bne");
                    if (! (cpu.asregs.cc & CC_EQ))
-                     pc += INST2OFFSET(inst) - 2;
+                     pc += INST2OFFSET(inst);
                  }
                  break;
                case 0x02: /* blt */
                  {
                    TRACE("blt");
                    if (cpu.asregs.cc & CC_LT)
-                     pc += INST2OFFSET(inst) - 2;
+                     pc += INST2OFFSET(inst);
                  }               break;
                case 0x03: /* bgt */
                  {
                    TRACE("bgt");
                    if (cpu.asregs.cc & CC_GT)
-                     pc += INST2OFFSET(inst) - 2;
+                     pc += INST2OFFSET(inst);
                  }
                  break;
                case 0x04: /* bltu */
                  {
                    TRACE("bltu");
                    if (cpu.asregs.cc & CC_LTU)
-                     pc += INST2OFFSET(inst) - 2;
+                     pc += INST2OFFSET(inst);
                  }
                  break;
                case 0x05: /* bgtu */
                  {
                    TRACE("bgtu");
                    if (cpu.asregs.cc & CC_GTU)
-                     pc += INST2OFFSET(inst) - 2;
+                     pc += INST2OFFSET(inst);
                  }
                  break;
                case 0x06: /* bge */
                  {
                    TRACE("bge");
                    if (cpu.asregs.cc & (CC_GT | CC_EQ))
-                     pc += INST2OFFSET(inst) - 2;
+                     pc += INST2OFFSET(inst);
                  }
                  break;
                case 0x07: /* ble */
                  {
                    TRACE("ble");
                    if (cpu.asregs.cc & (CC_LT | CC_EQ))
-                     pc += INST2OFFSET(inst) - 2;
+                     pc += INST2OFFSET(inst);
                  }
                  break;
                case 0x08: /* bgeu */
                  {
                    TRACE("bgeu");
                    if (cpu.asregs.cc & (CC_GTU | CC_EQ))
-                     pc += INST2OFFSET(inst) - 2;
+                     pc += INST2OFFSET(inst);
                  }
                  break;
                case 0x09: /* bleu */
                  {
                    TRACE("bleu");
                    if (cpu.asregs.cc & (CC_LTU | CC_EQ))
-                     pc += INST2OFFSET(inst) - 2;
+                     pc += INST2OFFSET(inst);
                  }
                  break;
                default:
@@ -1020,8 +1014,6 @@ sim_resume (sd, step, siggnal)
   /* Hide away the things we've cached while executing.  */
   cpu.asregs.regs[PC_REGNO] = pc;
   cpu.asregs.insts += insts;           /* instructions done ... */
-
-  signal (SIGINT, sigsave);
 }
 
 int
@@ -1163,7 +1155,6 @@ sim_open (kind, cb, abfd, argv)
      char ** argv;
 {
   SIM_DESC sd = sim_state_alloc (kind, cb);
-  printf ("0x%x 0x%x\n", sd, STATE_MAGIC(sd));
   SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
 
   if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
@@ -1239,7 +1230,7 @@ load_dtb (SIM_DESC sd, const char *filename)
 SIM_RC
 sim_load (sd, prog, abfd, from_tty)
      SIM_DESC sd;
-     char * prog;
+     const char * prog;
      bfd * abfd;
      int from_tty;
 {
@@ -1359,7 +1350,7 @@ sim_kill (sd)
 void
 sim_do_command (sd, cmd)
      SIM_DESC sd;
-     char * cmd;
+     const char *cmd;
 {
   if (sim_args_command (sd, cmd) != SIM_RC_OK)
     sim_io_printf (sd,