UPDATING PSIM:
-A PSIM is an ongoing development. Occasional snapshots which both contain new features and fix old bugs are made available. See the ftp directory:
+A PSIM is an ongoing development. Occasional snapshots which both contain new
+features and fix old bugs are made available. See the ftp directory:
ftp://ftp.ci.com.au/pub/psim/beta
or ftp://cambridge.cygnus.com/pub/psim/beta
---enable-sim-cflags=<opts>
-
-
-Specify additional C compiler flags that are to be used when compiling
-just PSIM.
-
-PSIM places heavy demands on both the host machine and its C compiler.
-So that the builder has better control over the compiler the above
-option can be used to pass additional options to the compiler while PSIM is being built.
-
-Ex: No debug information
-
-PSIM can be built with everything inline. Unfortunately, because of
-all the debugging information generated the C compiler can grow very
-very large as a result. For GCC, the debug information can be
-restricted with the `-g0' option. To specify that this option should
-be include in the CFLAGS when compiling the psim source code use:
-
- --enable-sim-cflags=-g0
-
-Ex: Additional optimization flags
-
-A significant gain in performance can be achieved by tuning the
-optimization flags passed to the C compiler. For instance on an x86
-you may consider:
-
- --enable-sim-cflags='-g0 -O2 -fno-strength-reduce -f...'
-
-
-
--enable-sim-warnings=<flags>
---enable-sim-bswap
-
-
-(x86 specific) Use the i486/P5/P6 byte swap instruction.
-
-PSIM contains generic byte swapping code. For the x86 (P[4-6]) PSIM
-can be built so that it uses the bswap instruction instead of relying
-on the compiler to generate byte swap code.
-
-Ex: default
-
-By default, when compiling with GCC-2 on an i486/P5/P6 the bswap
-instruction is used.
-
-
-
--enable-sim-endian=endian
Ex: recommended
-Unless you intend studying multi-processor systems there is little reason for having PSIM configured with SMP support. Specifying:
+Unless you intend studying multi-processor systems there is little reason for
+having PSIM configured with SMP support. Specifying:
--disable-sim-smp
or --enable-sim-smp=0
Hardwire the PowerPC environment being modelled (user, virtual or
operating).
-The PowerPC architecture defines three different levels of compliance
-to its architectural specification. These environments are discussed in detail in PowerPC publications.
+The PowerPC architecture defines three different levels of compliance to its
+architectural specification. These environments are discussed in detail in
+PowerPC publications.
user - normal user programs
virtual - an extension of the user environment (includes timers)
--enable-sim-warnings \
--enable-sim-inline \
--disable-sim-smp \
- --enable-sim-bswap \
--enable-sim-duplicate \
--enable-sim-endian=big \
--disable-sim-xor-endian \
--enable-sim-env=user \
--disable-sim-reserved-bits \
--disable-sim-assert \
- --disable-sim-trace \
- --enable-sim-cflags='-g0 -O2 -fno-strength-reduce -fomit-frame-pointer -malign-loops=2 -malign-jumps=2 -malign-functions=2'
+ --disable-sim-trace
OEA CODE ONLY:
--enable-sim-powerpc \
--enable-sim-inline \
--disable-sim-smp \
- --enable-sim-bswap \
--enable-sim-duplicate \
--enable-sim-endian=big \
--disable-sim-xor-endian \
--disable-sim-assert \
--disable-sim-trace \
--enable-sim-opcode=ppc-opcode-flat \
- --disable-sim-icache \
- --enable-sim-cflags='-g0 -O3 -fno-strength-reduce -fomit-frame-pointer -malign-loops=2 -malign-jumps=2 -malign-functions=2'
+ --disable-sim-icache