xcoff slurp_armap bounds checking

[deliverable/binutils-gdb.git] / sim / ppc / interrupts.h

diff --git a/sim/ppc/interrupts.h b/sim/ppc/interrupts.h
index 7e03d38019c0ada4ca4c9a66ff97f1473679168e..717112933098b9e016e63d0f7c0274dfab92538a 100644 (file)
--- a/sim/ppc/interrupts.h
+++ b/sim/ppc/interrupts.h
@@ -4,7 +4,7 @@
 
     This program is free software; you can redistribute it and/or modify
     it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 2 of the License, or
+    the Free Software Foundation; either version 3 of the License, or
     (at your option) any later version.
 
     This program is distributed in the hope that it will be useful,
@@ -13,8 +13,7 @@
     GNU General Public License for more details.
  
     You should have received a copy of the GNU General Public License
-    along with this program; if not, write to the Free Software
-    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+    along with this program; if not, see <http://www.gnu.org/licenses/>.
  
     */
 
@@ -68,19 +67,22 @@ typedef enum {
 } storage_interrupt_reasons;
 
 
-void INLINE_INTERRUPTS data_storage_interrupt
+INLINE_INTERRUPTS\
+(void) data_storage_interrupt
 (cpu *processor,
  unsigned_word cia,
  unsigned_word ea,
  storage_interrupt_reasons reason,
  int is_store);
 
-void INLINE_INTERRUPTS instruction_storage_interrupt
+INLINE_INTERRUPTS\
+(void) instruction_storage_interrupt
 (cpu *processor,
  unsigned_word cia,
  storage_interrupt_reasons reason);
 
-void INLINE_INTERRUPTS alignment_interrupt
+INLINE_INTERRUPTS\
+(void) alignment_interrupt
 (cpu *processor,
  unsigned_word cia,
  unsigned_word ra);
@@ -90,63 +92,78 @@ typedef enum {
   illegal_instruction_program_interrupt,
   privileged_instruction_program_interrupt,
   trap_program_interrupt,
+  optional_instruction_program_interrupt, /* subset of illegal instruction */
+  mpc860c0_instruction_program_interrupt, /* fwd br, taken but not predicted, near EO page */
   nr_program_interrupt_reasons
 } program_interrupt_reasons;
 
-void INLINE_INTERRUPTS program_interrupt
+INLINE_INTERRUPTS\
+(void) program_interrupt
 (cpu *processor,
  unsigned_word cia,
  program_interrupt_reasons reason);
 
-void INLINE_INTERRUPTS floating_point_unavailable_interrupt
+INLINE_INTERRUPTS\
+(void) floating_point_unavailable_interrupt
 (cpu *processor,
  unsigned_word cia);
 
-void INLINE_INTERRUPTS system_call_interrupt
+INLINE_INTERRUPTS\
+(void) system_call_interrupt
 (cpu *processor,
  unsigned_word cia);
 
-void INLINE_INTERRUPTS trace_interrupt
+INLINE_INTERRUPTS\
+(void) floating_point_assist_interrupt
 (cpu *processor,
  unsigned_word cia);
 
-void INLINE_INTERRUPTS floating_point_assist_interrupt
+INLINE_INTERRUPTS\
+(void) machine_check_interrupt
 (cpu *processor,
  unsigned_word cia);
 
-void INLINE_INTERRUPTS machine_check_interrupt
-(cpu *processor,
- unsigned_word cia);
-
-/* Bit of a funny one.  One of the trap instructions has been marked
-   as the breakpoint instruction.  This special case calls this
-   interrupt routine */
-
-void INLINE_INTERRUPTS breakpoint_interrupt
-(cpu *processor,
- unsigned_word cia);
-
-/* Hardware generated interrupts
-
-   These hardware generated interrupt routines are called outside of
-   the instruction execution cycle and so return normally.
-
-   More importantly, they assume that the current instruction address
-   held within the processor is correct.
-
-   Return a non zero value if the interrupt was not successfully
-   delivered */
-
-int INLINE_INTERRUPTS decrementer_interrupt
+/* Hardware generated interrupts:
+
+   These asynchronous hardware generated interrupts may be called at
+   any time.  It is the responsibility of this (the interrupts) module
+   to ensure that interrupts are delivered correctly (when possible).
+   The delivery of these interrupts is controlled by the MSR's
+   external interrupt enable bit.  When ever the MSR's value is
+   changed, the processor must call the check_masked_interrupts()
+   function in case delivery has been made possible.
+
+   decrementer_interrupt is `edge' sensitive.  Multiple edges arriving
+   before the first edge has been delivered result in only one
+   interrupt.
+
+   external_interrupt is `level' sensitive.  An external interrupt
+   will only be delivered when the external interrupt port is
+   `asserted'. While interrupts are disabled, the external interrupt
+   can be asserted and then de-asserted without an interrupt
+   eventually being delivered. */
+
+enum {
+  external_interrupt_pending = 1,
+  decrementer_interrupt_pending = 2,
+};
+
+typedef struct _interrupts {
+  event_entry_tag delivery_scheduled;
+  int pending_interrupts;
+} interrupts;
+
+INLINE_INTERRUPTS\
+(void) check_masked_interrupts
 (cpu *processor);
 
-int INLINE_INTERRUPTS hard_system_reset
+INLINE_INTERRUPTS\
+(void) decrementer_interrupt
 (cpu *processor);
 
-int INLINE_INTERRUPTS soft_system_reset
-(cpu *processor);
-
-int INLINE_INTERRUPTS external_interrupt
-(cpu *processor);
+INLINE_INTERRUPTS\
+(void) external_interrupt
+(cpu *processor,
+ int is_asserted);
 
 #endif /* _INTERRUPTS_H_ */