* Makefile.def: Add dependencies for configure-opcodes

[deliverable/binutils-gdb.git] / sim / ppc / registers.h

diff --git a/sim/ppc/registers.h b/sim/ppc/registers.h
index 4da6ea4bbe652fae3c7e7af5bdb5b01f5d8cc369..15c9d43c9d68a56b48880603bc93ba51bd18cbfb 100644 (file)
--- a/sim/ppc/registers.h
+++ b/sim/ppc/registers.h
@@ -1,6 +1,6 @@
 /*  This file is part of the program psim.
 
-    Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au>
+    Copyright 1994, 1997, 2003 Andrew Cagney
 
     This program is free software; you can redistribute it and/or modify
     it under the terms of the GNU General Public License as published by
@@ -28,6 +28,19 @@
  *
  */
 
+/* FIXME:
+
+   For the moment use macro's to determine if the E500 or Altivec
+   registers should be included.  IGEN should instead of a :register:
+   field to facilitate the specification and generation of per ISA
+   registers.  */
+
+#ifdef WITH_E500
+#include "e500_registers.h"
+#endif
+#if WITH_ALTIVEC
+#include "altivec_registers.h"
+#endif
 
 /**
  ** General Purpose Registers
@@ -228,7 +241,6 @@ enum {
   srr1_subsequent_instruction = BIT(47)
 };
 
-
 /**
  ** storage interrupt registers
  **/
@@ -264,8 +276,14 @@ typedef struct _registers {
   /* Segment Registers */
   sreg sr[nr_of_srs];
 
-} registers;
+#if WITH_ALTIVEC
+  struct altivec_regs altivec;
+#endif
+#if WITH_E500
+  struct e500_regs e500;
+#endif
 
+} registers;
 
 /* dump out all the registers */
 
@@ -281,6 +299,12 @@ typedef enum {
   reg_gpr, reg_fpr, reg_spr, reg_msr,
   reg_cr, reg_fpscr, reg_pc, reg_sr,
   reg_insns, reg_stalls, reg_cycles,
+#ifdef WITH_ALTIVEC
+  reg_vr, reg_vscr,
+#endif
+#ifdef WITH_E500
+  reg_acc, reg_gprh, reg_evr,
+#endif
   nr_register_types
 } register_types;