: current_target_byte_order)
+/* PowerPC XOR endian.
+
+ In addition to the above, the simulator can support the PowerPC's
+ horrible XOR endian mode. This feature makes it possible to
+ control the endian mode of a processor using the MSR. */
+
+#ifndef WITH_XOR_ENDIAN
+#define WITH_XOR_ENDIAN 8
+#endif
+
+
/* Intel host BSWAP support:
Whether to use bswap on the 486 and pentiums rather than the 386
/options/smp@<nr-cpu> */
#ifndef WITH_SMP
-#define WITH_SMP 2
+#define WITH_SMP 5
#endif
#if WITH_SMP
#define MAX_NR_PROCESSORS WITH_SMP
/* Program environment:
- Two environments are available. VEA (or virtual environment
- architecture) and OEA (or operating environment architecture). The
- former is the environment that a user program would see while the
- latter is the environment as seen by an operating system. By
+ Three environments are available - UEA (user), VEA (virtual) and
+ OEA (perating). The former two are environment that users would
+ expect to see (VEA includes things like coherency and the time
+ base) while OEA is what an operating system expects to see. By
setting these to specific values, the build process is able to
eliminate non relevent environment code
CURRENT_ENVIRONMENT specifies which of vea or oea is required for
the current runtime. */
-#define VIRTUAL_ENVIRONMENT 1
-#define OPERATING_ENVIRONMENT 2
+#define USER_ENVIRONMENT 1
+#define VIRTUAL_ENVIRONMENT 2
+#define OPERATING_ENVIRONMENT 3
#ifndef WITH_ENVIRONMENT
#define WITH_ENVIRONMENT 0
queue implements this. Unfortunatly this adds the need to check
for any events once each full instruction cycle. */
-#define WITH_EVENTS (WITH_ENVIRONMENT != VIRTUAL_ENVIRONMENT)
+#define WITH_EVENTS (WITH_ENVIRONMENT != USER_ENVIRONMENT)
/* Time base:
of of some instruction cycles. */
#ifndef WITH_TIME_BASE
-#define WITH_TIME_BASE 1
+#define WITH_TIME_BASE (WITH_ENVIRONMENT != USER_ENVIRONMENT)
#endif
#define WITH_ASSERT 1
#endif
+/* Whether to check instructions for reserved bits being set */
+
+#ifndef WITH_RESERVED_BITS
+#define WITH_RESERVED_BITS 1
+#endif
+
/* include monitoring code */
#define MONITOR_INSTRUCTION_ISSUE 1
| MONITOR_INSTRUCTION_ISSUE)
#endif
+/* Current CPU model (models are in the generated models.h include file) */
+#ifndef WITH_MODEL
+#define WITH_MODEL 0
+#endif
+
+#define CURRENT_MODEL (WITH_MODEL \
+ ? WITH_MODEL \
+ : current_model)
+
+#ifndef WITH_DEFAULT_MODEL
+#define WITH_DEFAULT_MODEL DEFAULT_MODEL
+#endif
+
+#define MODEL_ISSUE_IGNORE (-1)
+#define MODEL_ISSUE_PROCESS 1
+
+#ifndef WITH_MODEL_ISSUE
+#define WITH_MODEL_ISSUE 0
+#endif
+extern int current_model_issue;
+#define CURRENT_MODEL_ISSUE (WITH_MODEL_ISSUE \
+ ? WITH_MODEL_ISSUE \
+ : current_model_issue)
/* INLINE CODE SELECTION:
/* Your compilers inline reserved word */
#ifndef INLINE
-#if defined(__GNUC__) && defined(__OPTIMIZE__)
+#if defined(__GNUC__) && defined(__OPTIMIZE__) && \
+ (DEFAULT_INLINE || SIM_ENDIAN_INLINE || BITS_INLINE || CPU_INLINE || VM_INLINE || CORE_INLINE \
+ || EVENTS_INLINE || MON_INLINE || INTERRUPTS_INLINE || REGISTERS_INLINE || DEVICE_TREE_INLINE \
+ || DEVICES_INLINE || SPREG_INLINE || SEMANTICS_INLINE || IDECODE_INLINE || MODEL_INLINE)
#define INLINE __inline__
#else
#define INLINE /*inline*/
#endif
/* Code that converts between hosts and target byte order. Used on
- every memory access (instruction and data). (See ppc-endian.h for
+ every memory access (instruction and data). (See sim-endian.h for
additional byte swapping configuration information) */
-#ifndef ENDIAN_INLINE
-#define ENDIAN_INLINE DEFAULT_INLINE
+#ifndef SIM_ENDIAN_INLINE
+#define SIM_ENDIAN_INLINE DEFAULT_INLINE
+#endif
+
+/* Low level bit manipulation routines used to work around a compiler
+ bug in 2.6.3. */
+
+#ifndef BITS_INLINE
+#define BITS_INLINE DEFAULT_INLINE
#endif
/* Code that gives access to various CPU internals such as registers.
not a leaf */
#ifndef DEVICE_TREE_INLINE
-#define DEVICE_TREE_INLINE DEFAULT_INLINE
+#define DEVICE_TREE_INLINE 0
#endif
#ifndef DEVICES_INLINE
#define IDECODE_INLINE DEFAULT_INLINE
#endif
+/* Model specific code used in simulating functional units. Note, it actaully
+ pays NOT to inline the PowerPC model functions (at least on the x86). This
+ is because if it is inlined, each PowerPC instruction gets a separate copy
+ of the code, which is not friendly to the cache. */
+
+#ifndef MODEL_INLINE
+#define MODEL_INLINE (DEFAULT_INLINE ? 1 : 0)
+#endif
+
+/* Code to print out what options we were compiled with. Because this
+ is called at process startup, it doesn't have to be inlined, but
+ if it isn't brought in and the model routines are inline, the model
+ routines will be pulled in twice. */
+
+#ifndef OPTIONS_INLINE
+#define OPTIONS_INLINE (DEFAULT_INLINE ? 1 : 0)
+#endif
+
#endif /* _CONFIG_H */