Ravenscar port for RISC-V

[deliverable/binutils-gdb.git] / sim / rx / cpu.h

diff --git a/sim/rx/cpu.h b/sim/rx/cpu.h
index 37ca7f8cb4076cc00760a5be63bbfd751810bb17..816973312d81085f7c394d423bfa20b3ed56cf89 100644 (file)
--- a/sim/rx/cpu.h
+++ b/sim/rx/cpu.h
@@ -1,6 +1,6 @@
 /* cpu.h --- declarations for the RX core.
 
-Copyright (C) 2005, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
+Copyright (C) 2005-2019 Free Software Foundation, Inc.
 Contributed by Red Hat, Inc.
 
 This file is part of the GNU simulators.
@@ -235,6 +235,7 @@ extern unsigned int heaptop;
 extern unsigned int heapbottom;
 
 extern int decode_opcode (void);
+extern void reset_decoder (void);
 extern void reset_pipeline_stats (void);
 extern void halt_pipeline_stats (void);
 extern void pipeline_stats (void);