Revert 'Remove unused struct serial::name field'

[deliverable/binutils-gdb.git] / sim / v850 / v850.igen

diff --git a/sim/v850/v850.igen b/sim/v850/v850.igen
index b3dcdfede368e6fe5e0c52c697a7fc9a4d4001b5..41a9075a8e79448ee9bfb22422f5bb20bd1916a9 100644 (file)
--- a/sim/v850/v850.igen
+++ b/sim/v850/v850.igen
@@ -7,6 +7,7 @@
 :option:::format-names:XIV,XV
 :option:::format-names:Z
 :option:::format-names:F_I
+:option:::format-names:C
 
 
 :model:::v850:v850:
@@ -19,6 +20,8 @@
 :model:::v850e2:v850e2:
 :option:::multi-sim:true
 :model:::v850e2v3:v850e2v3:
+:option:::multi-sim:true
+:model:::v850e3v5:v850e3v5:
 
 // Cache macros
 
@@ -27,6 +30,15 @@
 :cache:::unsigned:reg3:wwwww:(wwwww)
 :cache:::unsigned:reg4:W,WWWW:(W + (WWWW << 1))
 
+:cache:::unsigned:vreg1:VVVVV:(VVVVV)
+:cache:::unsigned:vreg1:VVVV:(VVVV << 1)
+:cache:::unsigned:vreg2:vvvvv:(vvvvv)
+:cache:::unsigned:vreg2:vvvv:(vvvv << 1)
+:cache:::unsigned:vreg3:xxxx:(xxxx << 1)
+:cache:::unsigned:vreg3:xxxxx:(xxxxx)
+:cache:::unsigned:imm2:ii:(ii)
+:cache:::unsigned:imm1:i:(i)
+
 :cache:::unsigned:reg1e:RRRR:(RRRR << 1)
 :cache:::unsigned:reg2e:rrrr:(rrrr << 1)
 :cache:::unsigned:reg3e:wwww:(wwww << 1)
@@ -61,6 +73,7 @@
 
 :cache:::unsigned:bit3:bbb:bbb
 :cache:::unsigned:bit4:bbbb:bbbb
+:cache:::unsigned:bit13:B,BBB:((B << 3) + BBB)
 
 
 // What do we do with an illegal instruction?
@@ -101,6 +114,7 @@ rrrrr,110000,RRRRR + iiiiiiiiiiiiiiii:VI:::addi
 rrrrr,111111,RRRRR + wwwww,011101,cccc!13,0:XI:::adf
 *v850e2
 *v850e2v3
+*v850e3v5
 "adf %s<cccc>, r<reg1>, r<reg2>, r<reg3>"
 {
   int cond = condition_met (cccc);
@@ -185,6 +199,7 @@ ddddd,1011,ddd,cccc:III:::Bcond
 "breakpoint":((disp17 == 0) && (cccc == 0x05))
 "b%s<cccc> <disp17>"
 *v850e2v3
+*v850e3v5
 {
   int cond;
   cond = condition_met (cccc);
@@ -202,6 +217,7 @@ rrrrr,11111100000 + wwwww,01101000010:XII:::bsh
 *v850e1
 *v850e2
 *v850e2v3
+*v850e3v5
 "bsh r<reg2>, r<reg3>"
 {
   unsigned32 value;
@@ -229,6 +245,7 @@ rrrrr,11111100000 + wwwww,01101000000:XII:::bsw
 *v850e1
 *v850e2
 *v850e2v3
+*v850e3v5
 "bsw r<reg2>, r<reg3>"
 {
 #define WORDHASNULLBYTE(x) (((x) - 0x01010101) & ~(x)&0x80808080)
@@ -259,6 +276,7 @@ rrrrr,11111100000 + wwwww,01101000000:XII:::bsw
 *v850e1
 *v850e2
 *v850e2v3
+*v850e3v5
 "callt <imm6>"
 {
   unsigned32 adr;
@@ -277,6 +295,7 @@ rrrrr,11111100000 + wwwww,01101000000:XII:::bsw
 rrrrr,111111,RRRRR + wwwww,00011101110:IX:::caxi
 *v850e2
 *v850e2v3
+*v850e3v5
 "caxi [reg1], reg2, reg3"
 {
   unsigned int z,s,cy,ov;
@@ -333,6 +352,7 @@ rrrrr,111111,RRRRR + 0000000011100100:IX:::clr1
 *v850e1
 *v850e2
 *v850e2v3
+*v850e3v5
 "clr1 r<reg2>, [r<reg1>]"
 {
   COMPAT_2 (OP_E407E0 ());
@@ -346,6 +366,7 @@ rrrrr,111111,RRRRR + 0000000011100100:IX:::clr1
 *v850e1
 *v850e2
 *v850e2v3
+*v850e3v5
 "ctret"
 {
   nia  = (CTPC & ~1);
@@ -361,6 +382,7 @@ rrrrr,111111,RRRRR + wwwww,011001,cccc,0:XI:::cmov
 *v850e1
 *v850e2
 *v850e2v3
+*v850e3v5
 "cmov %s<cccc>, r<reg1>, r<reg2>, r<reg3>"
 {
   int cond = condition_met (cccc);
@@ -374,6 +396,7 @@ rrrrr,111111,iiiii + wwwww,011000,cccc,0:XII:::cmov
 *v850e1
 *v850e2
 *v850e2v3
+*v850e3v5
 "cmov %s<cccc>, <imm5>, r<reg2>, r<reg3>"
 {
   int cond = condition_met (cccc);
@@ -416,6 +439,7 @@ rrrrr,010011,iiiii:II:::cmp
 *v850e1
 *v850e2
 *v850e2v3
+*v850e3v5
 "dispose <imm5>, <list12>":RRRRR == 0
 "dispose <imm5>, <list12>, [reg1]"
 {
@@ -451,6 +475,7 @@ rrrrr,111111,RRRRR + wwwww,01011000000:XI:::div
 *v850e1
 *v850e2
 *v850e2v3
+*v850e3v5
 "div r<reg1>, r<reg2>, r<reg3>"
 {
   COMPAT_2 (OP_2C007E0 ());
@@ -510,6 +535,7 @@ rrrrr,111111,RRRRR + wwwww,01010000000:XI:::divh
 *v850e1
 *v850e2
 *v850e2v3
+*v850e3v5
 "divh r<reg1>, r<reg2>, r<reg3>"
 {
   COMPAT_2 (OP_28007E0 ());
@@ -522,6 +548,7 @@ rrrrr,111111,RRRRR + wwwww,01010000010:XI:::divhu
 *v850e1
 *v850e2
 *v850e2v3
+*v850e3v5
 "divhu r<reg1>, r<reg2>, r<reg3>"
 {
   COMPAT_2 (OP_28207E0 ());
@@ -534,6 +561,7 @@ rrrrr,111111,RRRRR + wwwww,01011000010:XI:::divu
 *v850e1
 *v850e2
 *v850e2v3
+*v850e3v5
 "divu r<reg1>, r<reg2>, r<reg3>"
 {
   COMPAT_2 (OP_2C207E0 ());
@@ -544,6 +572,7 @@ rrrrr,111111,RRRRR + wwwww,01011000010:XI:::divu
 rrrrr,111111,RRRRR + wwwww,01011111100:XI:::divq
 *v850e2
 *v850e2v3
+*v850e3v5
 "divq r<reg1>, r<reg2>, r<reg3>"
 {
   unsigned int quotient;
@@ -567,6 +596,7 @@ rrrrr,111111,RRRRR + wwwww,01011111100:XI:::divq
 rrrrr,111111,RRRRR + wwwww,01011111110:XI:::divqu
 *v850e2
 *v850e2v3
+*v850e3v5
 "divq r<reg1>, r<reg2>, r<reg3>"
 {
   unsigned int quotient;
@@ -600,6 +630,7 @@ rrrrr,111111,RRRRR + wwwww,01011111110:XI:::divqu
 "eiret"
 *v850e2
 *v850e2v3
+*v850e3v5
 {
   TRACE_ALU_INPUT1 (MPM & MPM_AUE);
 
@@ -625,6 +656,7 @@ rrrrr,111111,RRRRR + wwwww,01011111110:XI:::divqu
 "feret"
 *v850e2
 *v850e2v3
+*v850e3v5
 {
   TRACE_ALU_INPUT1 (MPM & MPM_AUE);
 
@@ -649,6 +681,7 @@ rrrrr,111111,RRRRR + wwwww,01011111110:XI:::divqu
 "fetrap"
 *v850e2
 *v850e2v3
+*v850e3v5
 {
   TRACE_ALU_INPUT0 ();
 
@@ -678,6 +711,7 @@ rrrrr,111111,RRRRR + wwwww,01011111110:XI:::divqu
 rrrrr,11111100000 + wwwww,01101000110:XII:::hsh
 *v850e2
 *v850e2v3
+*v850e3v5
 "hsh r<reg2>, r<reg3>"
 {
   unsigned32 value;
@@ -701,6 +735,7 @@ rrrrr,11111100000 + wwwww,01101000100:XII:::hsw
 *v850e1
 *v850e2
 *v850e2v3
+*v850e3v5
 "hsw r<reg2>, r<reg3>"
 {
   unsigned32 value;
@@ -735,6 +770,7 @@ rrrrr!0,11110,dddddd + ddddddddddddddd,0:V:::jarl
 00000010111,RRRRR!0 + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::jarl32
 *v850e2
 *v850e2v3
+*v850e3v5
 "jarl <imm32>, r<reg1>"
 {
   GR[reg1] = nia;
@@ -744,6 +780,16 @@ rrrrr!0,11110,dddddd + ddddddddddddddd,0:V:::jarl
 }
 
 
+11000111111,RRRRR + wwwww!0,00101100000:XI:::jarl_reg
+*v850e3v5
+"jarl [r<reg1>], r<reg3>"
+{
+  GR[reg3] = nia;
+  nia = GR[reg1];
+  TRACE_BRANCH_RESULT (nia);
+}
+
+
 // JMP
 00000000011,RRRRR:I:::jmp
 "jmp [r<reg1>]"
@@ -755,6 +801,7 @@ rrrrr!0,11110,dddddd + ddddddddddddddd,0:V:::jarl
 00000110111,RRRRR + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::jmp32
 *v850e2
 *v850e2v3
+*v850e3v5
 "jmp <imm32>[r<reg1>]"
 {
   nia = (GR[reg1] + imm32) & ~1;
@@ -776,6 +823,7 @@ rrrrr!0,11110,dddddd + ddddddddddddddd,0:V:::jarl
 0000001011100000 + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::jr32
 *v850e2
 *v850e2v3
+*v850e3v5
 "jr <imm32>"
 {
   nia = (cia + imm32) & ~1;
@@ -794,6 +842,7 @@ rrrrr,111000,RRRRR + dddddddddddddddd:VII:::ld.b
 00000111100,RRRRR+wwwww,ddddddd,0101+dddddddddddddddd:XIV:::ld.b
 "ld.b <disp23>[r<reg1>], r<reg3>"
 *v850e2v3
+*v850e3v5
 {
   unsigned32 addr = GR[reg1] + disp23;
   unsigned32 result = EXTEND8 (load_data_mem (sd, addr, 1));
@@ -809,6 +858,7 @@ rrrrr,111001,RRRRR + ddddddddddddddd,0:VII:::ld.h
 
 00000111100,RRRRR+wwwww,dddddd,00111+dddddddddddddddd:XIV:::ld.h
 *v850e2v3
+*v850e3v5
 "ld.h <disp23>[r<reg1>], r<reg3>"
 {
   unsigned32 addr = GR[reg1] + disp23;
@@ -825,6 +875,7 @@ rrrrr,111001,RRRRR + ddddddddddddddd,1:VII:::ld.w
 
 00000111100,RRRRR+wwwww,dddddd,01001+dddddddddddddddd:XIV:::ld.w
 *v850e2v3
+*v850e3v5
 "ld.w <disp23>[r<reg1>], r<reg3>"
 {
   unsigned32 addr = GR[reg1] + disp23;
@@ -833,11 +884,25 @@ rrrrr,111001,RRRRR + ddddddddddddddd,1:VII:::ld.w
   TRACE_LD (addr, result);
 }
 
+00000111101,RRRRR+wwwww,dddddd,01001+dddddddddddddddd:XIV:::ld.dw
+*v850e3v5
+"ld.dw <disp23>[r<reg1>], r<reg3>"
+{
+  unsigned32 addr = GR[reg1] + disp23;
+  unsigned32 result = load_data_mem (sd, addr, 4);
+  GR[reg3] = result;
+  TRACE_LD (addr, result);
+  result = load_data_mem (sd, addr + 4, 4);
+  GR[reg3 + 1] = result;
+  TRACE_LD (addr + 4, result);
+}
+
 rrrrr!0,11110,b,RRRRR + ddddddddddddddd,1:VII:::ld.bu
 *v850e
 *v850e1
 *v850e2
 *v850e2v3
+*v850e3v5
 "ld.bu <disp16>[r<reg1>], r<reg2>"
 {
   COMPAT_2 (OP_10780 ());
@@ -845,6 +910,7 @@ rrrrr!0,11110,b,RRRRR + ddddddddddddddd,1:VII:::ld.bu
 
 00000111101,RRRRR+wwwww,ddddddd,0101+dddddddddddddddd:XIV:::ld.bu
 *v850e2v3
+*v850e3v5
 "ld.bu <disp23>[r<reg1>], r<reg3>"
 { 
   unsigned32 addr = GR[reg1] + disp23;
@@ -858,6 +924,7 @@ rrrrr!0,111111,RRRRR + ddddddddddddddd,1:VII:::ld.hu
 *v850e1
 *v850e2
 *v850e2v3
+*v850e3v5
 "ld.hu <disp16>[r<reg1>], r<reg2>"
 {
   COMPAT_2 (OP_107E0 ());
@@ -865,6 +932,7 @@ rrrrr!0,111111,RRRRR + ddddddddddddddd,1:VII:::ld.hu
 
 00000111101,RRRRR+wwwww,dddddd,00111+dddddddddddddddd:XIV:::ld.hu
 *v850e2v3
+*v850e3v5
 "ld.hu <disp23>[r<reg1>], r<reg3>"
 {
   unsigned32 addr = GR[reg1] + disp23;
@@ -876,19 +944,25 @@ rrrrr!0,111111,RRRRR + ddddddddddddddd,1:VII:::ld.hu
 
 
 // LDSR
-regID,111111,RRRRR + 0000000000100000:IX:::ldsr
-"ldsr r<reg1>, s<regID>"
+regID,111111,RRRRR + selID,00000100000:IX:::ldsr
+"ldsr r<reg1>, s<regID>":(selID == 0)
+"ldsr r<reg1>, s<regID>, <selID>"
 {
   uint32 sreg = GR[reg1];
   TRACE_ALU_INPUT1 (GR[reg1]);
-  
-   if ((idecode_issue == idecode_v850e2_issue
-       || idecode_issue == idecode_v850e2v3_issue)
-      && regID < 28)
+
+  /* FIXME: For now we ignore the selID.  */
+  if (idecode_issue == idecode_v850e3v5_issue && selID != 0)
+    {
+      (CPU)->reg.selID_sregs[selID][regID] = sreg;
+    }
+  else if ((   idecode_issue == idecode_v850e2_issue
+            || idecode_issue == idecode_v850e3v5_issue
+           || idecode_issue == idecode_v850e2v3_issue)
+           && regID < 28)
     {
       int protect_p = (PSW & PSW_NPV) ? 1 : 0;
 
-      
       switch (BSEL & 0xffff)
        {
        case 0x0000:
@@ -1032,11 +1106,11 @@ regID,111111,RRRRR + 0000000000100000:IX:::ldsr
 }
 
 
-
 // MAC
 rrrrr,111111,RRRRR + wwww,0011110,mmmm,0:XI:::mac
 *v850e2
 *v850e2v3
+*v850e3v5
 "mac r<reg1>, r<reg2>, r<reg3e>, r<reg4e>"
 {
   unsigned long op0;
@@ -1110,6 +1184,7 @@ rrrrr,111111,RRRRR + wwww,0011110,mmmm,0:XI:::mac
 rrrrr,111111,RRRRR + wwww,0011111,mmmm,0:XI:::macu
 *v850e2
 *v850e2v3
+*v850e3v5
 "macu r<reg1>, r<reg2>, r<reg3e>, r<reg4e>"
 {
   unsigned long op0;
@@ -1177,6 +1252,7 @@ rrrrr!0,010000,iiiii:II:::mov
 *v850e1
 *v850e2
 *v850e2v3
+*v850e3v5
 "mov <imm32>, r<reg1>"
 {
   SAVE_2;
@@ -1213,6 +1289,7 @@ rrrrr,111111,RRRRR + wwwww,01000100000:XI:::mul
 *v850e1
 *v850e2
 *v850e2v3
+*v850e3v5
 "mul r<reg1>, r<reg2>, r<reg3>"
 {
   COMPAT_2 (OP_22007E0 ());
@@ -1223,6 +1300,7 @@ rrrrr,111111,iiiii + wwwww,01001,IIII,00:XII:::mul
 *v850e1
 *v850e2
 *v850e2v3
+*v850e3v5
 "mul <imm9>, r<reg2>, r<reg3>"
 {
   COMPAT_2 (OP_24007E0 ());
@@ -1259,6 +1337,7 @@ rrrrr,111111,RRRRR + wwwww,01000100010:XI:::mulu
 *v850e1
 *v850e2
 *v850e2v3
+*v850e3v5
 "mulu r<reg1>, r<reg2>, r<reg3>"
 {
   COMPAT_2 (OP_22207E0 ());
@@ -1269,6 +1348,7 @@ rrrrr,111111,iiiii + wwwww,01001,IIII,10:XII:::mulu
 *v850e1
 *v850e2
 *v850e2v3
+*v850e3v5
 "mulu <imm9>, r<reg2>, r<reg3>"
 {
   COMPAT_2 (OP_24207E0 ());
@@ -1306,6 +1386,7 @@ rrrrr,111111,RRRRR + 0000000011100010:IX:::not1
 *v850e1
 *v850e2
 *v850e2v3
+*v850e3v5
 "not1 r<reg2>, r<reg1>"
 {
   COMPAT_2 (OP_E207E0 ());
@@ -1337,6 +1418,7 @@ rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori
 *v850e1
 *v850e2
 *v850e2v3
+*v850e3v5
 "prepare <list12>, <imm5>"
 {
   int  i;
@@ -1364,6 +1446,7 @@ rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori
 *v850e1
 *v850e2
 *v850e2v3
+*v850e3v5
 "prepare <list12>, <imm5>, sp"
 {
   COMPAT_2 (OP_30780 ());
@@ -1374,6 +1457,7 @@ rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori
 *v850e1
 *v850e2
 *v850e2v3
+*v850e3v5
 "prepare <list12>, <imm5>, <uimm16>"
 {
   COMPAT_2 (OP_B0780 ());
@@ -1384,6 +1468,7 @@ rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori
 *v850e1
 *v850e2
 *v850e2v3
+*v850e3v5
 "prepare <list12>, <imm5>, <uimm16>"
 {
   COMPAT_2 (OP_130780 ());
@@ -1394,13 +1479,12 @@ rrrrr,110100,RRRRR + iiiiiiiiiiiiiiii:VI:::ori
 *v850e1
 *v850e2
 *v850e2v3
+*v850e3v5
 "prepare <list12>, <imm5>, <uimm32>"
 {
   COMPAT_2 (OP_1B0780 ());
 }
 
-
-
 // RETI
 0000011111100000 + 0000000101000000:X:::reti
 "reti"
@@ -1441,6 +1525,7 @@ rrrrr,010101,iiiii:II:::sar
 rrrrr,111111,RRRRR + wwwww,00010100010:XI:::sar
 *v850e2
 *v850e2v3
+*v850e3v5
 "sar r<reg1>, r<reg2>, r<reg3>"
 {
   TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]);
@@ -1450,11 +1535,12 @@ rrrrr,111111,RRRRR + wwwww,00010100010:XI:::sar
 
 
 // SASF
-rrrrr,1111110,cccc + 0000001000000000:IX:::sasf
+rrrrr,1111110,cccc+0000001000000000:IX:::sasf
 *v850e
 *v850e1
 *v850e2
 *v850e2v3
+*v850e3v5
 "sasf %s<cccc>, r<reg2>"
 {
   COMPAT_2 (OP_20007E0 ());
@@ -1478,6 +1564,7 @@ rrrrr!0,010001,iiiii:II:::satadd
 rrrrr,111111,RRRRR + wwwww,01110111010:XI:::satadd
 *v850e2
 *v850e2v3
+*v850e3v5
 "satadd r<reg1>, r<reg2>, r<reg3>"
 {
   TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]);
@@ -1497,6 +1584,7 @@ rrrrr!0,000101,RRRRR:I:::satsub
 rrrrr,111111,RRRRR + wwwww,01110011010:XI:::satsub
 *v850e2
 *v850e2v3
+*v850e3v5
 "satsub r<reg1>, r<reg2>, r<reg3>"
 {
   TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]);
@@ -1528,6 +1616,7 @@ rrrrr!0,000100,RRRRR:I:::satsubr
 rrrrr,111111,RRRRR + wwwww,011100,cccc!13,0:XI:::sbf
 *v850e2
 *v850e2v3
+*v850e3v5
 "sbf %s<cccc>, r<reg1>, r<reg2>, r<reg3>"
 {
   int cond = condition_met (cccc);
@@ -1542,6 +1631,7 @@ rrrrr,111111,RRRRR + wwwww,011100,cccc!13,0:XI:::sbf
 rrrrr,11111100000 + wwwww,01101100100:IX:::sch0l
 *v850e2
 *v850e2v3
+*v850e3v5
 "sch0l r<reg2>, r<reg3>"
 {
   unsigned int pos, op0;
@@ -1591,6 +1681,7 @@ rrrrr,11111100000 + wwwww,01101100100:IX:::sch0l
 rrrrr,11111100000 + wwwww,01101100000:IX:::sch0r
 *v850e2
 *v850e2v3
+*v850e3v5
 "sch0r r<reg2>, r<reg3>"
 {
   unsigned int pos, op0;
@@ -1638,6 +1729,7 @@ rrrrr,11111100000 + wwwww,01101100000:IX:::sch0r
 rrrrr,11111100000 + wwwww,01101100110:IX:::sch1l
 *v850e2
 *v850e2v3
+*v850e3v5
 "sch1l r<reg2>, r<reg3>"
 {
   unsigned int pos, op0;
@@ -1685,6 +1777,7 @@ rrrrr,11111100000 + wwwww,01101100110:IX:::sch1l
 rrrrr,11111100000 + wwwww,01101100010:IX:::sch1r
 *v850e2
 *v850e2v3
+*v850e3v5
 "sch1r r<reg2>, r<reg3>"
 {
   unsigned int pos, op0;
@@ -1732,6 +1825,7 @@ rrrrr,11111100000 + wwwww,01101100010:IX:::sch1r
 rrrrr,111111,RRRRR + wwwww,00011000010:XI:::shl
 *v850e2
 *v850e2v3
+*v850e3v5
 "shl r<reg1>, r<reg2>, r<reg3>"
 {
   TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]);
@@ -1743,6 +1837,7 @@ rrrrr,111111,RRRRR + wwwww,00011000010:XI:::shl
 rrrrr,111111,RRRRR + wwwww,00010000010:XI:::shr
 *v850e2
 *v850e2v3
+*v850e3v5
 "shr r<reg1>, r<reg2>, r<reg3>"
 {
   TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]);
@@ -1773,6 +1868,7 @@ rrrrr,111111,RRRRR + 0000000011100000:IX:::set1
 *v850e1
 *v850e2
 *v850e2v3
+*v850e3v5
 "set1 r<reg2>, [r<reg1>]"
 {
   COMPAT_2 (OP_E007E0 ());
@@ -1863,6 +1959,7 @@ rrrrr!0,0000110,dddd:IV:::sld.bu
 *v850e1
 *v850e2
 *v850e2v3
+*v850e3v5
 "sld.b <disp4>[ep], r<reg2>":(PSW & PSW_US)
 "sld.bu <disp4>[ep], r<reg2>"
 {
@@ -1886,6 +1983,7 @@ rrrrr!0,0000111,dddd:IV:::sld.hu
 *v850e1
 *v850e2
 *v850e2v3
+*v850e3v5
 "sld.h <disp5>[ep], r<reg2>":(PSW & PSW_US)
 "sld.hu <disp5>[ep], r<reg2>"
 {
@@ -1934,6 +2032,7 @@ rrrrr,111010,RRRRR + dddddddddddddddd:VII:::st.b
 
 00000111100,RRRRR + wwwww,ddddddd,1101 + dddddddddddddddd:XIV:::st.b
 *v850e2v3
+*v850e3v5
 "st.b r<reg3>, <disp23>[r<reg1>]"
 {
   unsigned32 addr = GR[reg1] + disp23;
@@ -1949,6 +2048,7 @@ rrrrr,111011,RRRRR + ddddddddddddddd,0:VII:::st.h
 
 00000111101,RRRRR+wwwww,dddddd,01101+dddddddddddddddd:XIV:::st.h
 *v850e2v3
+*v850e3v5
 "st.h r<reg3>, <disp23>[r<reg1>]"
 {
   unsigned32 addr = GR[reg1] + disp23;
@@ -1964,6 +2064,7 @@ rrrrr,111011,RRRRR + ddddddddddddddd,1:VII:::st.w
 
 00000111100,RRRRR+wwwww,dddddd,01111+dddddddddddddddd:XIV:::st.w
 *v850e2v3
+*v850e3v5
 "st.w r<reg3>, <disp23>[r<reg1>]"
 {
   unsigned32 addr = GR[reg1] + disp23;
@@ -1971,6 +2072,17 @@ rrrrr,111011,RRRRR + ddddddddddddddd,1:VII:::st.w
   TRACE_ST (addr, GR[reg3]);
 }
 
+00000111101,RRRRR+wwwww,dddddd,01111+dddddddddddddddd:XIV:::st.dw
+*v850e3v5
+"st.dw r<reg3>, <disp23>[r<reg1>]"
+{
+  unsigned32 addr = GR[reg1] + disp23;
+  store_data_mem (sd, addr, 4, GR[reg3]);
+  TRACE_ST (addr, GR[reg3]);
+  store_data_mem (sd, addr + 4, 4, GR[reg3 + 1]);
+  TRACE_ST (addr + 4, GR[reg3 + 1]);
+}
+
 
 // STSR
 rrrrr,111111,regID + 0000000001000000:IX:::stsr
@@ -1979,6 +2091,7 @@ rrrrr,111111,regID + 0000000001000000:IX:::stsr
   uint32 sreg = 0;
 
   if ((idecode_issue == idecode_v850e2_issue
+       || idecode_issue == idecode_v850e3v5_issue
        || idecode_issue == idecode_v850e2v3_issue)
       && regID < 28)
     {
@@ -2057,6 +2170,7 @@ rrrrr,001100,RRRRR:I:::subr
 *v850e1
 *v850e2
 *v850e2v3
+*v850e3v5
 "switch r<reg1>"
 {
   unsigned long adr;
@@ -2073,6 +2187,7 @@ rrrrr,001100,RRRRR:I:::subr
 *v850e1
 *v850e2
 *v850e2v3
+*v850e3v5
 "sxb r<reg1>"
 {
   TRACE_ALU_INPUT1 (GR[reg1]);
@@ -2086,6 +2201,7 @@ rrrrr,001100,RRRRR:I:::subr
 *v850e1
 *v850e2
 *v850e2v3
+*v850e3v5
 "sxh r<reg1>"
 {
   TRACE_ALU_INPUT1 (GR[reg1]);
@@ -2119,6 +2235,7 @@ rrrrr,111111,RRRRR + 0000000011100110:IX:::tst1
 *v850e1
 *v850e2
 *v850e2v3
+*v850e3v5
 "tst1 r<reg2>, [r<reg1>]"
 {
   COMPAT_2 (OP_E607E0 ());
@@ -2144,6 +2261,7 @@ rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori
 *v850e1
 *v850e2
 *v850e2v3
+*v850e3v5
 "zxb r<reg1>"
 {
   TRACE_ALU_INPUT1 (GR[reg1]);
@@ -2157,6 +2275,7 @@ rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori
 *v850e1
 *v850e2
 *v850e2v3
+*v850e3v5
 "zxh r<reg1>"
 {
   TRACE_ALU_INPUT1 (GR[reg1]);
@@ -2177,14 +2296,22 @@ rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori
 *v850e1
 *v850e2
 *v850e2v3
+*v850e3v5
 "dbtrap"
 {
-  DBPC = cia + 2;
-  DBPSW = PSW;
-  PSW = PSW | (PSW_NP | PSW_EP | PSW_ID);
-  PC = 0x00000060;
-  nia = 0x00000060;
-  TRACE_BRANCH0 ();
+  if (STATE_OPEN_KIND (SD) == SIM_OPEN_DEBUG)
+    {
+      sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
+    }
+  else 
+    {
+      DBPC = cia + 2;
+      DBPSW = PSW;
+      PSW = PSW | (PSW_NP | PSW_EP | PSW_ID);
+      PC = 0x00000060;
+      nia = 0x00000060;
+      TRACE_BRANCH0 ();
+    }
 }
 
 // New breakpoint: 0x7E0 0x7E0
@@ -2198,6 +2325,7 @@ rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori
 *v850e1
 *v850e2
 *v850e2v3
+*v850e3v5
 "dbret"
 {
   nia = DBPC;
@@ -2238,6 +2366,7 @@ rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori
 // ABSF.D
 rrrr,011111100000 + wwww,010001011000:F_I:::absf_d
 *v850e2v3
+*v850e3v5
 "absf.d r<reg2e>, r<reg3e>"
 {
   sim_fpu ans, wop;
@@ -2257,6 +2386,7 @@ rrrr,011111100000 + wwww,010001011000:F_I:::absf_d
 // ABSF.S
 rrrrr,11111100000 + wwwww,10001001000:F_I:::absf_s
 *v850e2v3
+*v850e3v5
 "absf.s r<reg2>, r<reg3>"
 {
   sim_fpu ans, wop;
@@ -2275,6 +2405,7 @@ rrrrr,11111100000 + wwwww,10001001000:F_I:::absf_s
 // ADDF.D
 rrrr,0111111,RRRR,0 + wwww,010001110000:F_I:::addf_d
 *v850e2v3
+*v850e3v5
 "addf.d r<reg1e>, r<reg2e>, r<reg3e>"
 {
   sim_fpu ans, wop1, wop2;
@@ -2296,6 +2427,7 @@ rrrr,0111111,RRRR,0 + wwww,010001110000:F_I:::addf_d
 // ADDF.S
 rrrrr,111111,RRRRR + wwwww,10001100000:F_I:::addf_s
 *v850e2v3
+*v850e3v5
 "addf.s r<reg1>, r<reg2>, r<reg3>"
 {
   sim_fpu ans, wop1, wop2;
@@ -2317,6 +2449,7 @@ rrrrr,111111,RRRRR + wwwww,10001100000:F_I:::addf_s
 // CMOVF.D
 rrrr,0111111,RRRR,0 + wwww!0,01000001,bbb,0:F_I:::cmovf_d
 *v850e2v3
+*v850e3v5
 "cmovf.d <bbb>, r<reg1e>, r<reg2e>, r<reg3e>"
 {
   unsigned int ophi,oplow;
@@ -2347,6 +2480,7 @@ rrrr,0111111,RRRR,0 + wwww!0,01000001,bbb,0:F_I:::cmovf_d
 // CMOVF.S
 rrrrr,111111,RRRRR!0 + wwwww!0,1000000,bbb,0:F_I:::cmovf_s
 *v850e2v3
+*v850e3v5
 "cmovf.d <bbb>, r<reg1>, r<reg2>, r<reg3>"
 {
   unsigned int op;
@@ -2374,8 +2508,9 @@ rrrrr,111111,RRRRR!0 + wwwww!0,1000000,bbb,0:F_I:::cmovf_s
 // CMPF.D
 rrrr,0111111,RRRR,0 + 0,FFFF,1000011,bbb,0:F_I:::cmpf_d
 *v850e2v3
-"cmpf.d %s<FFFF>, r<reg1e>, r<reg2e>":(bbb == 0)
-"cmpf.d %s<FFFF>, r<reg1e>, r<reg2e>, <bbb>"
+*v850e3v5
+"cmpf.d %s<FFFF>, r<reg2e>, r<reg1e>":(bbb == 0)
+"cmpf.d %s<FFFF>, r<reg2e>, r<reg1e>, <bbb>"
 {
   int result;
   sim_fpu wop1;
@@ -2383,9 +2518,9 @@ rrrr,0111111,RRRR,0 + 0,FFFF,1000011,bbb,0:F_I:::cmpf_d
   
   sim_fpu_232to (&wop1, GR[reg1e+1], GR[reg1e]);
   sim_fpu_232to (&wop2, GR[reg2e+1], GR[reg2e]);
-  TRACE_FP_INPUT_FPU2 (&wop1, &wop2);
+  TRACE_FP_INPUT_FPU2 (&wop2, &wop1);
 
-  result = v850_float_compare(sd, FFFF, wop1, wop2, 1);
+  result = v850_float_compare(sd, FFFF, wop2, wop1, 1);
 
   if (result)  
     SET_FPCC(bbb);
@@ -2398,8 +2533,9 @@ rrrr,0111111,RRRR,0 + 0,FFFF,1000011,bbb,0:F_I:::cmpf_d
 // CMPF.S
 rrrrr,111111,RRRRR + 0,FFFF,1000010,bbb,0:F_I:::cmpf_s
 *v850e2v3
-"cmpf.s %s<FFFF>, r<reg1>, r<reg2>":(bbb == 0)
-"cmpf.s %s<FFFF>, r<reg1>, r<reg2>, <bbb>"
+*v850e3v5
+"cmpf.s %s<FFFF>, r<reg2>, r<reg1>":(bbb == 0)
+"cmpf.s %s<FFFF>, r<reg2>, r<reg1>, <bbb>"
 {
   int result; 
   sim_fpu wop1;
@@ -2407,9 +2543,9 @@ rrrrr,111111,RRRRR + 0,FFFF,1000010,bbb,0:F_I:::cmpf_s
 
   sim_fpu_32to( &wop1, GR[reg1] );
   sim_fpu_32to( &wop2, GR[reg2] );
-  TRACE_FP_INPUT_FPU2 (&wop1, &wop2);
+  TRACE_FP_INPUT_FPU2 (&wop2, &wop1);
 
-  result = v850_float_compare(sd, FFFF, wop1, wop2, 0);
+  result = v850_float_compare(sd, FFFF, wop2, wop1, 0);
 
   if (result)  
     SET_FPCC(bbb);
@@ -2422,9 +2558,10 @@ rrrrr,111111,RRRRR + 0,FFFF,1000010,bbb,0:F_I:::cmpf_s
 // CVTF.DL
 rrrr,011111100100 + wwww,010001010100:F_I:::cvtf_dl
 *v850e2v3
+*v850e3v5
 "cvtf.dl r<reg2e>, r<reg3e>"
 {
-  unsigned64 ans;
+  signed64 ans;
   sim_fpu wop;
   sim_fpu_status status;
 
@@ -2444,6 +2581,7 @@ rrrr,011111100100 + wwww,010001010100:F_I:::cvtf_dl
 // CVTF.DS
 rrrr,011111100011 + wwwww,10001010010:F_I:::cvtf_ds
 *v850e2v3
+*v850e3v5
 "cvtf.ds r<reg2e>, r<reg3>"
 {
   sim_fpu wop;
@@ -2463,9 +2601,10 @@ rrrr,011111100011 + wwwww,10001010010:F_I:::cvtf_ds
 // CVTF.DW
 rrrr,011111100100 + wwwww,10001010000:F_I:::cvtf_dw
 *v850e2v3
+*v850e3v5
 "cvtf.dw r<reg2e>, r<reg3>"
 {
-  uint32 ans;
+  int32 ans;
   sim_fpu wop;
   sim_fpu_status status;
 
@@ -2484,6 +2623,7 @@ rrrr,011111100100 + wwwww,10001010000:F_I:::cvtf_dw
 // CVTF.LD
 rrrr,011111100001 + wwww,010001010010:F_I:::cvtf_ld
 *v850e2v3
+*v850e3v5
 "cvtf.ld r<reg2e>, r<reg3e>"
 {
   signed64 op;
@@ -2505,6 +2645,7 @@ rrrr,011111100001 + wwww,010001010010:F_I:::cvtf_ld
 // CVTF.LS
 rrrr,011111100001 + wwwww,10001000010:F_I:::cvtf_ls
 *v850e2v3
+*v850e3v5
 "cvtf.ls r<reg2e>, r<reg3>"
 {
   signed64 op;
@@ -2526,6 +2667,7 @@ rrrr,011111100001 + wwwww,10001000010:F_I:::cvtf_ls
 // CVTF.SD
 rrrrr,11111100010 + wwww,010001010010:F_I:::cvtf_sd
 *v850e2v3
+*v850e3v5
 "cvtf.sd r<reg2>, r<reg3e>"
 {
   sim_fpu wop;
@@ -2544,6 +2686,7 @@ rrrrr,11111100010 + wwww,010001010010:F_I:::cvtf_sd
 // CVTF.SL
 rrrrr,11111100100 + wwww,010001000100:F_I:::cvtf_sl
 *v850e2v3
+*v850e3v5
 "cvtf.sl r<reg2>, r<reg3e>"
 {
   signed64 ans;
@@ -2566,9 +2709,10 @@ rrrrr,11111100100 + wwww,010001000100:F_I:::cvtf_sl
 // CVTF.SW
 rrrrr,11111100100 + wwwww,10001000000:F_I:::cvtf_sw
 *v850e2v3
+*v850e3v5
 "cvtf.sw r<reg2>, r<reg3>"
 {
-  uint32 ans;
+  int32 ans;
   sim_fpu wop;
   sim_fpu_status status;
 
@@ -2587,6 +2731,7 @@ rrrrr,11111100100 + wwwww,10001000000:F_I:::cvtf_sw
 // CVTF.WD
 rrrrr,11111100000 + wwww,010001010010:F_I:::cvtf_wd
 *v850e2v3
+*v850e3v5
 "cvtf.wd r<reg2>, r<reg3e>"
 {
   sim_fpu wop;
@@ -2605,6 +2750,7 @@ rrrrr,11111100000 + wwww,010001010010:F_I:::cvtf_wd
 // CVTF.WS
 rrrrr,11111100000 + wwwww,10001000010:F_I:::cvtf_ws
 *v850e2v3
+*v850e3v5
 "cvtf.ws r<reg2>, r<reg3>"
 {
   sim_fpu wop;
@@ -2623,6 +2769,7 @@ rrrrr,11111100000 + wwwww,10001000010:F_I:::cvtf_ws
 // DIVF.D
 rrrr,0111111,RRRR,0 + wwww,010001111110:F_I:::divf_d
 *v850e2v3
+*v850e3v5
 "divf.d r<reg1e>, r<reg2e>, r<reg3e>"
 {
   sim_fpu ans, wop1, wop2;
@@ -2644,6 +2791,7 @@ rrrr,0111111,RRRR,0 + wwww,010001111110:F_I:::divf_d
 // DIVF.S
 rrrrr,111111,RRRRR + wwwww,10001101110:F_I:::divf_s
 *v850e2v3
+*v850e3v5
 "divf.s r<reg1>, r<reg2>, r<reg3>"
 {
   sim_fpu ans, wop1, wop2;
@@ -2686,9 +2834,34 @@ rrrrr,111111,RRRRR + wwwww,101,W,00,WWWW,0:F_I:::maddf_s
   TRACE_FP_RESULT_FPU1 (&ans);
 }
 
+// FMAF.S
+rrrrr,111111,RRRRR + wwwww,10011100000:F_I:::fmaf_s
+*v850e3v5
+"fmaf.s r<reg1>, r<reg2>, r<reg3>"
+{
+  sim_fpu ans, wop1, wop2, wop3;
+  sim_fpu_status status;
+
+  sim_fpu_32to (&wop1, GR[reg1]);
+  sim_fpu_32to (&wop2, GR[reg2]);
+  sim_fpu_32to (&wop3, GR[reg3]);
+  TRACE_FP_INPUT_FPU3 (&wop1, &wop2, &wop3);
+
+  status = sim_fpu_mul (&ans, &wop1, &wop2);
+  wop1 = ans;
+  status |= sim_fpu_add (&ans, &wop1, &wop3);
+  status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
+
+  update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
+
+  sim_fpu_to32 (&GR[reg3], &ans);
+  TRACE_FP_RESULT_FPU1 (&ans);
+}
+
 // MAXF.D
 rrrr,0111111,RRRR,0 + wwww,010001111000:F_I:::maxf_d
 *v850e2v3
+*v850e3v5
 "maxf.d r<reg1e>, r<reg2e>, r<reg3e>"
 {
   sim_fpu ans, wop1, wop2;
@@ -2726,6 +2899,7 @@ rrrr,0111111,RRRR,0 + wwww,010001111000:F_I:::maxf_d
 // MAXF.S
 rrrrr,111111,RRRRR + wwwww,10001101000:F_I:::maxf_s
 *v850e2v3
+*v850e3v5
 "maxf.s r<reg1>, r<reg2>, r<reg3>"
 {
   sim_fpu ans, wop1, wop2;
@@ -2763,6 +2937,7 @@ rrrrr,111111,RRRRR + wwwww,10001101000:F_I:::maxf_s
 // MINF.D
 rrrr,0111111,RRRR,0 + wwww,010001111010:F_I:::minf_d
 *v850e2v3
+*v850e3v5
 "minf.d r<reg1e>, r<reg2e>, r<reg3e>"
 {
   sim_fpu ans, wop1, wop2;
@@ -2800,6 +2975,7 @@ rrrr,0111111,RRRR,0 + wwww,010001111010:F_I:::minf_d
 // MINF.S
 rrrrr,111111,RRRRR + wwwww,10001101010:F_I:::minf_s
 *v850e2v3
+*v850e3v5
 "minf.s r<reg1>, r<reg2>, r<reg3>"
 {
   sim_fpu ans, wop1, wop2;
@@ -2859,9 +3035,35 @@ rrrrr,111111,RRRRR + wwwww,101,W,01,WWWW,0:F_I:::msubf_s
   TRACE_FP_RESULT_FPU1 (&ans);
 }
 
+// FMSF.S
+rrrrr,111111,RRRRR + wwwww,10011100010:F_I:::fmsf_s
+*v850e3v5
+"fmsf.s r<reg1>, r<reg2>, r<reg3>"
+{
+  sim_fpu ans, wop1, wop2, wop3;
+  sim_fpu_status status;
+
+  sim_fpu_32to (&wop1, GR[reg1]);
+  sim_fpu_32to (&wop2, GR[reg2]);
+  sim_fpu_32to (&wop3, GR[reg3]);
+  TRACE_FP_INPUT_FPU3 (&wop1, &wop2, &wop3);
+
+  status = sim_fpu_mul (&ans, &wop1, &wop2);
+  status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
+  wop1 = ans;
+  status |= sim_fpu_sub (&ans, &wop1, &wop3);
+  status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
+
+  update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
+
+  sim_fpu_to32 (&GR[reg3], &ans);
+  TRACE_FP_RESULT_FPU1 (&ans);
+}
+
 // MULF.D
 rrrr,0111111,RRRR,0 + wwww,010001110100:F_I:::mulf_d
 *v850e2v3
+*v850e3v5
 "mulf.d r<reg1e>, r<reg2e>, r<reg3e>"
 {
   sim_fpu ans, wop1, wop2;
@@ -2883,6 +3085,7 @@ rrrr,0111111,RRRR,0 + wwww,010001110100:F_I:::mulf_d
 // MULF.S
 rrrrr,111111,RRRRR + wwwww,10001100100:F_I:::mulf_s
 *v850e2v3
+*v850e3v5
 "mulf.s r<reg1>, r<reg2>, r<reg3>"
 {
   sim_fpu ans, wop1, wop2;
@@ -2904,6 +3107,7 @@ rrrrr,111111,RRRRR + wwwww,10001100100:F_I:::mulf_s
 // NEGF.D
 rrrr,011111100001 + wwww,010001011000:F_I:::negf_d
 *v850e2v3
+*v850e3v5
 "negf.d r<reg2e>, r<reg3e>"
 {
   sim_fpu ans, wop;
@@ -2923,6 +3127,7 @@ rrrr,011111100001 + wwww,010001011000:F_I:::negf_d
 // NEGF.S
 rrrrr,11111100001 + wwwww,10001001000:F_I:::negf_s
 *v850e2v3
+*v850e3v5
 "negf.s r<reg2>, r<reg3>"
 {
   sim_fpu ans, wop;
@@ -2965,6 +3170,32 @@ rrrrr,111111,RRRRR + wwwww,101,W,10,WWWW,0:F_I:::nmaddf_s
   TRACE_FP_RESULT_FPU1 (&ans);
 }
 
+// FNMAF.S
+rrrrr,111111,RRRRR + wwwww,10011100100:F_I:::fnmaf_s
+*v850e3v5
+"fnmaf.s r<reg1>, r<reg2>, r<reg3>"
+{
+  sim_fpu ans, wop1, wop2, wop3;
+  sim_fpu_status status;
+
+  sim_fpu_32to (&wop1, GR[reg1]);
+  sim_fpu_32to (&wop2, GR[reg2]);
+  sim_fpu_32to (&wop3, GR[reg3]);
+  TRACE_FP_INPUT_FPU3 (&wop1, &wop2, &wop3);
+
+  status = sim_fpu_mul (&ans, &wop1, &wop2);
+  wop1 = ans;
+  status |= sim_fpu_add (&ans, &wop1, &wop3);
+  status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
+  wop1 = ans;
+  status |= sim_fpu_neg (&ans, &wop1);
+
+  update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
+
+  sim_fpu_to32 (&GR[reg3], &ans);
+  TRACE_FP_RESULT_FPU1 (&ans);
+}
+
 // NMSUBF.S
 rrrrr,111111,RRRRR + wwwww,101,W,11,WWWW,0:F_I:::nmsubf_s
 *v850e2v3
@@ -2992,9 +3223,37 @@ rrrrr,111111,RRRRR + wwwww,101,W,11,WWWW,0:F_I:::nmsubf_s
   TRACE_FP_RESULT_FPU1 (&ans);
 }
 
+// FNMSF.S
+rrrrr,111111,RRRRR + wwwww,10011100110:F_I:::fnmsf_s
+*v850e3v5
+"fnmsf.s r<reg1>, r<reg2>, r<reg3>"
+{
+  sim_fpu ans, wop1, wop2, wop3;
+  sim_fpu_status status;
+
+  sim_fpu_32to (&wop1, GR[reg1]);
+  sim_fpu_32to (&wop2, GR[reg2]);
+  sim_fpu_32to (&wop3, GR[reg3]);
+  TRACE_FP_INPUT_FPU3 (&wop1, &wop2, &wop3);
+
+  status = sim_fpu_mul (&ans, &wop1, &wop2);
+  status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
+  wop1 = ans;
+  status |= sim_fpu_sub (&ans, &wop1, &wop3);
+  status |= sim_fpu_round_64 (&ans, FPSR_GET_ROUND(), sim_fpu_denorm_underflow_inexact);
+  wop1 = ans;
+  status |= sim_fpu_neg (&ans, &wop1);
+
+  update_fpsr (sd, status, FPSR_XEV | FPSR_XEI | FPSR_XEO | FPSR_XEU, 0);
+
+  sim_fpu_to32 (&GR[reg3], &ans);
+  TRACE_FP_RESULT_FPU1 (&ans);
+}
+
 // RECIPF.D
 rrrr,011111100001 + wwww,010001011110:F_I:::recipf.d
 *v850e2v3
+*v850e3v5
 "recipf.d r<reg2e>, r<reg3e>"
 {
   sim_fpu ans, wop;
@@ -3015,6 +3274,7 @@ rrrr,011111100001 + wwww,010001011110:F_I:::recipf.d
 // RECIPF.S
 rrrrr,11111100001 + wwwww,10001001110:F_I:::recipf.s
 *v850e2v3
+*v850e3v5
 "recipf.s r<reg2>, r<reg3>"
 {
   sim_fpu ans, wop;
@@ -3035,6 +3295,7 @@ rrrrr,11111100001 + wwwww,10001001110:F_I:::recipf.s
 // RSQRTF.D
 rrrr,011111100010 + wwww,010001011110:F_I:::rsqrtf.d
 *v850e2v3
+*v850e3v5
 "rsqrtf.d r<reg2e>, r<reg3e>"
 {
   sim_fpu ans, wop;
@@ -3058,6 +3319,7 @@ rrrr,011111100010 + wwww,010001011110:F_I:::rsqrtf.d
 // RSQRTF.S
 rrrrr,11111100010 + wwwww,10001001110:F_I:::rsqrtf.s
 *v850e2v3
+*v850e3v5
 "rsqrtf.s r<reg2>, r<reg3>"
 {
   sim_fpu ans, wop;
@@ -3081,6 +3343,7 @@ rrrrr,11111100010 + wwwww,10001001110:F_I:::rsqrtf.s
 // SQRTF.D
 rrrr,011111100000 + wwww,010001011110:F_I:::sqrtf.d
 *v850e2v3
+*v850e3v5
 "sqrtf.d r<reg2e>, r<reg3e>"
 {
   sim_fpu ans, wop;
@@ -3101,6 +3364,7 @@ rrrr,011111100000 + wwww,010001011110:F_I:::sqrtf.d
 // SQRTF.S
 rrrrr,11111100000 + wwwww,10001001110:F_I:::sqrtf.s
 *v850e2v3
+*v850e3v5
 "sqrtf.s r<reg2>, r<reg3>"
 {
   sim_fpu ans, wop;
@@ -3121,6 +3385,7 @@ rrrrr,11111100000 + wwwww,10001001110:F_I:::sqrtf.s
 // SUBF.D
 rrrr,0111111,RRRR,0 + wwww,010001110010:F_I:::subf.d
 *v850e2v3
+*v850e3v5
 "subf.d r<reg1e>, r<reg2e>, r<reg3e>"
 {
   sim_fpu ans, wop1, wop2;
@@ -3142,6 +3407,7 @@ rrrr,0111111,RRRR,0 + wwww,010001110010:F_I:::subf.d
 // SUBF.S
 rrrrr,111111,RRRRR + wwwww,10001100010:F_I:::subf.s
 *v850e2v3
+*v850e3v5
 "subf.s r<reg1>, r<reg2>, r<reg3>"
 {
   sim_fpu ans, wop1, wop2;
@@ -3163,6 +3429,7 @@ rrrrr,111111,RRRRR + wwwww,10001100010:F_I:::subf.s
 // TRFSR
 0000011111100000 + 000001000000,bbb,0:F_I:::trfsr
 *v850e2v3
+*v850e3v5
 "trfsr":(bbb == 0)
 "trfsr <bbb>"
 {
@@ -3179,6 +3446,7 @@ rrrrr,111111,RRRRR + wwwww,10001100010:F_I:::subf.s
 // TRNCF.DL
 rrrr,011111100001 + wwww,010001010100:F_I:::trncf_dl
 *v850e2v3
+*v850e3v5
 "trncf.dl r<reg2e>, r<reg3e>"
 {
   signed64 ans;
@@ -3197,12 +3465,35 @@ rrrr,011111100001 + wwww,010001010100:F_I:::trncf_dl
   TRACE_FP_RESULT_WORD2 (GR[reg3e], GR[reg3e+1]);
 }
 
+// TRNCF.DUL
+rrrr,011111110001 + wwww,010001010100:F_I:::trncf_dul
+*v850e2v3
+*v850e3v5
+"trncf.dul r<reg2e>, r<reg3e>"
+{
+  unsigned64 ans;
+  sim_fpu wop;
+  sim_fpu_status status;
+
+  sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]);
+  TRACE_FP_INPUT_FPU1 (&wop);
+
+  status = sim_fpu_to64u (&ans, &wop, sim_fpu_round_zero);
+
+  check_cvt_fi(sd, status, 1);
+
+  GR[reg3e] = ans;
+  GR[reg3e+1] = ans>>32L;
+  TRACE_FP_RESULT_WORD2 (GR[reg3e], GR[reg3e+1]);
+}
+
 // TRNCF.DW
 rrrr,011111100001 + wwwww,10001010000:F_I:::trncf_dw
 *v850e2v3
+*v850e3v5
 "trncf.dw r<reg2e>, r<reg3>"
 {
-  uint32 ans;
+  int32 ans;
   sim_fpu wop;
   sim_fpu_status status;
 
@@ -3217,9 +3508,31 @@ rrrr,011111100001 + wwwww,10001010000:F_I:::trncf_dw
   TRACE_FP_RESULT_WORD1 (ans);
 }
 
+// TRNCF.DUW
+rrrr,011111110001 + wwwww,10001010000:F_I:::trncf_duw
+*v850e2v3
+*v850e3v5
+"trncf.duw r<reg2e>, r<reg3>"
+{
+  uint32 ans;
+  sim_fpu wop;
+  sim_fpu_status status;
+
+  sim_fpu_232to (&wop, GR[reg2e+1], GR[reg2e]);
+  TRACE_FP_INPUT_FPU1 (&wop);
+
+  status = sim_fpu_to32u (&ans, &wop, sim_fpu_round_zero);
+
+  check_cvt_fi(sd, status, 1);
+
+  GR[reg3] = ans;
+  TRACE_FP_RESULT_WORD1 (ans);
+}
+
 // TRNCF.SL
 rrrrr,11111100001 + wwww,010001000100:F_I:::trncf_sl
 *v850e2v3
+*v850e3v5
 "trncf.sl r<reg2>, r<reg3e>"
 {
   signed64 ans;
@@ -3236,12 +3549,33 @@ rrrrr,11111100001 + wwww,010001000100:F_I:::trncf_sl
   TRACE_FP_RESULT_WORD2 (GR[reg3e], GR[reg3e+1]);
 }
 
+// TRNCF.SUL
+rrrrr,11111110001 + wwww,010001000100:F_I:::trncf_sul
+*v850e2v3
+*v850e3v5
+"trncf.sul r<reg2>, r<reg3e>"
+{
+  unsigned64 ans;
+  sim_fpu wop;
+  sim_fpu_status status;
+
+  sim_fpu_32to (&wop, GR[reg2]);
+  TRACE_FP_INPUT_FPU1 (&wop);
+
+  status = sim_fpu_to64u (&ans, &wop, sim_fpu_round_zero);
+
+  GR[reg3e] = ans;
+  GR[reg3e+1] = ans >> 32L;
+  TRACE_FP_RESULT_WORD2 (GR[reg3e], GR[reg3e+1]);
+}
+
 // TRNCF.SW
 rrrrr,11111100001 + wwwww,10001000000:F_I:::trncf_sw
 *v850e2v3
+*v850e3v5
 "trncf.sw r<reg2>, r<reg3>"
 {
-  uint32 ans;
+  int32 ans;
   sim_fpu wop;
   sim_fpu_status status;
 
@@ -3255,3 +3589,754 @@ rrrrr,11111100001 + wwwww,10001000000:F_I:::trncf_sw
   GR[reg3] = ans;
   TRACE_FP_RESULT_WORD1 (ans);
 }
+
+// TRNCF.SUW
+rrrrr,11111110001 + wwwww,10001000000:F_I:::trncf_suw
+*v850e2v3
+*v850e3v5
+"trncf.suw r<reg2>, r<reg3>"
+{
+  uint32 ans;
+  sim_fpu wop;
+  sim_fpu_status status;
+
+  sim_fpu_32to (&wop, GR[reg2]);
+  TRACE_FP_INPUT_FPU1 (&wop);
+
+  status = sim_fpu_to32u (&ans, &wop, sim_fpu_round_zero);
+
+  check_cvt_fi(sd, status, 0);
+
+  GR[reg3] = ans;
+  TRACE_FP_RESULT_WORD1 (ans);
+}
+
+// ROTL
+rrrrr,111111,iiiii+wwwww,00011000100:VII:::rotl_imm
+*v850e3v5
+"rotl imm5, r<reg2>, r<reg3>"
+{
+  TRACE_ALU_INPUT1 (GR[reg2]);
+  v850_rotl (sd, imm5, GR[reg2], & GR[reg3]);
+  TRACE_ALU_RESULT1 (GR[reg3]);
+}
+
+rrrrr,111111,RRRRR+wwwww,00011000110:VII:::rotl
+*v850e3v5
+"rotl r<reg1>, r<reg2>, r<reg3>"
+{
+  TRACE_ALU_INPUT2 (GR[reg1], GR[reg2]);
+  v850_rotl (sd, GR[reg1], GR[reg2], & GR[reg3]);
+  TRACE_ALU_RESULT1 (GR[reg3]);
+}
+
+// BINS
+rrrrr,111111,RRRRR+bbbb,B,0001001,BBB,0:IX:::bins_top
+*v850e3v5
+"bins r<reg1>, <bit13> + 16, <bit4> - <bit13> + 17, r<reg2>"
+{
+  TRACE_ALU_INPUT1 (GR[reg1]);
+  v850_bins (sd, GR[reg1], bit13 + 16, bit4 + 16, & GR[reg2]);
+  TRACE_ALU_RESULT1 (GR[reg2]);
+}
+
+rrrrr,111111,RRRRR+bbbb,B,0001011,BBB,0:IX:::bins_middle
+*v850e3v5
+"bins r<reg1>, <bit13>, <bit4> - <bit13> + 17, r<reg2>"
+{
+  TRACE_ALU_INPUT1 (GR[reg1]);
+  v850_bins (sd, GR[reg1], bit13, bit4 + 16, & GR[reg2]);
+  TRACE_ALU_RESULT1 (GR[reg2]);
+}
+
+rrrrr,111111,RRRRR+bbbb,B,0001101,BBB,0:IX:::bins_bottom
+*v850e3v5
+"bins r<reg1>, <bit13>, <bit4> - <bit13> + 1, r<reg2>"
+{
+  TRACE_ALU_INPUT1 (GR[reg1]);
+  v850_bins (sd, GR[reg1], bit13, bit4, & GR[reg2]);
+  TRACE_ALU_RESULT1 (GR[reg2]);
+}
+
+vvvvv,11111100100+xxxxx,11001111110:C:::cnvq15q30
+*v850e3v5
+"cnvq15q30 v<vreg2>, v<vreg3>"
+{
+  reg64_t v;
+
+  TRACE_ALU_INPUT1 (VR[vreg2]);
+
+  if (VR[vreg2] & (1 << 15))
+    v = 0x0001ffffffff0000 | VR[vreg2];
+  else
+    v = VR[vreg2];
+  VR[vreg3] = v << 15;
+
+  TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,11111100110+xxxxx,11001111110:C:::cnvq30q15
+*v850e3v5
+"cnvq30q15 v<vreg2>, v<vreg3>"
+{
+  reg64_t v;
+
+  TRACE_ALU_INPUT1 (VR[vreg2]);
+
+  v = ROUND_Q62_Q15 (VR[vreg2]);
+  SAT16 (v);
+  VR[vreg3] &= 0xffffffffffff0000UL;
+  v         &=             0xffffUL;
+  VR[vreg3] |= v;
+
+  TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,11111100101+xxxxx,11001111110:C:::cnvq31q62
+*v850e3v5
+"cnvq31q62 v<vreg2>, v<vreg3>"
+{
+  reg64_t v;
+
+  TRACE_ALU_INPUT1 (VR[vreg2]);
+
+  if (VR[vreg2] & (1 << 31))
+    v = 0xffffffff00000000 | VR[vreg2];
+  else
+    v = VR[vreg2];
+  VR[vreg3] = v << 31;
+
+  TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,11111100111+xxxxx,11001111110:C:::cnvq62q31
+*v850e3v5
+"cnvq62q31 v<vreg2>, v<vreg3>"
+{
+  reg64_t v;
+
+  TRACE_ALU_INPUT1 (VR[vreg2]);
+
+  v = ROUND_Q62_Q31 (VR[vreg2]);
+  SAT32 (v);
+  VR[vreg3] &= 0xffffffff00000000UL;
+  v         &=         0xffffffffUL;
+  VR[vreg3] |= v;
+
+  TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,111111100,ii+xxxxx,11011011100:C:::dup.h
+*v850e3v5
+"dup.h <imm2> v<vreg2>, v<vreg3>"
+{
+  reg64_t v;
+
+  TRACE_ALU_INPUT1 (VR[vreg2]);
+  switch (imm2)
+    {
+    case 0: v = VR[vreg2] & 0xffff; break;
+    case 1: v = (VR[vreg2] >> 16) & 0xffff; break;
+    case 2: v = (VR[vreg2] >> 32) & 0xffff; break;
+    case 3: v = (VR[vreg2] >> 48) & 0xffff; break;
+    default:
+      sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
+      v = 0;
+    }
+
+  VR[vreg3] = v | (v << 16) | (v << 32) | (v << 48);
+  TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,1111111100,i+xxxxx,11011011110:C:::dup.w
+*v850e3v5
+"dup.w <imm1> v<vreg2>, v<vreg3>"
+{
+  reg64_t v;
+
+  TRACE_ALU_INPUT1 (VR[vreg2]);
+  switch (imm1)
+    {
+    case 0: v = VR[vreg2] & 0xffffffff; break;
+    case 1: v = (VR[vreg2] >> 32) & 0xffffffff; break;
+    default:
+      sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
+      v = 0;
+    }
+
+  VR[vreg3] = v | (v << 32);
+  TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,11111101000+xxxxx,11001111110:C:::expq31
+*v850e3v5
+"expq31 v<vreg2>, v<vreg3>"
+{
+  int i;
+  reg64_t v;
+
+  TRACE_ALU_INPUT1 (VR[vreg2]);
+  v = VR[vreg2] & 0xffffffff;
+  if (v & (1 << 31))
+    {
+      if (v == 0x80000000)
+        i = 31;
+      else if (v == 0xffffffff)
+        i = 0;
+      else
+        for (i = 31; i; --i)
+          if ((v & (1 << i)) == 0)
+            break;
+    }
+  else
+    {
+      if (v == 0x7fffffff)
+        i = 31;
+      else if (v == 0x0)
+        i = 0;
+      else
+        for (i = 31; i; --i)
+          if (v & (1 << i))
+            break;
+    }
+  VR[vreg3] = 31 - i;
+  TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+rrrr,011111100000+0000011011011000:C:::modadd
+*v850e3v5
+"modadd r<reg2e>"
+{
+  reg_t r;
+  int32 inc;
+  reg_t max;
+
+  TRACE_ALU_INPUT1 (GR[reg2e]);
+  r = GR[reg2e];
+  inc = r >> 16;
+  r = r & 0xffff;
+  max = GR[reg2e + 1];
+  max &= 0xffff;
+  r += inc;
+  if (inc > 0 && r > max)
+    r = 0;
+  else if (inc < 0 && r < 0)
+    r = max;
+  GR[reg2e] = (r & 0xffff) | (inc << 16);
+  TRACE_ALU_RESULT1 (GR[reg2e]);
+}
+
+vvvvv,11111111000+wwwww,11011011010:C:::mov_dw_to_gr
+*v850e3v5
+"mov.dw v<vreg2>, r<reg3>"
+{
+  TRACE_ALU_INPUT1 (VR[vreg2]);
+  GR[reg3] = VR[vreg2] & 0xffffffff;
+  GR[reg3 + 1] = VR[vreg2] >> 32;
+  TRACE_ALU_RESULT2 (GR[reg3], GR[reg3 + 1]);
+}
+
+rrrrr,11111111100+xxxxx,11011011010:C:::mov_dw_to_vr
+*v850e3v5
+"mov.dw r<reg2>, v<vreg3>"
+{
+  TRACE_ALU_INPUT2 (GR[reg2], GR[reg2 + 1]);
+  VR[vreg3] = GR[reg2 + 1];
+  VR[vreg3] <<= 32;
+  VR[vreg3] |= GR[reg2];
+  TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,111111000,ii+xxxxx,11011011100:C:::mov.h
+*v850e3v5
+"mov.h <imm2> v<vreg2>, v<vreg3>"
+{
+  reg64_t v = VR[vreg2];
+  reg64_t mask = 0xffffUL;
+  int shift;
+
+  TRACE_ALU_INPUT1 (VR[vreg2]);
+
+  switch (imm2)
+    {
+    default:
+      sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
+    case 0: shift = 0; break;
+    case 1: shift = 16; break;
+    case 2: shift = 32; break;
+    case 3: shift = 48; break;
+    }
+
+  v         &= mask;  
+  VR[vreg3] &= ~ (mask << shift);
+  VR[vreg3] |= (v << shift);
+    
+  TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,1111110000,i+xxxxx,11011011010:C:::mov.w.vreg_to_vreg
+*v850e3v5
+"mov.w <imm1> v<vreg2>, v<vreg3>"
+{
+  reg64_t v = VR[vreg2];
+  reg64_t mask = 0xffffffffUL;
+  int shift;
+
+  TRACE_ALU_INPUT1 (VR[vreg2]);
+  switch (imm1)
+    {
+    default:
+      sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
+    case 0: shift = 0; break;
+    case 1: shift = 32; break;
+    }
+
+  v         &= mask;
+  VR[vreg3] &= ~ (mask << shift);
+  VR[vreg3] |= (v << shift);
+    
+  TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+rrrrr,1111111000,i+xxxxx,11011011010:C:::mov.w.reg_to_vreg
+*v850e3v5
+"mov.w <imm1> r<reg2>, v<vreg3>"
+{
+  reg64_t v;
+  reg64_t mask = 0xffffffffUL;
+  int shift;
+
+  TRACE_ALU_INPUT1 (GR[reg2]);
+  switch (imm1)
+    {
+    default:
+      sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
+    case 0: shift = 0; break;
+    case 1: shift = 32; break;
+    }
+
+  v          = GR[reg2];
+  VR[vreg3] &= ~ (mask << shift);
+  VR[vreg3] |= (v << shift);
+    
+  TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,1111110100,i+wwwww,11011011010:C:::mov.w.vreg_to_reg
+*v850e3v5
+"mov.w <imm1> v<vreg2>, r<reg3>"
+{
+  TRACE_ALU_INPUT1 (VR[vreg2]);
+
+  switch (imm1)
+    {
+    default:
+      sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
+    case 0:
+      GR[reg3] = VR[vreg2];
+      break;
+    case 1:
+      GR[reg3] = VR[vreg2] >> 32;
+      break;
+    }
+    
+  TRACE_ALU_RESULT1 (GR[reg3]);
+}
+
+vvvvv,111111,VVVVV+xxxxx,11001101010:C:::pki16i32
+*v850e3v5
+"pki16i32 v<vreg1>, v<vreg2>, v<vreg3>"
+{
+  reg64_t v,t;
+
+  TRACE_ALU_INPUT1 (VR[vreg1]);
+
+  v = VR[vreg1];
+  VR[vreg2] = (SEXT32 (v, 16) & 0xffffffff);
+  v >>= 16;
+  t = SEXT32 (v, 16);
+  VR[vreg2] |= t << 32;
+  
+  v >>= 16;
+  VR[vreg3] = (SEXT32 (v, 16) & 0xffffffff);
+  v >>= 16;
+  t = SEXT32 (v, 16);
+  VR[vreg3] |= t << 32;
+
+  TRACE_ALU_RESULT2 (VR[vreg2], VR[vreg3]);
+}
+
+vvvvv,111111,VVVVV+xxxxx,11001100110:C:::pki16ui8
+*v850e3v5
+"pki16ui8 v<vreg1>, v<vreg2>, v<vreg3>"
+{
+  TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
+
+  VR[vreg3] = VR[vreg1] & 0xff;
+  VR[vreg3] |= ((VR[vreg1] >>  8) & 0xff00);
+  VR[vreg3] |= ((VR[vreg1] >> 16) & 0xff0000);
+  VR[vreg3] |= ((VR[vreg1] >> 24) & 0xff000000);
+
+  VR[vreg3] |= ((VR[vreg2] << 32) & 0xff00000000UL);
+  VR[vreg3] |= ((VR[vreg2] << 24) & 0xff0000000000UL);
+  VR[vreg3] |= ((VR[vreg2] << 16) & 0xff000000000000UL);
+  VR[vreg3] |= ((VR[vreg2] <<  8) & 0xff00000000000000UL);
+    
+  TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,111111,VVVVV+xxxxx,11001100100:C:::pki32i16
+*v850e3v5
+"pki32i16 v<vreg1>, v<vreg2>, v<vreg3>"
+{
+  reg64_t v;
+
+  TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
+
+  v = VR[vreg1] & 0xffffffff;
+  SAT16 (v);
+  VR[vreg3] = v & 0xffff;
+
+  v = VR[vreg1] >> 32;
+  SAT16 (v);
+  VR[vreg3] |= ((v & 0xffff) << 16);
+  
+  v = VR[vreg2] & 0xffffffff;
+  SAT16 (v);
+  VR[vreg3] = ((v & 0xffff) << 32);
+
+  v = VR[vreg2] >> 32;
+  SAT16 (v);
+  VR[vreg3] |= ((v & 0xffff) << 48);
+  
+  TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,111111,VVVVV+xxxxx,11001100010:C:::pki64i32
+*v850e3v5
+"pki64i32 v<vreg1>, v<vreg2>, v<vreg3>"
+{
+  reg64_t v;
+
+  TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
+
+  v = VR[vreg1];
+  SAT32 (v);
+  VR[vreg3] = v & 0xffffffff;
+
+  v = VR[vreg2];
+  SAT32 (v);
+  VR[vreg3] |= v << 32;
+  
+  TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,111111,VVVVV+xxxxx,11001101000:C:::pkq15q31
+*v850e3v5
+"pkq15q31 v<vreg1>, v<vreg2>, v<vreg3>"
+{
+  reg64_t v;
+
+  TRACE_ALU_INPUT1 (VR[vreg1]);
+
+  v = VR[vreg1];
+  VR[vreg2] = ((v & 0xffff) << 16);
+  VR[vreg2] |= ((v & 0xffff0000) << 32);
+
+  VR[vreg3] = ((v & 0xffff00000000UL) >> 16);
+  VR[vreg3] |= ((v & 0xffff000000000000UL));
+
+  TRACE_ALU_RESULT2 (VR[vreg2], VR[vreg3]);
+}
+
+vvvvv,111111,VVVVV+xxxxx,11001011110:C:::pkq30q31
+*v850e3v5
+"pkq30q31 v<vreg1>, v<vreg2>, v<vreg3>"
+{
+  reg64_t v;
+
+  TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
+
+  v = VR[vreg1];
+  v <<= 1;
+  SAT32 (v);
+  VR[vreg3] = v & 0xffffffff;
+
+  v = VR[vreg2];
+  v <<= 1;
+  SAT32 (v);
+  VR[vreg3] = v << 32;
+    
+  TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,111111,VVVVV+xxxxx,11001100000:C:::pkq31q15
+*v850e3v5
+"pkq31q15 v<vreg1>, v<vreg2>, v<vreg3>"
+{
+  reg64_t v;
+
+  TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
+    
+  v = ROUND_Q31_Q15 (VR[vreg1] & 0xffffffff);
+  SAT16 (v);
+  VR[vreg3] = v & 0xffff;
+
+  v = ROUND_Q31_Q15 (VR[vreg1] >> 32);
+  SAT16 (v);
+  VR[vreg3] |= (v & 0xffff) << 16;
+
+  v = ROUND_Q31_Q15 (VR[vreg2] & 0xffffffff);
+  SAT16 (v);
+  VR[vreg3] |= (v & 0xffff) << 32;
+
+  v = ROUND_Q31_Q15 (VR[vreg2] >> 32);
+  SAT16 (v);
+  VR[vreg3] |= (v & 0xffff) << 48;
+      
+  TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,111111,VVVVV+xxxxx,11001101100:C:::pkui8i16
+*v850e3v5
+"pkui8i16 v<vreg1>, v<vreg2>, v<vreg3>"
+{
+  reg64_t v;
+
+  TRACE_ALU_INPUT1 (VR[vreg1]);
+
+  v = VR[vreg1];
+
+  VR[vreg2] = v & 0x00ff;
+  VR[vreg2] |= (v << 8)  & 0x00ff0000;
+  VR[vreg2] |= (v << 16) & 0x00ff00000000UL;
+  VR[vreg2] |= (v << 24) & 0x00ff000000000000UL;
+
+  VR[vreg3]  = (v >> 32) & 0x00ff;
+  VR[vreg3] |= (v >> 24) & 0x00ff0000;
+  VR[vreg3] |= (v >> 16) & 0x00ff00000000UL;
+  VR[vreg3] |= (v >>  8) & 0x00ff000000000000UL;
+        
+  TRACE_ALU_RESULT2 (VR[vreg2], VR[vreg3]);
+}
+
+vvvvv,11111100000+xxxxx,11001111110:C:::vabs.h
+*v850e3v5
+"vabs.h v<vreg2>, v<vreg3>"
+{
+  int shift;
+
+  TRACE_ALU_INPUT1 (VR[vreg2]);
+
+  VR[vreg3] = 0;
+  for (shift = 0; shift < 64; shift += 16);
+    {
+      reg64_t v;
+
+      v = VR[vreg2] >> shift;
+      ABS16 (v);
+      VR[vreg3] |= v << shift;
+    }
+  
+  TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,11111100001+xxxxx,11001111110:C:::vabs.w
+*v850e3v5
+"vabs.w v<vreg2>, v<vreg3>"
+{
+  reg64_t v;
+
+  TRACE_ALU_INPUT1 (VR[vreg2]);
+
+  v = VR[vreg2];
+  ABS32 (v);
+  VR[vreg3] = v;
+
+  v = VR[vreg2] >> 32;
+  ABS32 (v);
+  VR[vreg3] |= v << 32;
+  
+  TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,111111,VVVVV+xxxxx,11001011000:C:::vadd.dw
+*v850e3v5
+"vadd.dw v<vreg1>, v<vreg2>, v<vreg3>"
+{
+  TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
+
+  /* FIXME: saturation handling needed.  */
+  sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
+
+  VR[vreg3] = VR[vreg1] + VR[vreg2];
+  
+  TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+ 
+vvvvv,111111,VVVVV+xxxxx,11000000000:C:::vadd.h
+*v850e3v5
+"vadd.h v<vreg1>, v<vreg2>, v<vreg3>"
+{
+  TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
+
+  /* FIXME: Implementation needed.  */
+  sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
+
+  TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,111111,VVVVV+xxxxx,11000000010:C:::vadd.w
+*v850e3v5
+"vadd.w v<vreg1>, v<vreg2>, v<vreg3>"
+{
+  TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
+
+  /* FIXME: Implementation needed.  */
+  sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
+
+  TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,111111,VVVVV+xxxxx,11000001000:C:::vadds.h
+*v850e3v5
+"vadds.h v<vreg1>, v<vreg2>, v<vreg3>"
+{
+  TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
+
+  /* FIXME: Implementation needed.  */
+  sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
+
+  TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,111111,VVVVV+xxxxx,11000001010:C:::vadds.w
+*v850e3v5
+"vadds.w v<vreg1>, v<vreg2>, v<vreg3>"
+{
+  TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
+
+  /* FIXME: Implementation needed.  */
+  sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
+
+  TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,111111,VVVVV+xxxxx,11000010000:C:::vaddsat.h
+*v850e3v5
+"vaddsat.h v<vreg1>, v<vreg2>, v<vreg3>"
+{
+  TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
+
+  /* FIXME: Implementation needed.  */
+  sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
+
+  TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,111111,VVVVV+xxxxx,11000010010:C:::vaddsat.w
+*v850e3v5
+"vaddsat.w v<vreg1>, v<vreg2>, v<vreg3>"
+{
+  TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
+
+  /* FIXME: Implementation needed.  */
+  sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
+
+  TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,111111,VVVVV+xxxxx,11010000000:C:::vand
+*v850e3v5
+"vand v<vreg1>, v<vreg2>, v<vreg3>"
+{
+  TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
+
+  VR[vreg3] = VR[vreg1] & VR[vreg2];
+
+  TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,111111,VVVVV+xxxxx,11001011100:C:::vbiq.h
+*v850e3v5
+"vbiq.h v<vreg1>, v<vreg2>, v<vreg3>"
+{
+  TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
+
+  /* FIXME: Implementation needed.  */
+  sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
+
+  TRACE_ALU_RESULT2 (VR[vreg2], VR[vreg3]);
+}
+
+vvvvv,11111100111+xxxxx,11011011110:C:::vbswap.dw
+*v850e3v5
+"vbswap.dw v<vreg2>, v<vreg3>"
+{
+  TRACE_ALU_INPUT1 (VR[vreg2]);
+
+  /* FIXME: Implementation needed.  */
+  sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
+
+  TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,11111100101+xxxxx,11011011110:C:::vbswap.h
+*v850e3v5
+"vbswap.h v<vreg2>, v<vreg3>"
+{
+  TRACE_ALU_INPUT1 (VR[vreg2]);
+
+  /* FIXME: Implementation needed.  */
+  sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
+
+  TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,11111100110+xxxxx,11011011110:C:::vbswap.w
+*v850e3v5
+"vbswap.w v<vreg2>, v<vreg3>"
+{
+  TRACE_ALU_INPUT1 (VR[vreg2]);
+
+  /* FIXME: Implementation needed.  */
+  sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
+
+  TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,111111,VVVVV+xxxxx,11001110000:C:::vcalc.h
+*v850e3v5
+"vcalc.h v<vreg1>,v<vreg2>, v<vreg3>"
+{
+  TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
+
+  /* FIXME: Implementation needed.  */
+  sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
+
+  TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,111111,VVVVV+xxxxx,11001110010:C:::vcalc.w
+*v850e3v5
+"vcalc.w v<vreg1>,v<vreg2>, v<vreg3>"
+{
+  TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
+
+  /* FIXME: Implementation needed.  */
+  sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
+
+  TRACE_ALU_RESULT1 (VR[vreg3]);
+}
+
+vvvvv,111111,VVVVV+xxxxx,11010110000:C:::vcmov
+*v850e3v5
+"vcmov v<vreg1>, v<vreg2>, v<vreg3>"
+{
+  TRACE_ALU_INPUT2 (VR[vreg1], VR[vreg2]);
+
+  /* FIXME: Implementation needed.  */
+  sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
+
+  TRACE_ALU_RESULT1 (VR[vreg3]);
+}