X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;ds=sidebyside;f=opcodes%2Fi386-opc.h;h=aa080cfe3615ff9cdbaaf15eba762e818cb75d3e;hb=268e4f09144c48e02f01d82ab3aab359457df214;hp=ebf446f42d64d28b2f1f577b42f187978e900be6;hpb=5d79adc4b22b0abd4f12ea973a00e7fb0c1dad64;p=deliverable%2Fbinutils-gdb.git

diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index ebf446f42d..aa080cfe36 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -208,6 +208,8 @@ enum
   CpuAVX512_BITALG,
   /* Intel AVX-512 BF16 Instructions support required.  */
   CpuAVX512_BF16,
+  /* Intel AVX-512 VP2INTERSECT Instructions support required.  */
+  CpuAVX512_VP2INTERSECT,
   /* mwaitx instruction required */
   CpuMWAITX,
   /* Clzero instruction required */
@@ -241,6 +243,10 @@ enum
   CpuMOVDIR64B,
   /* ENQCMD instruction required */
   CpuENQCMD,
+  /* RDPRU instruction required */
+  CpuRDPRU,
+  /* MCOMMIT instruction required */
+  CpuMCOMMIT,
   /* 64bit support required  */
   Cpu64,
   /* Not supported in the 64bit mode  */
@@ -352,6 +358,7 @@ typedef union i386_cpu_flags
       unsigned int cpuavx512_vnni:1;
       unsigned int cpuavx512_bitalg:1;
       unsigned int cpuavx512_bf16:1;
+      unsigned int cpuavx512_vp2intersect:1;
       unsigned int cpumwaitx:1;
       unsigned int cpuclzero:1;
       unsigned int cpuospke:1;
@@ -369,6 +376,8 @@ typedef union i386_cpu_flags
       unsigned int cpumovdiri:1;
       unsigned int cpumovdir64b:1;
       unsigned int cpuenqcmd:1;
+      unsigned int cpurdpru:1;
+      unsigned int cpumcommit:1;
       unsigned int cpu64:1;
       unsigned int cpuno64:1;
 #ifdef CpuUnused
@@ -384,7 +393,9 @@ enum
 {
   /* has direction bit. */
   D = 0,
-  /* set if operands can be words or dwords encoded the canonical way */
+  /* set if operands can be both bytes and words/dwords/qwords, encoded the
+     canonical way; the base_opcode field should hold the encoding for byte
+     operands  */
   W,
   /* load form instruction. Must be placed before store form.  */
   Load,
@@ -392,14 +403,17 @@ enum
   Modrm,
   /* register is in low 3 bits of opcode */
   ShortForm,
-  /* special case for jump insns.  */
-  Jump,
+  /* special case for jump insns; value has to be 1 */
+#define JUMP 1
   /* call and jump */
-  JumpDword,
+#define JUMP_DWORD 2
   /* loop and jecxz */
-  JumpByte,
+#define JUMP_BYTE 3
   /* special case for intersegment leaps/calls */
-  JumpInterSegment,
+#define JUMP_INTERSEGMENT 4
+  /* absolute address for jump */
+#define JUMP_ABSOLUTE 5
+  Jump,
   /* FP insn memory format bit, sized by 0x4 */
   FloatMF,
   /* src/dest swap for floats. */
@@ -418,6 +432,8 @@ enum
   IgnoreSize,
   /* default insn size depends on mode */
   DefaultSize,
+  /* any memory size */
+  Anysize,
   /* b suffix on instruction illegal */
   No_bSuf,
   /* w suffix on instruction illegal */
@@ -432,8 +448,17 @@ enum
   No_ldSuf,
   /* instruction needs FWAIT */
   FWait,
-  /* quick test for string instructions */
+  /* IsString provides for a quick test for string instructions, and
+     its actual value also indicates which of the operands (if any)
+     requires use of the %es segment.  */
+#define IS_STRING_ES_OP0 2
+#define IS_STRING_ES_OP1 3
   IsString,
+  /* RegMem is for instructions with a modrm byte where the register
+     destination operand should be encoded in the mod and regmem fields.
+     Normally, it will be encoded in the reg field. We add a RegMem
+     flag to indicate that it should be encoded in the regmem field.  */
+  RegMem,
   /* quick test if branch instruction is MPX supported */
   BNDPrefixOk,
   /* quick test if NOTRACK prefix is supported */
@@ -618,7 +643,7 @@ enum
   /* Intel64.  */
   Intel64,
   /* The last bitfield in i386_opcode_modifier.  */
-  Opcode_Modifier_Max
+  Opcode_Modifier_Num
 };
 
 typedef struct i386_opcode_modifier
@@ -628,16 +653,14 @@ typedef struct i386_opcode_modifier
   unsigned int load:1;
   unsigned int modrm:1;
   unsigned int shortform:1;
-  unsigned int jump:1;
-  unsigned int jumpdword:1;
-  unsigned int jumpbyte:1;
-  unsigned int jumpintersegment:1;
+  unsigned int jump:3;
   unsigned int floatmf:1;
   unsigned int floatr:1;
   unsigned int size:2;
   unsigned int checkregsize:1;
   unsigned int ignoresize:1;
   unsigned int defaultsize:1;
+  unsigned int anysize:1;
   unsigned int no_bsuf:1;
   unsigned int no_wsuf:1;
   unsigned int no_lsuf:1;
@@ -645,7 +668,8 @@ typedef struct i386_opcode_modifier
   unsigned int no_qsuf:1;
   unsigned int no_ldsuf:1;
   unsigned int fwait:1;
-  unsigned int isstring:1;
+  unsigned int isstring:2;
+  unsigned int regmem:1;
   unsigned int bndprefixok:1;
   unsigned int notrackprefixok:1;
   unsigned int islockable:1;
@@ -685,28 +709,41 @@ typedef struct i386_opcode_modifier
   unsigned int intel64:1;
 } i386_opcode_modifier;
 
+/* Operand classes.  */
+
+#define CLASS_WIDTH 4
+enum operand_class
+{
+  ClassNone,
+  Reg, /* GPRs and FP regs, distinguished by operand size */
+  SReg, /* Segment register */
+  RegCR, /* Control register */
+  RegDR, /* Debug register */
+  RegTR, /* Test register */
+  RegMMX, /* MMX register */
+  RegSIMD, /* XMM/YMM/ZMM registers, distinguished by operand size */
+  RegMask, /* Vector Mask register */
+  RegBND, /* Bound register */
+};
+
+/* Special operand instances.  */
+
+#define INSTANCE_WIDTH 3
+enum operand_instance
+{
+  InstanceNone,
+  Accum, /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
+  RegC,  /* %cl / %cx / %ecx / %rcx, e.g. register to hold shift count */
+  RegD,  /* %dl / %dx / %edx / %rdx, e.g. register to hold I/O port addr */
+  RegB,  /* %bl / %bx / %ebx / %rbx */
+};
+
 /* Position of operand_type bits.  */
 
 enum
 {
-  /* Register (qualified by Byte, Word, etc) */
-  Reg = 0,
-  /* MMX register */
-  RegMMX,
-  /* Vector registers */
-  RegSIMD,
-  /* Vector Mask registers */
-  RegMask,
-  /* Control register */
-  Control,
-  /* Debug register */
-  Debug,
-  /* Test register */
-  Test,
-  /* 2 bit segment register */
-  SReg2,
-  /* 3 bit segment register */
-  SReg3,
+  /* Class and Instance */
+  ClassInstance = CLASS_WIDTH + INSTANCE_WIDTH - 1,
   /* 1 bit immediate */
   Imm1,
   /* 8 bit immediate */
@@ -738,26 +775,8 @@ enum
   Disp32S,
   /* 64 bit displacement */
   Disp64,
-  /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
-  Acc,
   /* Register which can be used for base or index in memory operand.  */
   BaseIndex,
-  /* Register to hold in/out port addr = dx */
-  InOutPortReg,
-  /* Register to hold shift count = cl */
-  ShiftCount,
-  /* Absolute address for jump.  */
-  JumpAbsolute,
-  /* String insn operand with fixed es segment */
-  EsSeg,
-  /* RegMem is for instructions with a modrm byte where the register
-     destination operand should be encoded in the mod and regmem fields.
-     Normally, it will be encoded in the reg field. We add a RegMem
-     flag to the destination register operand to indicate that it should
-     be encoded in the regmem field.  */
-  RegMem,
-  /* Memory.  */
-  Mem,
   /* BYTE size. */
   Byte,
   /* WORD size. 2 byte */
@@ -778,16 +797,8 @@ enum
   Zmmword,
   /* Unspecified memory size.  */
   Unspecified,
-  /* Any memory size.  */
-  Anysize,
 
-  /* Vector 4 bit immediate.  */
-  Vec_Imm4,
-
-  /* Bound register.  */
-  RegBND,
-
-  /* The number of bitfields in i386_operand_type.  */
+  /* The number of bits in i386_operand_type.  */
   OTNum
 };
 
@@ -804,15 +815,8 @@ typedef union i386_operand_type
 {
   struct
     {
-      unsigned int reg:1;
-      unsigned int regmmx:1;
-      unsigned int regsimd:1;
-      unsigned int regmask:1;
-      unsigned int control:1;
-      unsigned int debug:1;
-      unsigned int test:1;
-      unsigned int sreg2:1;
-      unsigned int sreg3:1;
+      unsigned int class:CLASS_WIDTH;
+      unsigned int instance:INSTANCE_WIDTH;
       unsigned int imm1:1;
       unsigned int imm8:1;
       unsigned int imm8s:1;
@@ -825,13 +829,7 @@ typedef union i386_operand_type
       unsigned int disp32:1;
       unsigned int disp32s:1;
       unsigned int disp64:1;
-      unsigned int acc:1;
       unsigned int baseindex:1;
-      unsigned int inoutportreg:1;
-      unsigned int shiftcount:1;
-      unsigned int jumpabsolute:1;
-      unsigned int esseg:1;
-      unsigned int regmem:1;
       unsigned int byte:1;
       unsigned int word:1;
       unsigned int dword:1;
@@ -842,9 +840,6 @@ typedef union i386_operand_type
       unsigned int ymmword:1;
       unsigned int zmmword:1;
       unsigned int unspecified:1;
-      unsigned int anysize:1;
-      unsigned int vec_imm4:1;
-      unsigned int regbnd:1;
 #ifdef OTUnused
       unsigned int unused:(OTNumOfBits - OTUnused);
 #endif
@@ -857,9 +852,6 @@ typedef struct insn_template
   /* instruction name sans width suffix ("mov" for movl insns) */
   char *name;
 
-  /* how many operands */
-  unsigned int operands;
-
   /* base_opcode is the fundamental opcode byte without optional
      prefix(es).  */
   unsigned int base_opcode;
@@ -876,12 +868,15 @@ typedef struct insn_template
      AMD 3DNow! instructions.
      If this template has no extension opcode (the usual case) use None
      Instructions */
-  unsigned int extension_opcode;
+  unsigned short extension_opcode;
 #define None 0xffff		/* If no extension_opcode is possible.  */
 
   /* Opcode length.  */
   unsigned char opcode_length;
 
+  /* how many operands */
+  unsigned char operands;
+
   /* cpu feature flags */
   i386_cpu_flags cpu_flags;