X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;ds=sidebyside;f=opcodes%2Frx-decode.opc;h=59d4338400e88f466b1c0a75f2271414015234b7;hb=036003a671233c43e35b3004f91e4cbd61255cf3;hp=b28ea8cf2d055ca9a31be6deeb47820cc89db4ba;hpb=78e98aaba5b8ece23f0cbb1a6baa0f3b1891b275;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/rx-decode.opc b/opcodes/rx-decode.opc index b28ea8cf2d..59d4338400 100644 --- a/opcodes/rx-decode.opc +++ b/opcodes/rx-decode.opc @@ -1,11 +1,32 @@ /* -*- c -*- */ +/* Copyright (C) 2012-2019 Free Software Foundation, Inc. + Contributed by Red Hat. + Written by DJ Delorie. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "sysdep.h" #include #include #include - -#include "config.h" #include "ansidecl.h" #include "opcode/rx.h" +#include "libiberty.h" #define RX_OPCODE_BIG_ENDIAN 0 @@ -22,30 +43,34 @@ static int trace = 0; #define BSIZE 0 #define WSIZE 1 #define LSIZE 2 +#define DSIZE 3 /* These are for when the upper bits are "don't care" or "undefined". */ -static int bwl[] = +static int bwl[4] = { RX_Byte, RX_Word, - RX_Long + RX_Long, + RX_Bad_Size /* Bogus instructions can have a size field set to 3. */ }; -static int sbwl[] = +static int sbwl[4] = { RX_SByte, RX_SWord, - RX_Long + RX_Long, + RX_Bad_Size /* Bogus instructions can have a size field set to 3. */ }; -static int ubwl[] = +static int ubw[4] = { RX_UByte, RX_UWord, - RX_Long + RX_Bad_Size,/* Bogus instructions can have a size field set to 2. */ + RX_Bad_Size /* Bogus instructions can have a size field set to 3. */ }; -static int memex[] = +static int memex[4] = { RX_SByte, RX_SWord, @@ -53,6 +78,12 @@ static int memex[] = RX_UWord }; +static int _ld[2] = +{ + RX_Long, + RX_Double +}; + #define ID(x) rx->id = RXO_##x #define OP(n,t,r,a) (rx->op[n].type = t, \ rx->op[n].reg = r, \ @@ -61,9 +92,12 @@ static int memex[] = rx->op[n].size = s ) /* This is for the BWL and BW bitfields. */ -static int SCALE[] = { 1, 2, 4 }; +static int SCALE[] = { 1, 2, 4, 0 }; /* This is for the prefix size enum. */ -static int PSCALE[] = { 4, 1, 1, 1, 2, 2, 2, 3, 4 }; +static int PSCALE[] = { 4, 1, 1, 1, 2, 2, 2, 3, 4, 8 }; + +#define GET_SCALE(_indx) ((unsigned)(_indx) < ARRAY_SIZE (SCALE) ? SCALE[(_indx)] : 0) +#define GET_PSCALE(_indx) ((unsigned)(_indx) < ARRAY_SIZE (PSCALE) ? PSCALE[(_indx)] : 0) static int flagmap[] = {0, 1, 2, 3, 0, 0, 0, 0, 16, 17, 0, 0, 0, 0, 0, 0 }; @@ -83,33 +117,47 @@ static int dsp3map[] = { 8, 9, 10, 3, 4, 5, 6, 7 }; #define DC(c) OP (0, RX_Operand_Immediate, 0, c) #define DR(r) OP (0, RX_Operand_Register, r, 0) #define DI(r,a) OP (0, RX_Operand_Indirect, r, a) -#define DIs(r,a,s) OP (0, RX_Operand_Indirect, r, (a) * SCALE[s]) +#define DIs(r,a,s) OP (0, RX_Operand_Indirect, r, (a) * GET_SCALE (s)) #define DD(t,r,s) rx_disp (0, t, r, bwl[s], ld); #define DF(r) OP (0, RX_Operand_Flag, flagmap[r], 0) +#define DCR(r) OP (0, RX_Operand_DoubleCReg, r, 0) +#define DDR(r) OP (0, RX_Operand_DoubleReg, r, 0) +#define DDRH(r) OP (0, RX_Operand_DoubleRegH, r, 0) +#define DDRL(r) OP (0, RX_Operand_DoubleRegL, r, 0) +#define DCND(r) OP (0, RX_Operand_DoubleCond, r, 0) #define SC(i) OP (1, RX_Operand_Immediate, 0, i) #define SR(r) OP (1, RX_Operand_Register, r, 0) #define SRR(r) OP (1, RX_Operand_TwoReg, r, 0) #define SI(r,a) OP (1, RX_Operand_Indirect, r, a) -#define SIs(r,a,s) OP (1, RX_Operand_Indirect, r, (a) * SCALE[s]) +#define SIs(r,a,s) OP (1, RX_Operand_Indirect, r, (a) * GET_SCALE (s)) #define SD(t,r,s) rx_disp (1, t, r, bwl[s], ld); #define SP(t,r) rx_disp (1, t, r, (t!=3) ? RX_UByte : RX_Long, ld); P(t, 1); #define SPm(t,r,m) rx_disp (1, t, r, memex[m], ld); rx->op[1].size = memex[m]; #define Scc(cc) OP (1, RX_Operand_Condition, cc, 0) +#define SCR(r) OP (1, RX_Operand_DoubleCReg, r, 0) +#define SDR(r) OP (1, RX_Operand_DoubleReg, r, 0) +#define SDRH(r) OP (1, RX_Operand_DoubleRegH, r, 0) +#define SDRL(r) OP (1, RX_Operand_DoubleRegL, r, 0) #define S2C(i) OP (2, RX_Operand_Immediate, 0, i) #define S2R(r) OP (2, RX_Operand_Register, r, 0) #define S2I(r,a) OP (2, RX_Operand_Indirect, r, a) -#define S2Is(r,a,s) OP (2, RX_Operand_Indirect, r, (a) * SCALE[s]) +#define S2Is(r,a,s) OP (2, RX_Operand_Indirect, r, (a) * GET_SCALE (s)) #define S2D(t,r,s) rx_disp (2, t, r, bwl[s], ld); #define S2P(t,r) rx_disp (2, t, r, (t!=3) ? RX_UByte : RX_Long, ld); P(t, 2); #define S2Pm(t,r,m) rx_disp (2, t, r, memex[m], ld); rx->op[2].size = memex[m]; #define S2cc(cc) OP (2, RX_Operand_Condition, cc, 0) +#define S2DR(r) OP (2, RX_Operand_DoubleReg, r, 0) +#define S2CR(r) OP (2, RX_Operand_DoubleCReg, r, 0) + +#define SDD(t,r,s) rx_disp (1, t, r, bwl, ld); #define BWL(sz) rx->op[0].size = rx->op[1].size = rx->op[2].size = rx->size = bwl[sz] #define sBWL(sz) rx->op[0].size = rx->op[1].size = rx->op[2].size = rx->size = sbwl[sz] -#define uBWL(sz) rx->op[0].size = rx->op[1].size = rx->op[2].size = rx->size = ubwl[sz] +#define uBW(sz) rx->op[0].size = rx->op[1].size = rx->op[2].size = rx->size = ubw[sz] #define P(t, n) rx->op[n].size = (t!=3) ? RX_UByte : RX_Long; +#define DL(sz) rx->op[0].size = rx->op[1].size = rx->op[2].size = rx->size = _ld[sz] #define F(f) store_flags(rx, f) @@ -187,7 +235,7 @@ immediate (int sfield, int ex, LocalData * ld) } static void -rx_disp (int n, int type, int reg, int size, LocalData * ld) +rx_disp (int n, int type, int reg, unsigned int size, LocalData * ld) { int disp; @@ -198,13 +246,13 @@ rx_disp (int n, int type, int reg, int size, LocalData * ld) ld->rx->op[n].type = RX_Operand_Register; break; case 0: - ld->rx->op[n].type = RX_Operand_Indirect; + ld->rx->op[n].type = RX_Operand_Zero_Indirect; ld->rx->op[n].addend = 0; break; case 1: ld->rx->op[n].type = RX_Operand_Indirect; disp = GETBYTE (); - ld->rx->op[n].addend = disp * PSCALE[size]; + ld->rx->op[n].addend = disp * GET_PSCALE (size); break; case 2: ld->rx->op[n].type = RX_Operand_Indirect; @@ -214,7 +262,7 @@ rx_disp (int n, int type, int reg, int size, LocalData * ld) #else disp = disp + GETBYTE () * 256; #endif - ld->rx->op[n].addend = disp * PSCALE[size]; + ld->rx->op[n].addend = disp * GET_PSCALE (size); break; default: abort (); @@ -226,7 +274,7 @@ rx_disp (int n, int type, int reg, int size, LocalData * ld) #define xZ 2 #define xC 1 -#define F_____ +#define F_____ #define F___ZC rx->flags_0 = rx->flags_s = xZ|xC; #define F__SZ_ rx->flags_0 = rx->flags_s = xS|xZ; #define F__SZC rx->flags_0 = rx->flags_s = xS|xZ|xC; @@ -284,10 +332,10 @@ rx_decode_opcode (unsigned long pc AU, ID(mov); sBWL (sz); DIs(dst, d*16+sppp, sz); SC(IMM(1)); F_____; /** 11sz sd ss rsrc rdst mov%s %1, %0 */ - if (ss == 3 && sz == 2 && rsrc == 0 && rdst == 0) + if (sd == 3 && ss == 3 && sz == 2 && rsrc == 0 && rdst == 0) { ID(nop2); - rx->syntax = "nop"; + SYNTAX ("nop\t; mov.l\tr0, r0"); } else { @@ -315,7 +363,7 @@ rx_decode_opcode (unsigned long pc AU, ID(movbir); sBWL(sz); DR(rdst); SRR(isrc); S2R(bsrc); F_____; /** 1111 1110 11sz isrc bsrc rdst movu%s [%1, %2], %0 */ - ID(movbi); uBWL(sz); DR(rdst); SRR(isrc); S2R(bsrc); F_____; + ID(movbi); uBW(sz); DR(rdst); SRR(isrc); S2R(bsrc); F_____; /** 1111 1101 0010 0p sz rdst rsrc mov%s %1, %0 */ ID(mov); sBWL (sz); SR(rsrc); F_____; @@ -326,13 +374,13 @@ rx_decode_opcode (unsigned long pc AU, OP(1, p ? RX_Operand_Predec : RX_Operand_Postinc, rsrc, 0); /** 1011 w dsp a src b dst movu%s %1, %0 */ - ID(mov); uBWL(w); DR(dst); SIs(src, dsp*4+a*2+b, w); F_____; + ID(mov); uBW(w); DR(dst); SIs(src, dsp*4+a*2+b, w); F_____; /** 0101 1 s ss rsrc rdst movu%s %1, %0 */ - ID(mov); uBWL(s); SD(ss, rsrc, s); DR(rdst); F_____; + ID(mov); uBW(s); SD(ss, rsrc, s); DR(rdst); F_____; /** 1111 1101 0011 1p sz rsrc rdst movu%s %1, %0 */ - ID(mov); uBWL (sz); DR(rdst); F_____; + ID(mov); uBW (sz); DR(rdst); F_____; OP(1, p ? RX_Operand_Predec : RX_Operand_Postinc, rsrc, 0); /*----------------------------------------------------------------------*/ @@ -343,10 +391,10 @@ rx_decode_opcode (unsigned long pc AU, /** 0110 1110 dsta dstb pushm %1-%2 */ ID(pushm); SR(dsta); S2R(dstb); F_____; - + /** 0111 1110 1011 rdst pop %0 */ ID(mov); OP(1, RX_Operand_Postinc, 0, 0); DR(rdst); F_____; - + /** 0111 1110 10sz rsrc push%s %1 */ ID(mov); BWL(sz); OP(0, RX_Operand_Predec, 0, 0); SR(rsrc); F_____; @@ -544,13 +592,23 @@ rx_decode_opcode (unsigned long pc AU, /* MAX */ /** 1111 1101 0111 im00 0100rdst max #%1, %0 */ - ID(max); DR(rdst); SC(IMMex(im)); + int val = IMMex (im); + if (im == 0 && (unsigned) val == 0x80000000 && rdst == 0) + { + ID (nop7); + SYNTAX("nop\t; max\t#0x80000000, r0"); + } + else + { + ID(max); + } + DR(rdst); SC(val); /** 1111 1100 0001 00ss rsrc rdst max %1%S1, %0 */ if (ss == 3 && rsrc == 0 && rdst == 0) { ID(nop3); - rx->syntax = "nop"; + SYNTAX("nop\t; max\tr0, r0"); } else { @@ -576,10 +634,38 @@ rx_decode_opcode (unsigned long pc AU, /* MUL */ /** 0110 0011 immm rdst mul #%1, %0 */ - ID(mul); DR(rdst); SC(immm); F_____; + if (immm == 1 && rdst == 0) + { + ID(nop2); + SYNTAX ("nop\t; mul\t#1, r0"); + } + else + { + ID(mul); + } + DR(rdst); SC(immm); F_____; /** 0111 01im 0001rdst mul #%1, %0 */ - ID(mul); DR(rdst); SC(IMMex(im)); F_____; + int val = IMMex(im); + if (val == 1 && rdst == 0) + { + SYNTAX("nop\t; mul\t#1, r0"); + switch (im) + { + case 2: ID(nop4); break; + case 3: ID(nop5); break; + case 0: ID(nop6); break; + default: + ID(mul); + SYNTAX("mul #%1, %0"); + break; + } + } + else + { + ID(mul); + } + DR(rdst); SC(val); F_____; /** 0100 11ss rsrc rdst mul %1%S1, %0 */ ID(mul); SP(ss, rsrc); DR(rdst); F_____; @@ -783,35 +869,35 @@ rx_decode_opcode (unsigned long pc AU, /*----------------------------------------------------------------------*/ /* HI/LO stuff */ -/** 1111 1101 0000 0000 srca srcb mulhi %1, %2 */ - ID(mulhi); SR(srca); S2R(srcb); F_____; +/** 1111 1101 0000 a000 srca srcb mulhi %1, %2, %0 */ + ID(mulhi); DR(a+32); SR(srca); S2R(srcb); F_____; -/** 1111 1101 0000 0001 srca srcb mullo %1, %2 */ - ID(mullo); SR(srca); S2R(srcb); F_____; +/** 1111 1101 0000 a001 srca srcb mullo %1, %2, %0 */ + ID(mullo); DR(a+32); SR(srca); S2R(srcb); F_____; -/** 1111 1101 0000 0100 srca srcb machi %1, %2 */ - ID(machi); SR(srca); S2R(srcb); F_____; +/** 1111 1101 0000 a100 srca srcb machi %1, %2, %0 */ + ID(machi); DR(a+32); SR(srca); S2R(srcb); F_____; -/** 1111 1101 0000 0101 srca srcb maclo %1, %2 */ - ID(maclo); SR(srca); S2R(srcb); F_____; +/** 1111 1101 0000 a101 srca srcb maclo %1, %2, %0 */ + ID(maclo); DR(a+32); SR(srca); S2R(srcb); F_____; -/** 1111 1101 0001 0111 0000 rsrc mvtachi %1 */ - ID(mvtachi); SR(rsrc); F_____; +/** 1111 1101 0001 0111 a000 rsrc mvtachi %1, %0 */ + ID(mvtachi); DR(a+32); SR(rsrc); F_____; -/** 1111 1101 0001 0111 0001 rsrc mvtaclo %1 */ - ID(mvtaclo); SR(rsrc); F_____; +/** 1111 1101 0001 0111 a001 rsrc mvtaclo %1, %0 */ + ID(mvtaclo); DR(a+32); SR(rsrc); F_____; -/** 1111 1101 0001 1111 0000 rdst mvfachi %0 */ - ID(mvfachi); DR(rdst); F_____; +/** 1111 1101 0001 111i a m00 rdst mvfachi #%2, %1, %0 */ + ID(mvfachi); S2C(((i^1)<<1)|m); SR(a+32); DR(rdst); F_____; -/** 1111 1101 0001 1111 0010 rdst mvfacmi %0 */ - ID(mvfacmi); DR(rdst); F_____; +/** 1111 1101 0001 111i a m10 rdst mvfacmi #%2, %1, %0 */ + ID(mvfacmi); S2C(((i^1)<<1)|m); SR(a+32); DR(rdst); F_____; -/** 1111 1101 0001 1111 0001 rdst mvfaclo %0 */ - ID(mvfaclo); DR(rdst); F_____; +/** 1111 1101 0001 111i a m01 rdst mvfaclo #%2, %1, %0 */ + ID(mvfaclo); S2C(((i^1)<<1)|m); SR(a+32); DR(rdst); F_____; -/** 1111 1101 0001 1000 000i 0000 racw #%1 */ - ID(racw); SC(i+1); F_____; +/** 1111 1101 0001 1000 a00i 0000 racw #%1, %0 */ + ID(racw); SC(i+1); DR(a+32); F_____; /*----------------------------------------------------------------------*/ /* SAT */ @@ -875,6 +961,8 @@ rx_decode_opcode (unsigned long pc AU, /** 1111 1100 0110 00sd rdst rsrc bset %1, %0%S0 */ ID(bset); BWL(BSIZE); SR(rsrc); DD(sd, rdst, BSIZE); F_____; + if (sd == 3) /* bset reg,reg */ + BWL(LSIZE); /** 0111 100b ittt rdst bset #%1, %0 */ ID(bset); BWL(LSIZE); SC(b*16+ittt); DR(rdst); F_____; @@ -885,6 +973,8 @@ rx_decode_opcode (unsigned long pc AU, /** 1111 1100 0110 01sd rdst rsrc bclr %1, %0%S0 */ ID(bclr); BWL(BSIZE); SR(rsrc); DD(sd, rdst, BSIZE); F_____; + if (sd == 3) /* bset reg,reg */ + BWL(LSIZE); /** 0111 101b ittt rdst bclr #%1, %0 */ ID(bclr); BWL(LSIZE); SC(b*16+ittt); DR(rdst); F_____; @@ -895,6 +985,8 @@ rx_decode_opcode (unsigned long pc AU, /** 1111 1100 0110 10sd rdst rsrc btst %2, %1%S1 */ ID(btst); BWL(BSIZE); S2R(rsrc); SD(sd, rdst, BSIZE); F___ZC; + if (sd == 3) /* bset reg,reg */ + BWL(LSIZE); /** 0111 110b ittt rdst btst #%2, %1 */ ID(btst); BWL(LSIZE); S2C(b*16+ittt); SR(rdst); F___ZC; @@ -905,6 +997,8 @@ rx_decode_opcode (unsigned long pc AU, /** 1111 1100 0110 11sd rdst rsrc bnot %1, %0%S0 */ ID(bnot); BWL(BSIZE); SR(rsrc); DD(sd, rdst, BSIZE); + if (sd == 3) /* bset reg,reg */ + BWL(LSIZE); /** 1111 1101 111bittt 1111 rdst bnot #%1, %0 */ ID(bnot); BWL(LSIZE); SC(bittt); DR(rdst); @@ -970,6 +1064,218 @@ rx_decode_opcode (unsigned long pc AU, /** 1111 1100 1101 sz sd rdst cond sc%1%s %0 */ ID(sccnd); BWL(sz); DD (sd, rdst, sz); Scc(cond); +/*----------------------------------------------------------------------*/ +/* RXv2 enhanced */ + +/** 1111 1101 0010 0111 rdst rsrc movco %1, [%0] */ + ID(movco); SR(rsrc); DR(rdst); F_____; + +/** 1111 1101 0010 1111 rsrc rdst movli [%1], %0 */ + ID(movli); SR(rsrc); DR(rdst); F_____; + +/** 1111 1100 0100 1011 rsrc rdst stz %1, %0 */ + ID(stcc); SR(rsrc); DR(rdst); S2cc(RXC_z); + +/** 1111 1100 0100 1111 rsrc rdst stnz %1, %0 */ + ID(stcc); SR(rsrc); DR(rdst); S2cc(RXC_nz); + +/** 1111 1101 0000 a111 srca srcb emaca %1, %2, %0 */ + ID(emaca); DR(a+32); SR(srca); S2R(srcb); F_____; + +/** 1111 1101 0100 a111 srca srcb emsba %1, %2, %0 */ + ID(emsba); DR(a+32); SR(srca); S2R(srcb); F_____; + +/** 1111 1101 0000 a011 srca srcb emula %1, %2, %0 */ + ID(emula); DR(a+32); SR(srca); S2R(srcb); F_____; + +/** 1111 1101 0000 a110 srca srcb maclh %1, %2, %0 */ + ID(maclh); DR(a+32); SR(srca); S2R(srcb); F_____; + +/** 1111 1101 0100 a100 srca srcb msbhi %1, %2, %0 */ + ID(msbhi); DR(a+32); SR(srca); S2R(srcb); F_____; + +/** 1111 1101 0100 a110 srca srcb msblh %1, %2, %0 */ + ID(msblh); DR(a+32); SR(srca); S2R(srcb); F_____; + +/** 1111 1101 0100 a101 srca srcb msblo %1, %2, %0 */ + ID(msblo); DR(a+32); SR(srca); S2R(srcb); F_____; + +/** 1111 1101 0000 a010 srca srcb mullh %1, %2, %0 */ + ID(mullh); DR(a+32); SR(srca); S2R(srcb); F_____; + +/** 1111 1101 0001 111i a m11 rdst mvfacgu #%2, %1, %0 */ + ID(mvfacgu); S2C(((i^1)<<1)|m); SR(a+32); DR(rdst); F_____; + +/** 1111 1101 0001 0111 a011 rdst mvtacgu %0, %1 */ + ID(mvtacgu); DR(a+32); SR(rdst); F_____; + +/** 1111 1101 0001 1001 a00i 0000 racl #%1, %0 */ + ID(racl); SC(i+1); DR(a+32); F_____; + +/** 1111 1101 0001 1001 a10i 0000 rdacl #%1, %0 */ + ID(rdacl); SC(i+1); DR(a+32); F_____; + +/** 1111 1101 0001 1000 a10i 0000 rdacw #%1, %0 */ + ID(rdacw); SC(i+1); DR(a+32); F_____; + +/** 1111 1111 1010 rdst srca srcb fadd %2, %1, %0 */ + ID(fadd); DR(rdst); SR(srcb); S2R(srca); F__SZ_; + +/** 1111 1111 1000 rdst srca srcb fsub %2, %1, %0 */ + ID(fsub); DR(rdst); SR(srcb); S2R(srca); F__SZ_; + +/** 1111 1111 1011 rdst srca srcb fmul %2, %1, %0 */ + ID(fmul); DR(rdst); SR(srcb); S2R(srca); F__SZ_; + +/** 1111 1100 1010 00sd rsrc rdst fsqrt %1%S1, %0 */ + ID(fsqrt); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_; + +/** 1111 1100 1010 01sd rsrc rdst ftou %1%S1, %0 */ + ID(ftou); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_; + +/** 1111 1100 0101 01sd rsrc rdst utof %1%S1, %0 */ + ID(utof); DR (rdst); SP(sd, rsrc); F__SZ_; + +/** 0000 0110 mx10 00sd 0001 0101 rsrc rdst utof %1%S1, %0 */ + ID(utof); DR (rdst); SPm(sd, rsrc, mx); F__SZ_; + +/*----------------------------------------------------------------------*/ +/* RXv3 enhanced */ + +/** 1111 1111 0110 rdst srca srcb xor %2, %1, %0 */ + ID(xor); DR(rdst); SR(srcb); S2R(srca); F__SZ_; + +/** 1111 1100 0101 1110 rsrc rdst bfmov %bf */ + ID(bfmov); DR(rdst); SR(rsrc); S2C(IMM(2)); F_____; + +/** 1111 1100 0101 1010 rsrc rdst bfmovz %bf */ + ID(bfmovz); DR(rdst); SR(rsrc); S2C(IMM(2)); F_____; + +/** 1111 1101 0111 0110 1101 rsrc 0000 0000 rstr %1 */ + ID(rstr); SR(rsrc); F_____; + +/** 1111 1101 0111 0110 1111 0000 rstr #%1 */ + ID(rstr); SC(IMM(1)); F_____; + +/** 1111 1101 0111 0110 1100 rsrc 0000 0000 save %1 */ + ID(save); SR(rsrc); F_____; + +/** 1111 1101 0111 0110 1110 0000 save #%1 */ + ID(save); SC(IMM(1)); F_____; + +/** 1111 1101 0111 0111 1000 rsrc rdst 001s dmov%s %1, %0 */ + ID(dmov); DDRH(rdst); SR(rsrc); DL(s); F_____; + +/** 1111 1101 0111 0111 1000 rsrc rdst 0000 dmov.l %1, %0 */ + ID(dmov); DDRL(rdst); SR(rsrc); F_____; + +/** 1111 1101 0111 0101 1000 rdst rsrc 0010 dmov.l %1, %0 */ + ID(dmov); DR(rdst); SDRH(rsrc); F_____; + +/** 1111 1101 0111 0101 1000 rdst rsrc 0000 dmov.l %1, %0 */ + ID(dmov); DR(rdst); SDRL(rsrc); F_____; + +/** 0111 0110 1001 0000 rsrc 1100 rdst 0000 dmov.d %1, %0 */ + ID(dmov); DDR(rdst); SDR(rsrc); F_____; + +/** 1111 1100 0111 1000 rdst 1000 rsrc 0000 dmov.d %1, %0 */ + ID(dmov); DD(0, rdst, 0); SDR(rsrc); F_____; + +/** 1111 1100 0111 10sz rdst 1000 dmov.d %1, %0 */ + int rsrc; + rx_disp(0, sz, rdst, RX_Double, ld); + rsrc = GETBYTE(); + if (rsrc & 0x0f) + UNSUPPORTED(); + else { + ID(dmov); SDR(rsrc >> 4); F_____; + } + +/** 1111 1100 1100 1000 rsrc 1000 rdst 0000 dmov.d %1, %0 */ + ID(dmov); SD(sd, rsrc, 0) ; DDR(rdst); F_____; + +/** 1111 1100 1100 10sz rsrc 1000 dmov.d %1, %0 */ + int rdst; + rx_disp(1, sz, rsrc, RX_Double, ld); + rdst = GETBYTE(); + if (rdst & 0x0f) + UNSUPPORTED(); + else { + ID(dmov); DDR(rdst >> 4); F_____; + } + +/** 1111 1001 0000 0011 rdst 001s dmov%s #%1, %0 */ + ID(dmov); DDRH(rdst); DL(s); SC(IMMex(0)); F_____; + +/** 1111 1001 0000 0011 rdst 0000 dmov.l #%1, %0 */ + ID(dmov); DDRL(rdst); SC(IMMex(0)); F_____; + +/** 0111 0101 1011 1000 rdst rnum dpopm.d %1-%2 */ + ID(dpopm); SDR(rdst); S2DR(rdst + rnum); F_____; + +/** 0111 0101 1010 1000 rdst rnum dpopm.l %1-%2 */ + ID(dpopm); SCR(rdst); S2CR(rdst + rnum); F_____; + +/** 0111 0101 1011 0000 rdst rnum dpushm.d %1-%2 */ + ID(dpushm); SDR(rdst); S2DR(rdst + rnum); F_____; + +/** 0111 0101 1010 0000 rdst rnum dpushm.l %1-%2 */ + ID(dpushm); SCR(rdst); S2CR(rdst + rnum); F_____; + +/** 1111 1101 0111 0101 1000 rdst rsrc 0100 mvfdc %1, %0 */ + ID(mvfdc); DR(rdst); SCR(rsrc); F_____; + +/** 0111 0101 1001 0000 0001 1011 mvfdr */ + ID(mvfdr); F_____; + +/** 1111 1101 0111 0111 1000 rdst rsrc 0100 mvtdc %1, %0 */ + ID(mvtdc); DCR(rdst); SR(rsrc); F_____; + +/** 0111 0110 1001 0000 rsrc 1100 rdst 0001 dabs %1, %0 */ + ID(dabs); DDR(rdst); SDR(rsrc); F_____; + +/** 0111 0110 1001 0000 srcb 0000 rdst srca dadd %1, %2, %0 */ + ID(dadd); DDR(rdst); SDR(srca); S2DR(srcb); F_____; + +/** 0111 0110 1001 0000 srcb 1000 cond srca dcmp%0 %1, %2 */ + ID(dcmp); DCND(cond); SDR(srca); S2DR(srcb); F_____; + +/** 0111 0110 1001 0000 srcb 0101 rdst srca ddiv %1, %2, %0 */ + ID(ddiv); DDR(rdst); SDR(srca); S2DR(srcb); F_____; + +/** 0111 0110 1001 0000 srcb 0010 rdst srca dmul %1, %2, %0 */ + ID(dmul); DDR(rdst); SDR(srca); S2DR(srcb); F_____; + +/** 0111 0110 1001 0000 rsrc 1100 rdst 0010 dneg %1, %0 */ + ID(dneg); DDR(rdst); SDR(rsrc); F_____; + +/** 0111 0110 1001 0000 rsrc 1101 rdst 1101 dround %1, %0 */ + ID(dround); DDR(rdst); SDR(rsrc); F_____; + +/** 0111 0110 1001 0000 rsrc 1101 rdst 0000 dsqrt %1, %0 */ + ID(dsqrt); DDR(rdst); SDR(rsrc); F_____; + +/** 0111 0110 1001 0000 srcb 0001 rdst srca dsub %1, %2, %0 */ + ID(dsub); DDR(rdst); SDR(srca); S2DR(srcb); F_____; + +/** 0111 0110 1001 0000 rsrc 1101 rdst 1100 dtof %1, %0 */ + ID(dtof); DDR(rdst); SDR(rsrc); F_____; + +/** 0111 0110 1001 0000 rsrc 1101 rdst 1000 dtoi %1, %0 */ + ID(dtoi); DDR(rdst); SDR(rsrc); F_____; + +/** 0111 0110 1001 0000 rsrc 1101 rdst 1001 dtou %1, %0 */ + ID(dtou); DDR(rdst); SDR(rsrc); F_____; + +/** 1111 1101 0111 0111 1000 rsrc rdst 1010 ftod %1, %0 */ + ID(ftod); DDR(rdst); SR(rsrc); F_____; + +/** 1111 1101 0111 0111 1000 rsrc rdst 1001 itod %1, %0 */ + ID(itod); DDR(rdst); SR(rsrc); F_____; + +/** 1111 1101 0111 0111 1000 rsrc rdst 1101 utod %1, %0 */ + ID(dsqrt); DDR(rdst); SR(rsrc); F_____; + /** */ return rx->n_bytes;