X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;ds=sidebyside;f=opcodes%2Fscore7-dis.c;h=6d20e7f50ce139811ba5643541de3af924cfab06;hb=c54a9b56696e584c2b8c7146caac337c063f5516;hp=b48d1786b772e45807208fe1e943d49a8c7eef63;hpb=b33bafa0d71c6f92b0d639466eb13af58989bfb7;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/score7-dis.c b/opcodes/score7-dis.c index b48d1786b7..6d20e7f50c 100644 --- a/opcodes/score7-dis.c +++ b/opcodes/score7-dis.c @@ -1,5 +1,5 @@ /* Instruction printing code for Score - Copyright 2009 Free Software Foundation, Inc. + Copyright (C) 2009-2020 Free Software Foundation, Inc. Contributed by: Brain.lin (brain.lin@sunplusct.com) Mei Ligang (ligang@sunnorth.com.cn) @@ -48,8 +48,8 @@ struct score_opcode { unsigned long value; - unsigned long mask; /* Recognise instruction if (op & mask) == value. */ - char *assembler; /* Disassembly string. */ + unsigned long mask; /* Recognise instruction if (op & mask) == value. */ + char *assembler; /* Disassembly string. */ }; /* Note: There is a partial ordering in this table - it must be searched from @@ -59,7 +59,7 @@ static struct score_opcode score_opcodes[] = { /* Score Instructions. */ {0x3800000a, 0x3e007fff, "abs\t\t%20-24r, %15-19r"}, - {0x3800004b, 0x3e007fff, "abs.s\t\t%20-24r, %15-19r"}, + {0x3800004b, 0x3e007fff, "abs.s\t\t%20-24r, %15-19r"}, {0x00000010, 0x3e0003ff, "add\t\t%20-24r, %15-19r, %10-14r"}, {0x00000011, 0x3e0003ff, "add.c\t\t%20-24r, %15-19r, %10-14r"}, {0x38000048, 0x3e0003ff, "add.s\t\t%20-24r, %15-19r, %10-14r"}, @@ -226,32 +226,32 @@ static struct score_opcode score_opcodes[] = {0x31e00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, {0x31f00000, 0x3ff00000, "cache\t\t%20-24d, [%15-19r, %0-14i]"}, {0x38000000, 0x3ff003ff, "mad\t\t%15-19r, %10-14r"}, - {0x38000020, 0x3ff003ff, "madu\t\t%15-19r, %10-14r"}, + {0x38000020, 0x3ff003ff, "madu\t\t%15-19r, %10-14r"}, {0x38000080, 0x3ff003ff, "mad.f\t\t%15-19r, %10-14r"}, - {0x38000001, 0x3ff003ff, "msb\t\t%15-19r, %10-14r"}, + {0x38000001, 0x3ff003ff, "msb\t\t%15-19r, %10-14r"}, {0x38000021, 0x3ff003ff, "msbu\t\t%15-19r, %10-14r"}, {0x38000081, 0x3ff003ff, "msb.f\t\t%15-19r, %10-14r"}, - {0x38000102, 0x3ff003ff, "mazl\t\t%15-19r, %10-14r"}, - {0x38000182, 0x3ff003ff, "mazl.f\t\t%15-19r, %10-14r"}, - {0x38000002, 0x3ff003ff, "madl\t\t%15-19r, %10-14r"}, - {0x380000c2, 0x3ff003ff, "madl.fs\t\t%15-19r, %10-14r"}, - {0x38000303, 0x3ff003ff, "mazh\t\t%15-19r, %10-14r"}, - {0x38000383, 0x3ff003ff, "mazh.f\t\t%15-19r, %10-14r"}, - {0x38000203, 0x3ff003ff, "madh\t\t%15-19r, %10-14r"}, - {0x380002c3, 0x3ff003ff, "madh.fs\t\t%15-19r, %10-14r"}, - {0x38000007, 0x3e0003ff, "max\t\t%20-24r, %15-19r, %10-14r"}, + {0x38000102, 0x3ff003ff, "mazl\t\t%15-19r, %10-14r"}, + {0x38000182, 0x3ff003ff, "mazl.f\t\t%15-19r, %10-14r"}, + {0x38000002, 0x3ff003ff, "madl\t\t%15-19r, %10-14r"}, + {0x380000c2, 0x3ff003ff, "madl.fs\t\t%15-19r, %10-14r"}, + {0x38000303, 0x3ff003ff, "mazh\t\t%15-19r, %10-14r"}, + {0x38000383, 0x3ff003ff, "mazh.f\t\t%15-19r, %10-14r"}, + {0x38000203, 0x3ff003ff, "madh\t\t%15-19r, %10-14r"}, + {0x380002c3, 0x3ff003ff, "madh.fs\t\t%15-19r, %10-14r"}, + {0x38000007, 0x3e0003ff, "max\t\t%20-24r, %15-19r, %10-14r"}, {0x38000006, 0x3e0003ff, "min\t\t%20-24r, %15-19r, %10-14r"}, - {0x38000104, 0x3ff003ff, "mszl\t\t%15-19r, %10-14r"}, - {0x38000184, 0x3ff003ff, "mszl.f\t\t%15-19r, %10-14r"}, - {0x38000004, 0x3ff003ff, "msbl\t\t%15-19r, %10-14r"}, + {0x38000104, 0x3ff003ff, "mszl\t\t%15-19r, %10-14r"}, + {0x38000184, 0x3ff003ff, "mszl.f\t\t%15-19r, %10-14r"}, + {0x38000004, 0x3ff003ff, "msbl\t\t%15-19r, %10-14r"}, {0x380000c4, 0x3ff003ff, "msbl.fs\t\t%15-19r, %10-14r"}, - {0x38000305, 0x3ff003ff, "mszh\t\t%15-19r, %10-14r"}, - {0x38000385, 0x3ff003ff, "mszh.f\t\t%15-19r, %10-14r"}, - {0x38000205, 0x3ff003ff, "msbh\t\t%15-19r, %10-14r"}, - {0x380002c5, 0x3ff003ff, "msbh.fs\t\t%15-19r, %10-14r"}, - {0x3800004e, 0x3e0003ff, "sll.s\t\t%20-24r, %15-19r, %10-14r"}, - {0x38000049, 0x3e0003ff, "sub.s\t\t%20-24r, %15-19r, %10-14r"}, - {0x3800000d, 0x3e007fff, "clz\t\t%20-24r, %15-19r"}, + {0x38000305, 0x3ff003ff, "mszh\t\t%15-19r, %10-14r"}, + {0x38000385, 0x3ff003ff, "mszh.f\t\t%15-19r, %10-14r"}, + {0x38000205, 0x3ff003ff, "msbh\t\t%15-19r, %10-14r"}, + {0x380002c5, 0x3ff003ff, "msbh.fs\t\t%15-19r, %10-14r"}, + {0x3800004e, 0x3e0003ff, "sll.s\t\t%20-24r, %15-19r, %10-14r"}, + {0x38000049, 0x3e0003ff, "sub.s\t\t%20-24r, %15-19r, %10-14r"}, + {0x3800000d, 0x3e007fff, "clz\t\t%20-24r, %15-19r"}, {0x38000000, 0x3e000000, "ceinst\t\t%20-24d, %15-19r, %10-14r, %5-9d, %0-4d"}, {0x00000019, 0x3ff003ff, "cmpteq.c\t\t%15-19r, %10-14r"}, {0x00100019, 0x3ff003ff, "cmptmi.c\t\t%15-19r, %10-14r"}, @@ -310,16 +310,16 @@ static struct score_opcode score_opcodes[] = {0x0e000000, 0x3e000007, "lw\t\t%20-24r, [%15-19r]+, %3-14i"}, {0x00002008, 0x0000700f, "lw!\t\t%8-11r, [%4-7r]"}, {0x00007000, 0x00007007, "lwp!\t\t%8-11r, %3-7d2"}, - {0x0000100b, 0x0000700f, "madh.fs!\t\t%8-11r, %4-7r"}, - {0x0000100a, 0x0000700f, "madl.fs!\t\t%8-11r, %4-7r"}, - {0x00001005, 0x0000700f, "madu!\t\t%8-11r, %4-7r"}, + {0x0000100b, 0x0000700f, "madh.fs!\t\t%8-11r, %4-7r"}, + {0x0000100a, 0x0000700f, "madl.fs!\t\t%8-11r, %4-7r"}, + {0x00001005, 0x0000700f, "madu!\t\t%8-11r, %4-7r"}, {0x00001004, 0x0000700f, "mad.f!\t\t%8-11r, %4-7r"}, - {0x00001009, 0x0000700f, "mazh.f!\t\t%8-11r, %4-7r"}, + {0x00001009, 0x0000700f, "mazh.f!\t\t%8-11r, %4-7r"}, {0x00001008, 0x0000700f, "mazl.f!\t\t%8-11r, %4-7r"}, {0x00000448, 0x3e007fff, "mfcel\t\t%20-24r"}, {0x00001001, 0x00007f0f, "mfcel!\t\t%4-7r"}, - {0x00000848, 0x3e007fff, "mfceh\t\t%20-24r"}, - {0x00001101, 0x00007f0f, "mfceh!\t\t%4-7r"}, + {0x00000848, 0x3e007fff, "mfceh\t\t%20-24r"}, + {0x00001101, 0x00007f0f, "mfceh!\t\t%4-7r"}, {0x00000c48, 0x3e007fff, "mfcehl\t\t%20-24r, %15-19r"}, {0x00000048, 0x3e0003ff, "mfce\t\t%20-24r, er%10-14d"}, {0x00000050, 0x3e0003ff, "mfsr\t\t%20-24r, sr%10-14d"}, @@ -331,10 +331,10 @@ static struct score_opcode score_opcodes[] = {0x0c000017, 0x3e00001f, "mfcc2\t\t%20-24r, c%15-19r"}, {0x0c00001f, 0x3e00001f, "mfcc3\t\t%20-24r, c%15-19r"}, {0x00000002, 0x0000700f, "mhfl!\t\t%8-11R, %4-7r"}, - {0x00000001, 0x0000700f, "mlfh!\t\t%8-11r, %4-7R"}, + {0x00000001, 0x0000700f, "mlfh!\t\t%8-11r, %4-7R"}, {0x00001006, 0x0000700f, "msb.f!\t\t%8-11r, %4-7r"}, {0x0000100f, 0x0000700f, "msbh.fs!\t\t%8-11r, %4-7r"}, - {0x0000100e, 0x0000700f, "msbl.fs!\t\t%8-11r, %4-7r"}, + {0x0000100e, 0x0000700f, "msbl.fs!\t\t%8-11r, %4-7r"}, {0x00001007, 0x0000700f, "msbu!\t\t%8-11r, %4-7r"}, {0x0000100d, 0x0000700f, "mszh.f!\t\t%8-11r, %4-7r"}, {0x0000100c, 0x0000700f, "mszl.f!\t\t%8-11r, %4-7r"}, @@ -355,11 +355,11 @@ static struct score_opcode score_opcodes[] = {0x00000040, 0x3e0003ff, "mul\t\t%15-19r, %10-14r"}, {0x00000040, 0x3e0003ff, "maz\t\t%15-19r, %10-14r"}, {0x00000041, 0x3e0003ff, "mul.f\t\t%15-19r, %10-14r"}, - {0x00000041, 0x3e0003ff, "maz.f\t\t%15-19r, %10-14r"}, + {0x00000041, 0x3e0003ff, "maz.f\t\t%15-19r, %10-14r"}, {0x00001002, 0x0000700f, "mul.f!\t\t%8-11r, %4-7r"}, {0x00000042, 0x3e0003ff, "mulu\t\t%15-19r, %10-14r"}, {0x00000042, 0x3e0003ff, "mazu\t\t%15-19r, %10-14r"}, - {0x00001003, 0x0000700f, "mulu!\t\t%8-11r, %4-7r"}, + {0x00001003, 0x0000700f, "mulu!\t\t%8-11r, %4-7r"}, {0x00000056, 0x3e007fff, "mvcs\t\t%20-24r, %15-19r"}, {0x00000456, 0x3e007fff, "mvcc\t\t%20-24r, %15-19r"}, {0x00000856, 0x3e007fff, "mvgtu\t\t%20-24r, %15-19r"}, @@ -386,8 +386,8 @@ static struct score_opcode score_opcodes[] = {0x00002006, 0x0000700f, "not!\t\t%8-11r, %4-7r"}, {0x00000022, 0x3e0003ff, "or\t\t%20-24r, %15-19r, %10-14r"}, {0x00000023, 0x3e0003ff, "or.c\t\t%20-24r, %15-19r, %10-14r"}, - {0x020a0000, 0x3e0e0001, "ori\t\t%20-24r, 0x%1-16x"}, - {0x020a0001, 0x3e0e0001, "ori.c\t\t%20-24r, 0x%1-16x"}, + {0x020a0000, 0x3e0e0001, "ori\t\t%20-24r, 0x%1-16x"}, + {0x020a0001, 0x3e0e0001, "ori.c\t\t%20-24r, 0x%1-16x"}, {0x0a0a0000, 0x3e0e0001, "oris\t\t%20-24r, 0x%1-16x"}, {0x0a0a0001, 0x3e0e0001, "oris.c\t\t%20-24r, 0x%1-16x"}, {0x1a000000, 0x3e000001, "orri\t\t%20-24r, %15-19r, 0x%1-14x"}, @@ -513,7 +513,8 @@ static struct score_opcode score_opcodes[] = {0x00000d05, 0x00007f0f, "tvc!"}, {0x00000026, 0x3e0003ff, "xor\t\t%20-24r, %15-19r, %10-14r"}, {0x00000027, 0x3e0003ff, "xor.c\t\t%20-24r, %15-19r, %10-14r"}, - {0x00002007, 0x0000700f, "xor!\t\t%8-11r, %4-7r"} + {0x00002007, 0x0000700f, "xor!\t\t%8-11r, %4-7r"}, + { 0, 0, NULL } }; typedef struct @@ -537,7 +538,7 @@ static unsigned int regname_selected = 0; #define score_regnames regnames[regname_selected].reg_names /* s3_s7: opcodes and export prototypes. */ -int +int s7_print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little); /* Print one instruction from PC on INFO->STREAM. @@ -552,142 +553,142 @@ print_insn_score32 (bfd_vma pc, struct disassemble_info *info, long given) for (insn = score_opcodes; insn->assembler; insn++) { if ((insn->mask & 0xffff0000) && (given & insn->mask) == insn->value) - { - char *c; - - for (c = insn->assembler; *c; c++) - { - if (*c == '%') - { - switch (*++c) - { - case 'j': - { - int target; - - if (info->flags & INSN_HAS_RELOC) - pc = 0; - target = (pc & 0xfe000000) | (given & 0x01fffffe); - (*info->print_address_func) (target, info); - } - break; - case 'b': - { - /* Sign-extend a 20-bit number. */ -#define SEXT20(x) ((((x) & 0xfffff) ^ (~ 0x7ffff)) + 0x80000) - int disp = ((given & 0x01ff8000) >> 5) | (given & 0x3fe); - int target = (pc + SEXT20 (disp)); - - (*info->print_address_func) (target, info); - } - break; - case '0': - case '1': - case '2': - case '3': - case '4': - case '5': - case '6': - case '7': - case '8': - case '9': - { - int bitstart = *c++ - '0'; - int bitend = 0; - - while (*c >= '0' && *c <= '9') - bitstart = (bitstart * 10) + *c++ - '0'; - - switch (*c) - { - case '-': - c++; - while (*c >= '0' && *c <= '9') - bitend = (bitend * 10) + *c++ - '0'; - - if (!bitend) - abort (); - - switch (*c) - { - case 'r': - { - long reg; - - reg = given >> bitstart; - reg &= (2 << (bitend - bitstart)) - 1; - - func (stream, "%s", score_regnames[reg]); - } - break; - case 'd': - { - long reg; - - reg = given >> bitstart; - reg &= (2 << (bitend - bitstart)) - 1; - - func (stream, "%ld", reg); - } - break; - case 'i': - { - long reg; - - reg = given >> bitstart; - reg &= (2 << (bitend - bitstart)) - 1; - reg = ((reg ^ (1 << (bitend - bitstart))) - - (1 << (bitend - bitstart))); - - if (((given & insn->mask) == 0x0c00000a) /* ldc1 */ - || ((given & insn->mask) == 0x0c000012) /* ldc2 */ - || ((given & insn->mask) == 0x0c00001c) /* ldc3 */ - || ((given & insn->mask) == 0x0c00000b) /* stc1 */ - || ((given & insn->mask) == 0x0c000013) /* stc2 */ - || ((given & insn->mask) == 0x0c00001b)) /* stc3 */ - reg <<= 2; - - func (stream, "%ld", reg); - } - break; - case 'x': - { - long reg; - - reg = given >> bitstart; - reg &= (2 << (bitend - bitstart)) - 1; - - func (stream, "%lx", reg); - } - break; - default: - abort (); - } - break; - case '`': - c++; - if ((given & (1 << bitstart)) == 0) - func (stream, "%c", *c); - break; - case '\'': - c++; - if ((given & (1 << bitstart)) != 0) - func (stream, "%c", *c); - break; - default: - abort (); - } - break; - } - default: + { + char *c; + + for (c = insn->assembler; *c; c++) + { + if (*c == '%') + { + switch (*++c) + { + case 'j': + { + int target; + + if (info->flags & INSN_HAS_RELOC) + pc = 0; + target = (pc & 0xfe000000) | (given & 0x01fffffe); + (*info->print_address_func) (target, info); + } + break; + case 'b': + { + /* Sign-extend a 20-bit number. */ +#define SEXT20(x) ((((x) & 0xfffff) ^ (~ 0x7ffff)) + 0x80000) + int disp = (given & 0x01ff8000) >> 5 | (given & 0x3fe); + int target = (pc + SEXT20 (disp)); + + (*info->print_address_func) (target, info); + } + break; + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + { + int bitstart = *c++ - '0'; + int bitend = 0; + + while (*c >= '0' && *c <= '9') + bitstart = (bitstart * 10) + *c++ - '0'; + + switch (*c) + { + case '-': + c++; + while (*c >= '0' && *c <= '9') + bitend = (bitend * 10) + *c++ - '0'; + + if (!bitend) + abort (); + + switch (*c) + { + case 'r': + { + unsigned long reg; + + reg = given >> bitstart; + reg &= (2u << (bitend - bitstart)) - 1; + + func (stream, "%s", score_regnames[reg]); + } + break; + case 'd': + { + unsigned long reg; + + reg = given >> bitstart; + reg &= (2u << (bitend - bitstart)) - 1; + + func (stream, "%ld", reg); + } + break; + case 'i': + { + long reg; + + reg = given >> bitstart; + reg &= (2u << (bitend - bitstart)) - 1; + reg = ((reg ^ (1 << (bitend - bitstart))) + - (1 << (bitend - bitstart))); + + if (((given & insn->mask) == 0x0c00000a) /* ldc1 */ + || ((given & insn->mask) == 0x0c000012) /* ldc2 */ + || ((given & insn->mask) == 0x0c00001c) /* ldc3 */ + || ((given & insn->mask) == 0x0c00000b) /* stc1 */ + || ((given & insn->mask) == 0x0c000013) /* stc2 */ + || ((given & insn->mask) == 0x0c00001b)) /* stc3 */ + reg *= 4; + + func (stream, "%ld", reg); + } + break; + case 'x': + { + unsigned long reg; + + reg = given >> bitstart; + reg &= (2u << (bitend - bitstart)) - 1; + + func (stream, "%lx", reg); + } + break; + default: + abort (); + } + break; + case '`': + c++; + if ((given & (1u << bitstart)) == 0) + func (stream, "%c", *c); + break; + case '\'': + c++; + if ((given & (1u << bitstart)) != 0) + func (stream, "%c", *c); + break; + default: + abort (); + } + break; + } + default: abort (); - } - } - else - func (stream, "%c", *c); - } - return 4; - } + } + } + else + func (stream, "%c", *c); + } + return 4; + } } #if (SCORE_SIMULATOR_ACTIVE) @@ -723,135 +724,135 @@ print_insn_score16 (bfd_vma pc, struct disassemble_info *info, long given) for (insn = score_opcodes; insn->assembler; insn++) { if (!(insn->mask & 0xffff0000) && (given & insn->mask) == insn->value) - { - char *c = insn->assembler; - - info->bytes_per_chunk = 2; - info->bytes_per_line = 4; - given &= 0xffff; - - for (; *c; c++) - { - if (*c == '%') - { - switch (*++c) - { - - case 'j': - { - int target; - - if (info->flags & INSN_HAS_RELOC) - pc = 0; - - target = (pc & 0xfffff000) | (given & 0x00000ffe); - (*info->print_address_func) (target, info); - } - break; - case 'b': - { - /* Sign-extend a 9-bit number. */ -#define SEXT9(x) ((((x) & 0x1ff) ^ (~ 0xff)) + 0x100) - int disp = (given & 0xff) << 1; - int target = (pc + SEXT9 (disp)); - - (*info->print_address_func) (target, info); - } - break; - - case '0': - case '1': - case '2': - case '3': - case '4': - case '5': - case '6': - case '7': - case '8': - case '9': - { - int bitstart = *c++ - '0'; - int bitend = 0; - - while (*c >= '0' && *c <= '9') - bitstart = (bitstart * 10) + *c++ - '0'; - - switch (*c) - { - case '-': - { - long reg; - - c++; - while (*c >= '0' && *c <= '9') - bitend = (bitend * 10) + *c++ - '0'; - if (!bitend) - abort (); - reg = given >> bitstart; - reg &= (2 << (bitend - bitstart)) - 1; - switch (*c) - { - case 'R': - func (stream, "%s", score_regnames[reg + 16]); - break; - case 'r': - func (stream, "%s", score_regnames[reg]); - break; - case 'd': - if (*(c + 1) == '\0') - func (stream, "%ld", reg); - else - { - c++; - if (*c == '1') - func (stream, "%ld", reg << 1); - else if (*c == '2') - func (stream, "%ld", reg << 2); - } - break; - - case 'x': - if (*(c + 1) == '\0') - func (stream, "%lx", reg); - else - { - c++; - if (*c == '1') - func (stream, "%lx", reg << 1); - else if (*c == '2') - func (stream, "%lx", reg << 2); - } - break; - case 'i': - reg = ((reg ^ (1 << bitend)) - (1 << bitend)); - func (stream, "%ld", reg); - break; - default: - abort (); - } - } - break; - - case '\'': - c++; - if ((given & (1 << bitstart)) != 0) - func (stream, "%c", *c); - break; - default: - abort (); - } - } - break; - default: - abort (); - } - } - else - func (stream, "%c", *c); - } - - return 2; - } + { + char *c = insn->assembler; + + info->bytes_per_chunk = 2; + info->bytes_per_line = 4; + given &= 0xffff; + + for (; *c; c++) + { + if (*c == '%') + { + switch (*++c) + { + + case 'j': + { + int target; + + if (info->flags & INSN_HAS_RELOC) + pc = 0; + + target = (pc & 0xfffff000) | (given & 0x00000ffe); + (*info->print_address_func) (target, info); + } + break; + case 'b': + { + /* Sign-extend a 9-bit number. */ +#define SEXT9(x) ((((x) & 0x1ff) ^ (~ 0xff)) + 0x100) + int disp = (given & 0xff) << 1; + int target = (pc + SEXT9 (disp)); + + (*info->print_address_func) (target, info); + } + break; + + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + { + int bitstart = *c++ - '0'; + int bitend = 0; + + while (*c >= '0' && *c <= '9') + bitstart = (bitstart * 10) + *c++ - '0'; + + switch (*c) + { + case '-': + { + long reg; + + c++; + while (*c >= '0' && *c <= '9') + bitend = (bitend * 10) + *c++ - '0'; + if (!bitend) + abort (); + reg = given >> bitstart; + reg &= (2u << (bitend - bitstart)) - 1; + switch (*c) + { + case 'R': + func (stream, "%s", score_regnames[reg + 16]); + break; + case 'r': + func (stream, "%s", score_regnames[reg]); + break; + case 'd': + if (*(c + 1) == '\0') + func (stream, "%ld", reg); + else + { + c++; + if (*c == '1') + func (stream, "%ld", reg << 1); + else if (*c == '2') + func (stream, "%ld", reg << 2); + } + break; + + case 'x': + if (*(c + 1) == '\0') + func (stream, "%lx", reg); + else + { + c++; + if (*c == '1') + func (stream, "%lx", reg << 1); + else if (*c == '2') + func (stream, "%lx", reg << 2); + } + break; + case 'i': + reg = ((reg ^ (1 << bitend)) - (1 << bitend)); + func (stream, "%ld", reg); + break; + default: + abort (); + } + } + break; + + case '\'': + c++; + if ((given & (1u << bitstart)) != 0) + func (stream, "%c", *c); + break; + default: + abort (); + } + } + break; + default: + abort (); + } + } + else + func (stream, "%c", *c); + } + + return 2; + } } #if (SCORE_SIMULATOR_ACTIVE) func (stream, _("")); @@ -861,7 +862,6 @@ print_insn_score16 (bfd_vma pc, struct disassemble_info *info, long given) abort (); } -/*****************************************************************************/ /* s3_s7: exported functions. */ /* NOTE: There are no checks in these routines that @@ -870,7 +870,7 @@ int s7_print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little) { unsigned char b[4]; - long given; + unsigned long given; long ridparity; int status; bfd_boolean insn_pce_p = FALSE; @@ -888,14 +888,14 @@ s7_print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little) else { info->bytes_per_chunk = 4; - status = info->read_memory_func (pc, (bfd_byte *) & b[0], 4, info); + status = info->read_memory_func (pc, (bfd_byte *) &b[0], 4, info); if (status != 0) - { - info->bytes_per_chunk = 2; - status = info->read_memory_func (pc, (bfd_byte *) b, 2, info); - b[3] = b[2] = 0; - insn_16_p = TRUE; - } + { + info->bytes_per_chunk = 2; + status = info->read_memory_func (pc, (bfd_byte *) b, 2, info); + b[3] = b[2] = 0; + insn_16_p = TRUE; + } } if (status != 0) @@ -905,13 +905,9 @@ s7_print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little) } if (little) - { - given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24); - } + given = b[0] | b[1] << 8 | b[2] << 16 | (unsigned) b[3] << 24; else - { - given = (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | (b[3]); - } + given = (unsigned) b[0] << 24 | b[1] << 16 | b[2] << 8 | b[3]; if ((given & 0x80008000) == 0x80008000) { @@ -919,25 +915,17 @@ s7_print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little) insn_16_p = FALSE; } else if ((given & 0x8000) == 0x8000) - { - insn_pce_p = TRUE; - } + insn_pce_p = TRUE; else - { - insn_16_p = TRUE; - } + insn_16_p = TRUE; /* 16 bit instruction. */ if (insn_16_p) { if (little) - { - given = b[0] | (b[1] << 8); - } + given = b[0] | (b[1] << 8); else - { - given = (b[0] << 8) | b[1]; - } + given = (b[0] << 8) | b[1]; status = print_insn_score16 (pc, info, given); } @@ -952,7 +940,8 @@ s7_print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little) status = print_insn_score16 (pc, info, given); print_insn_parallel_sym (info); status += print_insn_score16 (pc, info, other); - /* disassemble_bytes() will output 4 byte per chunk for pce instructio. */ + /* disassemble_bytes() will output 4 byte per chunk for pce + instruction. */ info->bytes_per_chunk = 4; } /* 32 bit instruction. */ @@ -967,5 +956,3 @@ s7_print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little) return status; } - -/*****************************************************************************/