X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=bfd%2Fbfd-in2.h;h=5b0417634235d4b73b90bac5f9b35ac7b1182edb;hb=574b0b3165dfa8ce1bdc2a41ae73148b6d8ea6be;hp=275f9779bb841f89b6b2df85ccddad1beee1ea24;hpb=df7b86aa4cb63ce86e60949b8160438bc0f9e389;p=deliverable%2Fbinutils-gdb.git diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h index 275f9779bb..5b04176342 100644 --- a/bfd/bfd-in2.h +++ b/bfd/bfd-in2.h @@ -32,7 +32,8 @@ #ifndef __BFD_H_SEEN__ #define __BFD_H_SEEN__ -#ifndef PACKAGE +/* PR 14072: Ensure that config.h is included first. */ +#if !defined PACKAGE && !defined PACKAGE_VERSION #error config.h must be included before this header #endif @@ -68,7 +69,7 @@ extern "C" { problem for example when trying to use STRING_COMMA_LEN to build the arguments to the strncmp() macro. Hence this alternative definition of strncmp is provided here. - + Note - these macros do NOT work if STR2 is not a constant string. */ #define CONST_STRNEQ(STR1,STR2) (strncmp ((STR1), (STR2), sizeof (STR2) - 1) == 0) /* strcpy() can have a similar problem, but since we know we are @@ -654,6 +655,8 @@ extern struct bfd_link_needed_list *bfd_elf_get_needed_list (bfd *, struct bfd_link_info *); extern bfd_boolean bfd_elf_get_bfd_needed_list (bfd *, struct bfd_link_needed_list **); +extern bfd_boolean bfd_elf_stack_segment_size (bfd *, struct bfd_link_info *, + const char *, bfd_vma); extern bfd_boolean bfd_elf_size_dynamic_sections (bfd *, const char *, const char *, const char *, const char *, const char *, const char * const *, struct bfd_link_info *, struct bfd_section **); @@ -704,7 +707,8 @@ extern int bfd_get_elf_phdrs the remote memory. */ extern bfd *bfd_elf_bfd_from_remote_memory (bfd *templ, bfd_vma ehdr_vma, bfd_vma *loadbasep, - int (*target_read_memory) (bfd_vma vma, bfd_byte *myaddr, int len)); + int (*target_read_memory) (bfd_vma vma, bfd_byte *myaddr, + bfd_size_type len)); extern struct bfd_section *_bfd_elf_tls_setup (bfd *, struct bfd_link_info *); @@ -933,6 +937,32 @@ extern unsigned int _bfd_elf_ppc_at_tls_transform extern unsigned int _bfd_elf_ppc_at_tprel_transform (unsigned int, unsigned int); +extern void bfd_elf64_aarch64_init_maps + (bfd *); + +void bfd_elf64_aarch64_set_options + (bfd *, struct bfd_link_info *, int, int, int); + +/* ELF AArch64 mapping symbol support. */ +#define BFD_AARCH64_SPECIAL_SYM_TYPE_MAP (1 << 0) +#define BFD_AARCH64_SPECIAL_SYM_TYPE_TAG (1 << 1) +#define BFD_AARCH64_SPECIAL_SYM_TYPE_OTHER (1 << 2) +#define BFD_AARCH64_SPECIAL_SYM_TYPE_ANY (~0) +extern bfd_boolean bfd_is_aarch64_special_symbol_name + (const char * name, int type); + +/* AArch64 stub generation support. Called from the linker. */ +extern int elf64_aarch64_setup_section_lists + (bfd *, struct bfd_link_info *); +extern void elf64_aarch64_next_input_section + (struct bfd_link_info *, struct bfd_section *); +extern bfd_boolean elf64_aarch64_size_stubs + (bfd *, bfd *, struct bfd_link_info *, bfd_signed_vma, + struct bfd_section * (*) (const char *, struct bfd_section *), + void (*) (void)); +extern bfd_boolean elf64_aarch64_build_stubs + (struct bfd_link_info *); + /* TI COFF load page support. */ extern void bfd_ticoff_set_section_load_page (struct bfd_section *, int); @@ -1532,12 +1562,12 @@ typedef struct bfd_section } asection; /* Relax table contains information about instructions which can - be removed by relaxation -- replacing a long address with a + be removed by relaxation -- replacing a long address with a short address. */ struct relax_table { /* Address where bytes may be deleted. */ bfd_vma addr; - + /* Number of bytes to be deleted. */ int size; }; @@ -1545,7 +1575,7 @@ struct relax_table { /* These sections are global, and are managed by BFD. The application and target back end are not permitted to change the values in these sections. */ -extern asection std_section[4]; +extern asection _bfd_std_section[4]; #define BFD_ABS_SECTION_NAME "*ABS*" #define BFD_UND_SECTION_NAME "*UND*" @@ -1553,13 +1583,13 @@ extern asection std_section[4]; #define BFD_IND_SECTION_NAME "*IND*" /* Pointer to the common section. */ -#define bfd_com_section_ptr (&std_section[0]) +#define bfd_com_section_ptr (&_bfd_std_section[0]) /* Pointer to the undefined section. */ -#define bfd_und_section_ptr (&std_section[1]) +#define bfd_und_section_ptr (&_bfd_std_section[1]) /* Pointer to the absolute section. */ -#define bfd_abs_section_ptr (&std_section[2]) +#define bfd_abs_section_ptr (&_bfd_std_section[2]) /* Pointer to the indirect section. */ -#define bfd_ind_section_ptr (&std_section[3]) +#define bfd_ind_section_ptr (&_bfd_std_section[3]) #define bfd_is_und_section(sec) ((sec) == bfd_und_section_ptr) #define bfd_is_abs_section(sec) ((sec) == bfd_abs_section_ptr) @@ -1703,6 +1733,10 @@ void bfd_section_list_clear (bfd *); asection *bfd_get_section_by_name (bfd *abfd, const char *name); +asection *bfd_get_next_section_by_name (asection *sec); + +asection *bfd_get_linker_section (bfd *abfd, const char *name); + asection *bfd_get_section_by_name_if (bfd *abfd, const char *name, @@ -1842,7 +1876,7 @@ enum bfd_architecture #define bfd_mach_sparc_64bit_p(mach) \ ((mach) >= bfd_mach_sparc_v9 && (mach) != bfd_mach_sparc_v8plusb) bfd_arch_spu, /* PowerPC SPU */ -#define bfd_mach_spu 256 +#define bfd_mach_spu 256 bfd_arch_mips, /* MIPS Rxxxx */ #define bfd_mach_mips3000 3000 #define bfd_mach_mips3900 3900 @@ -1858,6 +1892,7 @@ enum bfd_architecture #define bfd_mach_mips5000 5000 #define bfd_mach_mips5400 5400 #define bfd_mach_mips5500 5500 +#define bfd_mach_mips5900 5900 #define bfd_mach_mips6000 6000 #define bfd_mach_mips7000 7000 #define bfd_mach_mips8000 8000 @@ -2020,11 +2055,13 @@ enum bfd_architecture bfd_arch_tic6x, /* Texas Instruments TMS320C6X */ bfd_arch_tic80, /* TI TMS320c80 (MVP) */ bfd_arch_v850, /* NEC V850 */ + bfd_arch_v850_rh850,/* NEC V850 (using RH850 ABI) */ #define bfd_mach_v850 1 #define bfd_mach_v850e 'E' #define bfd_mach_v850e1 '1' #define bfd_mach_v850e2 0x4532 #define bfd_mach_v850e2v3 0x45325633 +#define bfd_mach_v850e3v5 0x45335635 /* ('E'|'3'|'V'|'5') */ bfd_arch_arc, /* ARC Cores */ #define bfd_mach_arc_5 5 #define bfd_mach_arc_6 6 @@ -2060,6 +2097,8 @@ enum bfd_architecture #define bfd_mach_mep 1 #define bfd_mach_mep_h1 0x6831 #define bfd_mach_mep_c5 0x6335 + bfd_arch_metag, +#define bfd_mach_metag 1 bfd_arch_ia64, /* HP/Intel ia64 */ #define bfd_mach_ia64_elf64 64 #define bfd_mach_ia64_elf32 32 @@ -2114,7 +2153,7 @@ enum bfd_architecture bfd_arch_s390, /* IBM s390 */ #define bfd_mach_s390_31 31 #define bfd_mach_s390_64 64 - bfd_arch_score, /* Sunplus score */ + bfd_arch_score, /* Sunplus score */ #define bfd_mach_score3 3 #define bfd_mach_score7 7 bfd_arch_openrisc, /* OpenRISC */ @@ -2158,6 +2197,8 @@ enum bfd_architecture #define bfd_mach_tilepro 1 #define bfd_mach_tilegx 1 #define bfd_mach_tilegx32 2 + bfd_arch_aarch64, /* AArch64 */ +#define bfd_mach_aarch64 0 bfd_arch_last }; @@ -2483,6 +2524,10 @@ The 24-bit relocation is used in some Intel 960 configurations. */ BFD_RELOC_HI16_S_PLTOFF, BFD_RELOC_8_PLTOFF, +/* Size relocations. */ + BFD_RELOC_SIZE32, + BFD_RELOC_SIZE64, + /* Relocations used by 68K ELF. */ BFD_RELOC_68K_GLOB_DAT, BFD_RELOC_68K_JMP_SLOT, @@ -3958,6 +4003,46 @@ short offset into 11 bits. */ BFD_RELOC_MEP_GNU_VTENTRY, +/* Imagination Technologies Meta relocations. */ + BFD_RELOC_METAG_HIADDR16, + BFD_RELOC_METAG_LOADDR16, + BFD_RELOC_METAG_RELBRANCH, + BFD_RELOC_METAG_GETSETOFF, + BFD_RELOC_METAG_HIOG, + BFD_RELOC_METAG_LOOG, + BFD_RELOC_METAG_REL8, + BFD_RELOC_METAG_REL16, + BFD_RELOC_METAG_HI16_GOTOFF, + BFD_RELOC_METAG_LO16_GOTOFF, + BFD_RELOC_METAG_GETSET_GOTOFF, + BFD_RELOC_METAG_GETSET_GOT, + BFD_RELOC_METAG_HI16_GOTPC, + BFD_RELOC_METAG_LO16_GOTPC, + BFD_RELOC_METAG_HI16_PLT, + BFD_RELOC_METAG_LO16_PLT, + BFD_RELOC_METAG_RELBRANCH_PLT, + BFD_RELOC_METAG_GOTOFF, + BFD_RELOC_METAG_PLT, + BFD_RELOC_METAG_COPY, + BFD_RELOC_METAG_JMP_SLOT, + BFD_RELOC_METAG_RELATIVE, + BFD_RELOC_METAG_GLOB_DAT, + BFD_RELOC_METAG_TLS_GD, + BFD_RELOC_METAG_TLS_LDM, + BFD_RELOC_METAG_TLS_LDO_HI16, + BFD_RELOC_METAG_TLS_LDO_LO16, + BFD_RELOC_METAG_TLS_LDO, + BFD_RELOC_METAG_TLS_IE, + BFD_RELOC_METAG_TLS_IENONPIC, + BFD_RELOC_METAG_TLS_IENONPIC_HI16, + BFD_RELOC_METAG_TLS_IENONPIC_LO16, + BFD_RELOC_METAG_TLS_TPOFF, + BFD_RELOC_METAG_TLS_DTPMOD, + BFD_RELOC_METAG_TLS_DTPOFF, + BFD_RELOC_METAG_TLS_LE, + BFD_RELOC_METAG_TLS_LE_HI16, + BFD_RELOC_METAG_TLS_LE_LO16, + /* These are relocations for the GETA instruction. */ BFD_RELOC_MMIX_GETA, BFD_RELOC_MMIX_GETA_1, @@ -4057,7 +4142,7 @@ of 32 bit value) into 8 bit immediate value of LDI insn. */ command address) into 8 bit immediate value of LDI insn. */ BFD_RELOC_AVR_LO8_LDI_PM, -/* This is a 16 bit reloc for the AVR that stores 8 bit value +/* This is a 16 bit reloc for the AVR that stores 8 bit value (command address) into 8 bit immediate value of LDI insn. If the address is beyond the 128k boundary, the linker inserts a jump stub for this reloc in the lower 128k. */ @@ -4288,6 +4373,9 @@ in .byte hlo8(symbol) */ BFD_RELOC_390_GOTPLT20, BFD_RELOC_390_TLS_GOTIE20, +/* STT_GNU_IFUNC relocation. */ + BFD_RELOC_390_IRELATIVE, + /* Score relocations Low 16 bit for load/store */ BFD_RELOC_SCORE_GPREL15, @@ -4978,52 +5066,52 @@ the linker could optimize the movq to a leaq if possible. */ /* Same as BFD_RELOC_32_PCREL but with an implicit -4 addend. */ BFD_RELOC_MACH_O_X86_64_PCREL32_4, -/* This is a 32 bit reloc for the microblaze that stores the +/* This is a 32 bit reloc for the microblaze that stores the low 16 bits of a value */ BFD_RELOC_MICROBLAZE_32_LO, -/* This is a 32 bit pc-relative reloc for the microblaze that +/* This is a 32 bit pc-relative reloc for the microblaze that stores the low 16 bits of a value */ BFD_RELOC_MICROBLAZE_32_LO_PCREL, -/* This is a 32 bit reloc for the microblaze that stores a +/* This is a 32 bit reloc for the microblaze that stores a value relative to the read-only small data area anchor */ BFD_RELOC_MICROBLAZE_32_ROSDA, -/* This is a 32 bit reloc for the microblaze that stores a +/* This is a 32 bit reloc for the microblaze that stores a value relative to the read-write small data area anchor */ BFD_RELOC_MICROBLAZE_32_RWSDA, -/* This is a 32 bit reloc for the microblaze to handle +/* This is a 32 bit reloc for the microblaze to handle expressions of the form "Symbol Op Symbol" */ BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM, -/* This is a 64 bit reloc that stores the 32 bit pc relative -value in two words (with an imm instruction). No relocation is +/* This is a 64 bit reloc that stores the 32 bit pc relative +value in two words (with an imm instruction). No relocation is done here - only used for relaxing */ BFD_RELOC_MICROBLAZE_64_NONE, -/* This is a 64 bit reloc that stores the 32 bit pc relative +/* This is a 64 bit reloc that stores the 32 bit pc relative value in two words (with an imm instruction). The relocation is PC-relative GOT offset */ BFD_RELOC_MICROBLAZE_64_GOTPC, -/* This is a 64 bit reloc that stores the 32 bit pc relative +/* This is a 64 bit reloc that stores the 32 bit pc relative value in two words (with an imm instruction). The relocation is GOT offset */ BFD_RELOC_MICROBLAZE_64_GOT, -/* This is a 64 bit reloc that stores the 32 bit pc relative +/* This is a 64 bit reloc that stores the 32 bit pc relative value in two words (with an imm instruction). The relocation is PC-relative offset into PLT */ BFD_RELOC_MICROBLAZE_64_PLT, -/* This is a 64 bit reloc that stores the 32 bit GOT relative +/* This is a 64 bit reloc that stores the 32 bit GOT relative value in two words (with an imm instruction). The relocation is relative offset from _GLOBAL_OFFSET_TABLE_ */ BFD_RELOC_MICROBLAZE_64_GOTOFF, -/* This is a 32 bit reloc that stores the 32 bit GOT relative +/* This is a 32 bit reloc that stores the 32 bit GOT relative value in a word. The relocation is relative offset from */ BFD_RELOC_MICROBLAZE_32_GOTOFF, @@ -5031,6 +5119,258 @@ value in a word. The relocation is relative offset from */ the dynamic object into the runtime process image. */ BFD_RELOC_MICROBLAZE_COPY, +/* Unused Reloc */ + BFD_RELOC_MICROBLAZE_64_TLS, + +/* This is a 64 bit reloc that stores the 32 bit GOT relative value +of the GOT TLS GD info entry in two words (with an imm instruction). The +relocation is GOT offset. */ + BFD_RELOC_MICROBLAZE_64_TLSGD, + +/* This is a 64 bit reloc that stores the 32 bit GOT relative value +of the GOT TLS LD info entry in two words (with an imm instruction). The +relocation is GOT offset. */ + BFD_RELOC_MICROBLAZE_64_TLSLD, + +/* This is a 32 bit reloc that stores the Module ID to GOT(n). */ + BFD_RELOC_MICROBLAZE_32_TLSDTPMOD, + +/* This is a 32 bit reloc that stores TLS offset to GOT(n+1). */ + BFD_RELOC_MICROBLAZE_32_TLSDTPREL, + +/* This is a 32 bit reloc for storing TLS offset to two words (uses imm +instruction) */ + BFD_RELOC_MICROBLAZE_64_TLSDTPREL, + +/* This is a 64 bit reloc that stores 32-bit thread pointer relative offset +to two words (uses imm instruction). */ + BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL, + +/* This is a 64 bit reloc that stores 32-bit thread pointer relative offset +to two words (uses imm instruction). */ + BFD_RELOC_MICROBLAZE_64_TLSTPREL, + +/* AArch64 ADD immediate instruction, holding bits 0 to 11 of the address. +Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */ + BFD_RELOC_AARCH64_ADD_LO12, + +/* AArch64 Load Literal instruction, holding a 19 bit PC relative word +offset of the global offset table entry for a symbol. The lowest two +bits must be zero and are not stored in the instruction, giving a 21 +bit signed byte offset. This relocation type requires signed overflow +checking. */ + BFD_RELOC_AARCH64_GOT_LD_PREL19, + +/* Get to the page base of the global offset table entry for a symbol as +part of an ADRP instruction using a 21 bit PC relative value.Used in +conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC. */ + BFD_RELOC_AARCH64_ADR_GOT_PAGE, + +/* AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page +offset, giving a 4KB aligned page base address. */ + BFD_RELOC_AARCH64_ADR_HI21_PCREL, + +/* AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page +offset, giving a 4KB aligned page base address, but with no overflow +checking. */ + BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL, + +/* AArch64 ADR instruction, holding a simple 21 bit pc-relative byte offset. */ + BFD_RELOC_AARCH64_ADR_LO21_PCREL, + +/* AArch64 19 bit pc-relative conditional branch and compare & branch. +The lowest two bits must be zero and are not stored in the instruction, +giving a 21 bit signed byte offset. */ + BFD_RELOC_AARCH64_BRANCH19, + +/* AArch64 26 bit pc-relative unconditional branch and link. +The lowest two bits must be zero and are not stored in the instruction, +giving a 28 bit signed byte offset. */ + BFD_RELOC_AARCH64_CALL26, + +/* AArch64 pseudo relocation code to be used internally by the AArch64 +assembler and not (currently) written to any object files. */ + BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP, + +/* AArch64 26 bit pc-relative unconditional branch. +The lowest two bits must be zero and are not stored in the instruction, +giving a 28 bit signed byte offset. */ + BFD_RELOC_AARCH64_JUMP26, + +/* AArch64 Load Literal instruction, holding a 19 bit pc-relative word +offset. The lowest two bits must be zero and are not stored in the +instruction, giving a 21 bit signed byte offset. */ + BFD_RELOC_AARCH64_LD_LO19_PCREL, + +/* Unsigned 12 bit byte offset for 64 bit load/store from the page of +the GOT entry for this symbol. Used in conjunction with +BFD_RELOC_AARCH64_ADR_GOTPAGE. */ + BFD_RELOC_AARCH64_LD64_GOT_LO12_NC, + +/* AArch64 unspecified load/store instruction, holding bits 0 to 11 of the +address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */ + BFD_RELOC_AARCH64_LDST_LO12, + +/* AArch64 8-bit load/store instruction, holding bits 0 to 11 of the +address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */ + BFD_RELOC_AARCH64_LDST8_LO12, + +/* AArch64 16-bit load/store instruction, holding bits 0 to 11 of the +address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */ + BFD_RELOC_AARCH64_LDST16_LO12, + +/* AArch64 32-bit load/store instruction, holding bits 0 to 11 of the +address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */ + BFD_RELOC_AARCH64_LDST32_LO12, + +/* AArch64 64-bit load/store instruction, holding bits 0 to 11 of the +address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */ + BFD_RELOC_AARCH64_LDST64_LO12, + +/* AArch64 128-bit load/store instruction, holding bits 0 to 11 of the +address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. */ + BFD_RELOC_AARCH64_LDST128_LO12, + +/* AArch64 MOV[NZK] instruction with most significant bits 0 to 15 +of an unsigned address/value. */ + BFD_RELOC_AARCH64_MOVW_G0, + +/* AArch64 MOV[NZ] instruction with most significant bits 0 to 15 +of a signed value. Changes instruction to MOVZ or MOVN depending on the +value's sign. */ + BFD_RELOC_AARCH64_MOVW_G0_S, + +/* AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of +an address/value. No overflow checking. */ + BFD_RELOC_AARCH64_MOVW_G0_NC, + +/* AArch64 MOV[NZK] instruction with most significant bits 16 to 31 +of an unsigned address/value. */ + BFD_RELOC_AARCH64_MOVW_G1, + +/* AArch64 MOV[NZK] instruction with less significant bits 16 to 31 +of an address/value. No overflow checking. */ + BFD_RELOC_AARCH64_MOVW_G1_NC, + +/* AArch64 MOV[NZ] instruction with most significant bits 16 to 31 +of a signed value. Changes instruction to MOVZ or MOVN depending on the +value's sign. */ + BFD_RELOC_AARCH64_MOVW_G1_S, + +/* AArch64 MOV[NZK] instruction with most significant bits 32 to 47 +of an unsigned address/value. */ + BFD_RELOC_AARCH64_MOVW_G2, + +/* AArch64 MOV[NZK] instruction with less significant bits 32 to 47 +of an address/value. No overflow checking. */ + BFD_RELOC_AARCH64_MOVW_G2_NC, + +/* AArch64 MOV[NZ] instruction with most significant bits 32 to 47 +of a signed value. Changes instruction to MOVZ or MOVN depending on the +value's sign. */ + BFD_RELOC_AARCH64_MOVW_G2_S, + +/* AArch64 MOV[NZK] instruction with most signficant bits 48 to 64 +of a signed or unsigned address/value. */ + BFD_RELOC_AARCH64_MOVW_G3, + +/* AArch64 TLS relocation. */ + BFD_RELOC_AARCH64_TLSDESC, + +/* AArch64 TLS DESC relocation. */ + BFD_RELOC_AARCH64_TLSDESC_ADD, + +/* AArch64 TLS DESC relocation. */ + BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC, + +/* AArch64 TLS DESC relocation. */ + BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE, + +/* AArch64 TLS DESC relocation. */ + BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21, + +/* AArch64 TLS DESC relocation. */ + BFD_RELOC_AARCH64_TLSDESC_CALL, + +/* AArch64 TLS DESC relocation. */ + BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC, + +/* AArch64 TLS DESC relocation. */ + BFD_RELOC_AARCH64_TLSDESC_LD64_PREL19, + +/* AArch64 TLS DESC relocation. */ + BFD_RELOC_AARCH64_TLSDESC_LDR, + +/* AArch64 TLS DESC relocation. */ + BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC, + +/* AArch64 TLS DESC relocation. */ + BFD_RELOC_AARCH64_TLSDESC_OFF_G1, + +/* Unsigned 12 bit byte offset to global offset table entry for a symbols +tls_index structure. Used in conjunction with +BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21. */ + BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC, + +/* Get to the page base of the global offset table entry for a symbols +tls_index structure as part of an adrp instruction using a 21 bit PC +relative value. Used in conjunction with +BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC. */ + BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21, + +/* AArch64 TLS INITIAL EXEC relocation. */ + BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21, + +/* AArch64 TLS INITIAL EXEC relocation. */ + BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19, + +/* AArch64 TLS INITIAL EXEC relocation. */ + BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC, + +/* AArch64 TLS INITIAL EXEC relocation. */ + BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC, + +/* AArch64 TLS INITIAL EXEC relocation. */ + BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1, + +/* AArch64 TLS LOCAL EXEC relocation. */ + BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12, + +/* AArch64 TLS LOCAL EXEC relocation. */ + BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12, + +/* AArch64 TLS LOCAL EXEC relocation. */ + BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC, + +/* AArch64 TLS LOCAL EXEC relocation. */ + BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0, + +/* AArch64 TLS LOCAL EXEC relocation. */ + BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC, + +/* AArch64 TLS LOCAL EXEC relocation. */ + BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1, + +/* AArch64 TLS LOCAL EXEC relocation. */ + BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC, + +/* AArch64 TLS LOCAL EXEC relocation. */ + BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2, + +/* AArch64 TLS relocation. */ + BFD_RELOC_AARCH64_TLS_DTPMOD64, + +/* AArch64 TLS relocation. */ + BFD_RELOC_AARCH64_TLS_DTPREL64, + +/* AArch64 TLS relocation. */ + BFD_RELOC_AARCH64_TLS_TPREL64, + +/* AArch64 14 bit pc-relative test bit and branch. +The lowest two bits must be zero and are not stored in the instruction, +giving a 16 bit signed byte offset. */ + BFD_RELOC_AARCH64_TSTBR14, + /* Tilera TILEPro Relocations. */ BFD_RELOC_TILEPRO_COPY, BFD_RELOC_TILEPRO_GLOB_DAT, @@ -5170,10 +5510,18 @@ the dynamic object into the runtime process image. */ BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PCREL, BFD_RELOC_TILEGX_IMM16_X0_HW0_GOT, BFD_RELOC_TILEGX_IMM16_X1_HW0_GOT, + BFD_RELOC_TILEGX_IMM16_X0_HW0_PLT_PCREL, + BFD_RELOC_TILEGX_IMM16_X1_HW0_PLT_PCREL, + BFD_RELOC_TILEGX_IMM16_X0_HW1_PLT_PCREL, + BFD_RELOC_TILEGX_IMM16_X1_HW1_PLT_PCREL, + BFD_RELOC_TILEGX_IMM16_X0_HW2_PLT_PCREL, + BFD_RELOC_TILEGX_IMM16_X1_HW2_PLT_PCREL, BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_GOT, BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_GOT, BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_GOT, BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_GOT, + BFD_RELOC_TILEGX_IMM16_X0_HW3_PLT_PCREL, + BFD_RELOC_TILEGX_IMM16_X1_HW3_PLT_PCREL, BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_GD, BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_GD, BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE, @@ -5188,6 +5536,12 @@ the dynamic object into the runtime process image. */ BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_GD, BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_IE, BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_IE, + BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL, + BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL, + BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL, + BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL, + BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL, + BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL, BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_IE, BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_IE, BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_IE, @@ -5801,6 +6155,11 @@ bfd_boolean bfd_set_private_flags (bfd *abfd, flagword flags); BFD_SEND (abfd, _bfd_find_nearest_line, \ (abfd, sec, syms, off, file, func, line)) +#define bfd_find_nearest_line_discriminator(abfd, sec, syms, off, file, func, \ + line, disc) \ + BFD_SEND (abfd, _bfd_find_nearest_line_discriminator, \ + (abfd, sec, syms, off, file, func, line, disc)) + #define bfd_find_line(abfd, syms, sym, file, line) \ BFD_SEND (abfd, _bfd_find_line, \ (abfd, syms, sym, file, line)) @@ -5888,24 +6247,6 @@ extern bfd_byte *bfd_get_relocated_section_contents bfd_boolean bfd_alt_mach_code (bfd *abfd, int alternative); -struct bfd_preserve -{ - void *marker; - void *tdata; - flagword flags; - const struct bfd_arch_info *arch_info; - struct bfd_section *sections; - struct bfd_section *section_last; - unsigned int section_count; - struct bfd_hash_table section_htab; -}; - -bfd_boolean bfd_preserve_save (bfd *, struct bfd_preserve *); - -void bfd_preserve_restore (bfd *, struct bfd_preserve *); - -void bfd_preserve_finish (bfd *, struct bfd_preserve *); - bfd_vma bfd_emul_get_maxpagesize (const char *); void bfd_emul_set_maxpagesize (const char *, bfd_vma); @@ -6182,6 +6523,7 @@ typedef struct bfd_target NAME##_bfd_is_target_special_symbol, \ NAME##_get_lineno, \ NAME##_find_nearest_line, \ + _bfd_generic_find_nearest_line_discriminator, \ _bfd_generic_find_line, \ NAME##_find_inliner_info, \ NAME##_bfd_make_debug_symbol, \ @@ -6205,6 +6547,9 @@ typedef struct bfd_target bfd_boolean (*_bfd_find_nearest_line) (bfd *, struct bfd_section *, struct bfd_symbol **, bfd_vma, const char **, const char **, unsigned int *); + bfd_boolean (*_bfd_find_nearest_line_discriminator) + (bfd *, struct bfd_section *, struct bfd_symbol **, bfd_vma, + const char **, const char **, unsigned int *, unsigned int *); bfd_boolean (*_bfd_find_line) (bfd *, struct bfd_symbol **, struct bfd_symbol *, const char **, unsigned int *); @@ -6428,6 +6773,9 @@ bfd_boolean bfd_compress_section_contents bfd_boolean bfd_get_full_section_contents (bfd *abfd, asection *section, bfd_byte **ptr); +void bfd_cache_section_contents + (asection *sec, void *contents); + bfd_boolean bfd_is_section_compressed (bfd *abfd, asection *section);