X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=bfd%2Fcpu-ia64-opc.c;h=ba8ff769d0a94d4b9697d13690256cb956151496;hb=7a8238b0722bf53839a939fb30100ce3bb90def9;hp=85908294a00a4f86d0a817066afc729bbf71db61;hpb=b90efa5b79ac1524ec260f8eb89d1be37e0219a7;p=deliverable%2Fbinutils-gdb.git diff --git a/bfd/cpu-ia64-opc.c b/bfd/cpu-ia64-opc.c index 85908294a0..ba8ff769d0 100644 --- a/bfd/cpu-ia64-opc.c +++ b/bfd/cpu-ia64-opc.c @@ -1,4 +1,4 @@ -/* Copyright (C) 1998-2015 Free Software Foundation, Inc. +/* Copyright (C) 1998-2021 Free Software Foundation, Inc. Contributed by David Mosberger-Tang This file is part of BFD, the Binary File Descriptor library. @@ -86,7 +86,7 @@ ins_immu (const struct ia64_operand *self, ia64_insn value, ia64_insn *code) for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i) { new_insn |= ((value & ((((ia64_insn) 1) << self->field[i].bits) - 1)) - << self->field[i].shift); + << self->field[i].shift); value >>= self->field[i].bits; } if (value) @@ -170,7 +170,7 @@ ins_imms_scaled (const struct ia64_operand *self, ia64_insn value, for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i) { new_insn |= ((svalue & ((((ia64_insn) 1) << self->field[i].bits) - 1)) - << self->field[i].shift); + << self->field[i].shift); sign_bit = (svalue >> (self->field[i].bits - 1)) & 1; svalue >>= self->field[i].bits; } @@ -186,7 +186,7 @@ ext_imms_scaled (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep, int scale) { int i, bits = 0, total = 0; - BFD_HOST_64_BIT val = 0, sign; + BFD_HOST_U_64_BIT val = 0, sign; for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i) { @@ -196,10 +196,10 @@ ext_imms_scaled (const struct ia64_operand *self, ia64_insn code, total += bits; } /* sign extend: */ - sign = (BFD_HOST_64_BIT) 1 << (total - 1); + sign = (BFD_HOST_U_64_BIT) 1 << (total - 1); val = (val ^ sign) - sign; - *valuep = (val << scale); + *valuep = val << scale; return 0; } @@ -657,7 +657,7 @@ const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT] = "a branch target" }, { REL, ins_imms4, ext_imms4, 0, {{20, 13}, { 1, 36}}, 0, /* TGT25c */ "a branch target" }, - { REL, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0, /* TGT64 */ + { REL, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0, /* TGT64 */ "a branch target" }, { ABS, ins_const, ext_const, 0, {{0, 0}}, 0, /* LDXMOV */