X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=cpu%2FChangeLog;h=8755ee70a4d1e69515cb896307dd667db0247138;hb=62e6599087efba193e0156d89ee65fb74fc99cb2;hp=ee902521e9e7de4dba9e4e57a0faafab4604e09f;hpb=752937aa0c1fd7a314d13731f999e895b2560b68;p=deliverable%2Fbinutils-gdb.git diff --git a/cpu/ChangeLog b/cpu/ChangeLog index ee902521e9..8755ee70a4 100644 --- a/cpu/ChangeLog +++ b/cpu/ChangeLog @@ -1,3 +1,233 @@ +2019-12-17 Alan Modra + + * bpf.cpu (f-imm64): Avoid signed overflow. + +2019-12-16 Alan Modra + + * xstormy16.cpu (f-rel12a): Avoid signed overflow. + +2019-12-11 Alan Modra + + * epiphany.cpu (f-sdisp11): Don't sign extend with shifts. + * lm32.cpu (f-branch, f-vall): Likewise. + * m32.cpu (f-lab-8-16): Likewise. + +2019-12-11 Alan Modra + + * epiphany.cpu (f-simm8, f-simm24): Use multiply rather than + shift left to avoid UB on left shift of negative values. + +2019-11-20 Jose E. Marchesi + + * bpf.cpu: Fix comment describing the 128-bit instruction format. + +2019-09-09 Phil Blundell + + binutils 2.33 branch created. + +2019-07-19 Jose E. Marchesi + + * bpf.cpu (h-gpr): when disassembling, use %r0 and %r6 instead of + %a and %ctx. + +2019-07-15 Jose E. Marchesi + + * bpf.cpu (dlabs): New pmacro. + (dlind): Likewise. + +2019-07-14 Jose E. Marchesi + + * bpf.cpu (dlsi): ldabs and ldind instructions do not take an + explicit 'dst' argument. + +2019-06-13 Stafford Horne + + * or1korfpx.cpu (float-setflag-insn-base): Add 'sf' to symbol. + +2019-06-13 Stafford Horne + + * or1k.cpu (or64nd, or32nd, or1200nd): Update comment.a + (l-adrp): Improve comment. + +2019-06-13 Stafford Horne + + * or1korfpx.cpu (insn-opcode-float-regreg): Add SFUEQ_S, SFUNE_S, + SFUGT_S, SFUGE_S, SFULT_S, SFULE_S, SFUN_S, SFUEQ_D, SFUNE_D, SFUGT_D, + SFUGE_D, SFULT_D, SFULE_D, SFUN_D opcodes. + (float-setflag-insn-base): New pmacro based on float-setflag-insn. + (float-setflag-symantics, float-setflag-unordered-cmp-symantics, + float-setflag-unordered-symantics): New pmacro for instruction + symantics. + (float-setflag-insn): Update to use float-setflag-insn-base. + (float-setflag-unordered-insn): New pmacro for generating instructions. + +2019-06-13 Andrey Bacherov + Stafford Horne + + * or1k.cpu (ORFPX64A32-MACHS): New pmacro. + (ORFPX-MACHS): Removed pmacro. + * or1k.opc (or1k_cgen_insn_supported): New function. + (CGEN_VALIDATE_INSN_SUPPORTED): Define macro. + (parse_regpair, print_regpair): New functions. + * or1kcommon.cpu (h-spr, spr-shift, spr-address, h-gpr): Reorder + and add comments. + (h-fdr): Update comment to indicate or64. + (reg-pair-reg-lo, reg-pair-reg-hi): New pmacros for register pairs. + (h-fd32r): New hardware for 64-bit fpu registers. + (h-i64r): New hardware for 64-bit int registers. + * or1korbis.cpu (f-resv-8-1): New field. + * or1korfpx.cpu (rDSF, rASF, rBSF): Update attribute to ORFPX32-MACHS. + (rDDF, rADF, rBDF): Update operand comment to indicate or64. + (f-rdoff-10-1, f-raoff-9-1, f-rboff-8-1): New fields. + (h-roff1): New hardware. + (double-field-and-ops mnemonic): New pmacro to generate operations + rDD32F, rAD32F, rBD32F, rDDI and rADI. + (float-regreg-insn): Update single precision generator to MACH + ORFPX32-MACHS. Add generator for or32 64-bit instructions. + (float-setflag-insn): Update single precision generator to MACH + ORFPX32-MACHS. Fix double instructions from single to double + precision. Add generator for or32 64-bit instructions. + (float-cust-insn cust-num): Update single precision generator to MACH + ORFPX32-MACHS. Add generator for or32 64-bit instructions. + (lf-rem-s, lf-itof-s, lf-ftoi-s, lf-madd-s): Update MACH to + ORFPX32-MACHS. + (lf-rem-d): Fix operation from mod to rem. + (lf-rem-d32, lf-itof-d32, lf-ftoi-d32, lf-madd-d32): New instruction. + (lf-itof-d): Fix operands from single to double. + (lf-ftoi-d): Update operand mode from DI to WI. + +2019-05-23 Jose E. Marchesi + + * bpf.cpu: New file. + * bpf.opc: Likewise. + +2018-06-24 Nick Clifton + + 2.32 branch created. + +2018-10-05 Richard Henderson + Stafford Horne + + * or1korbis.cpu (insn-opcode-mac): Add opcodes for MACU and MSBU. + (insn-opcode-alu-regreg): Add opcodes for MULD and MULDU. + (l-mul): Fix overflow support and indentation. + (l-mulu): Fix overflow support and indentation. + (l-muld, l-muldu, l-msbu, l-macu): New instructions. + (l-div); Remove incorrect carry behavior. + (l-divu): Fix carry and overflow behavior. + (l-mac): Add overflow support. + (l-msb, l-msbu): Add carry and overflow support. + +2018-10-05 Richard Henderson + + * or1k.opc (parse_disp26): Add support for plta() relocations. + (parse_disp21): New function. + (or1k_rclass): New enum. + (or1k_rtype): New enum. + (or1k_imm16_relocs): Define new PO and SPO relocation mappings. + (parse_reloc): Add new po(), gotpo() and gottppo() for LO13 relocations. + (parse_imm16): Add support for the new 21bit and 13bit relocations. + * or1korbis.cpu (f-disp26): Don't assume SI. + (f-disp21): New pc-relative 21-bit 13 shifted to right. + (insn-opcode): Add ADRP. + (l-adrp): New instruction. + +2018-10-05 Richard Henderson + + * or1k.opc: Add RTYPE_ enum. + (INVALID_STORE_RELOC): New string. + (or1k_imm16_relocs): New array array. + (parse_reloc): New static function that just does the parsing. + (parse_imm16): New static function for generic parsing. + (parse_simm16): Change to just call parse_imm16. + (parse_simm16_split): New function. + (parse_uimm16): Change to call parse_imm16. + (parse_uimm16_split): New function. + * or1korbis.cpu (simm16-split): Change to use new simm16_split. + (uimm16-split): Change to use new uimm16_split. + +2018-07-24 Alan Modra + + PR 23430 + * or1kcommon.cpu (spr-reg-indices): Fix description typo. + +2018-05-09 Sebastian Rasmussen + + * or1kcommon.cpu (spr-reg-info): Typo fix. + +2018-03-03 Alan Modra + + * frv.opc: Include opintl.h. + (add_next_to_vliw): Use opcodes_error_handler to print error. + Standardize error message. + (fr500_check_insn_major_constraints, frv_vliw_add_insn): Likewise. + +2018-01-13 Nick Clifton + + 2.30 branch created. + +2017-03-15 Stafford Horne + + * or1kcommon.cpu: Add pc set semantics to also update ppc. + +2016-10-06 Alan Modra + + * mep.opc (expand_string): Add fall through comment. + +2016-03-03 Alan Modra + + * fr30.cpu (f-m4): Replace bogus comment with a better guess + at what is really going on. + +2016-03-02 Alan Modra + + * fr30.cpu (f-m4): Replace -1 << 4 with -16. + +2016-02-02 Andrew Burgess + + * epiphany.opc (epiphany_print_insn): Set info->bytes_per_line to + a constant to better align disassembler output. + +2014-07-20 Stefan Kristiansson + + * or1korbis.cpu (l-msync, l-psync, l-csync): New instructions. + +2014-06-12 Alan Modra + + * or1k.opc: Whitespace fixes. + +2014-05-08 Stefan Kristiansson + + * or1korbis.cpu (h-atomic-reserve): New hardware. + (h-atomic-address): Likewise. + (insn-opcode): Add opcodes for LWA and SWA. + (atomic-reserve): New operand. + (atomic-address): Likewise. + (l-lwa, l-swa): New instructions. + (l-lbs): Fix typo in comment. + (store-insn): Clear atomic reserve on store to atomic-address. + Fix register names in fmt field. + +2014-04-22 Christian Svensson + + * openrisc.cpu: Delete. + * openrisc.opc: Delete. + * or1k.cpu: New file. + * or1k.opc: New file. + * or1kcommon.cpu: New file. + * or1korbis.cpu: New file. + * or1korfpx.cpu: New file. + +2013-12-07 Mike Frysinger + + * epiphany.opc: Remove +x file mode. + +2013-03-08 Yann Sionneau + + PR binutils/15241 + * lm32.cpu (Control and status registers): Add CFG2, PSW, + TLBVADDR, TLBPADDR and TLBBADVADDR. + 2012-11-30 Oleg Raikhman Joern Rennecke @@ -221,7 +451,7 @@ (dst32-16-16sa-Unprefixed-*): New (jsri): Fix operands. (setzx): Fix encoding. - + 2007-03-08 Alan Modra * m32r.opc: Formatting. @@ -243,7 +473,7 @@ (parse_signed_bitbase8): Likewise. (parse_signed_bitbase11): Likewise. (parse_signed_bitbase19): Likewise. - + 2006-03-13 DJ Delorie * m32c.cpu (Bit3-S): New. @@ -280,10 +510,10 @@ attribute. (jsri16, jsri32): Add 1ADDR attribute. (jsr32.w, jsr32.a): Add JUMP attribute. - + 2006-02-17 Shrirang Khisti - Anil Paranjape - Shilin Shakti + Anil Paranjape + Shilin Shakti * xc16x.cpu: New file containing complete CGEN specific XC16X CPU description. @@ -384,7 +614,7 @@ stzx16-imm8-imm8-abs16): Fix operand typos. * m32c.opc (m32c_asm_hash): Support bnCND. (parse_signed4n, print_signed4n): New. - + 2005-10-26 DJ Delorie * m32c.cpu (f-dsp-8-s24, Dsp-8-s24): New. @@ -458,7 +688,7 @@ Fix compile time warnings about signedness mismatches. Remove dead code. (parse_lab_5_3): New parser function. - + 2005-07-16 Jim Blandy * m32c.opc (m32c_cgen_insn_supported): Use int, not CGEN_BITSET,