X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=cpu%2Fm32c.cpu;h=5a38f1bd5264a574ae95c8569dc3d02fd185466b;hb=c0c3707ff46ccfb78ea175dd42d628d8c90dca8b;hp=a645a48b59bb23397b6490ce3edd867e1927a59e;hpb=43aa3bb1d43045f9a60a2a91be8766582a4aab42;p=deliverable%2Fbinutils-gdb.git diff --git a/cpu/m32c.cpu b/cpu/m32c.cpu index a645a48b59..5a38f1bd52 100644 --- a/cpu/m32c.cpu +++ b/cpu/m32c.cpu @@ -1,6 +1,6 @@ ; Renesas M32C CPU description. -*- Scheme -*- ; -; Copyright 2005, 2006 Free Software Foundation, Inc. +; Copyright 2005, 2006, 2007, 2009 Free Software Foundation, Inc. ; ; Contributed by Red Hat Inc; developed under contract from Renesas. ; @@ -8,7 +8,7 @@ ; ; This program is free software; you can redistribute it and/or modify ; it under the terms of the GNU General Public License as published by -; the Free Software Foundation; either version 2 of the License, or +; the Free Software Foundation; either version 3 of the License, or ; (at your option) any later version. ; ; This program is distributed in the hope that it will be useful, @@ -18,7 +18,8 @@ ; ; You should have received a copy of the GNU General Public License ; along with this program; if not, write to the Free Software -; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. +; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, +; MA 02110-1301, USA. (include "simplify.inc") @@ -571,10 +572,10 @@ ) (df f-dsp-8-s24 "24 bit signed" (all-isas) 8 24 INT ((value pc) (or SI - (or (srl value 16) (and value #xff00)) + (or (and (srl value 16) #xff) (and value #xff00)) (sll (ext INT (trunc QI (and value #xff))) 16))) ((value pc) (or SI - (or (srl value 16) (and value #xff00)) + (or (and (srl value 16) #xff) (and value #xff00)) (sll (ext INT (trunc QI (and value #xff))) 16))) ) @@ -616,12 +617,25 @@ (or USI (and (srl value 16) #x0000ff) (and value #x00ff00)) - (and (sll value 16) #xff0000))) ; insert + (and (sll value 16) #xff0000))) ; insert + ((value pc) (or USI + (or USI + (and USI (srl value 16) #x0000ff) + (and USI value #x00ff00)) + (and USI (sll value 16) #xff0000))) ; extract +) + +(df f-dsp-40-u20 "20 bit unsigned" (all-isas) 40 20 UINT + ((value pc) (or USI + (or USI + (and (srl value 16) #x0000ff) + (and value #x00ff00)) + (and (sll value 16) #x0f0000))) ; insert ((value pc) (or USI (or USI - (and USI (srl UHI value 16) #x0000ff) - (and USI value #x00ff00)) - (and USI (sll UHI value 16) #xff0000))) ; extract + (and USI (srl value 16) #x0000ff) + (and USI value #x00ff00)) + (and USI (sll value 16) #x0f0000))) ; extract ) (df f-dsp-40-u24 "24 bit unsigned" (all-isas) 40 24 UINT @@ -629,12 +643,12 @@ (or USI (and (srl value 16) #x0000ff) (and value #x00ff00)) - (and (sll value 16) #xff0000))) ; insert + (and (sll value 16) #xff0000))) ; insert ((value pc) (or USI (or USI - (and USI (srl UHI value 16) #x0000ff) - (and USI value #x00ff00)) - (and USI (sll UHI value 16) #xff0000))) ; extract + (and USI (srl value 16) #x0000ff) + (and USI value #x00ff00)) + (and USI (sll value 16) #xff0000))) ; extract ) (dnmf f-dsp-40-s32 "32 bit signed" (all-isas) INT @@ -649,6 +663,17 @@ ) ) +(dnmf f-dsp-48-u20 "20 bit unsigned" (all-isas) UINT + (f-dsp-48-u16 f-dsp-64-u8) + (sequence () ; insert + (set (ifield f-dsp-64-u8) (and (srl (ifield f-dsp-48-u20) 16) #x0f)) + (set (ifield f-dsp-48-u16) (and (ifield f-dsp-48-u20) #xffff)) + ) + (sequence () ; extract + (set (ifield f-dsp-48-u20) (or (and (ifield f-dsp-48-u16) #xffff) + (and (sll (ifield f-dsp-64-u8) 16) #x0f0000))) + ) +) (dnmf f-dsp-48-u24 "24 bit unsigned" (all-isas) UINT (f-dsp-48-u16 f-dsp-64-u8) (sequence () ; insert @@ -931,9 +956,12 @@ ) (df f-lab-8-16 "16 bit pc relative signed offset" (PCREL-ADDR SIGN-OPT all-isas) 8 16 UINT ((value pc) (or SI (sll (and (sub value (add pc 1)) #xff) 8) - (srl (and (sub value (add pc 1)) #xffff) 8))) - ((value pc) (add SI (or (srl (and value #xffff) 8) - (sra (sll (and value #xff) 24) 16)) (add pc 1))) + (srl (and (sub value (add pc 1)) #xff00) 8))) + ((value pc) (add SI (sub (xor (or (srl (and value #xff00) 8) + (sll (and value #xff) 8)) + #x8000) + #x8000) + (add pc 1))) ) (df f-lab-8-24 "24 bit absolute" (all-isas ABS-ADDR) 8 24 UINT ((value pc) (or SI @@ -1877,6 +1905,10 @@ h-sint DFLT f-dsp-40-s16 ((parse "signed16")) () () ) +(define-full-operand Dsp-40-u20 "unsigned 20 bit displacement at offset 40 bits" (all-isas) + h-uint DFLT f-dsp-40-u20 + ((parse "unsigned20")) () () +) (define-full-operand Dsp-40-u24 "unsigned 24 bit displacement at offset 40 bits" (all-isas) h-uint DFLT f-dsp-40-u24 ((parse "unsigned24")) () () @@ -1897,6 +1929,10 @@ h-sint DFLT f-dsp-48-s16 ((parse "signed16")) () () ) +(define-full-operand Dsp-48-u20 "unsigned 24 bit displacement at offset 40 bits" (all-isas) + h-uint DFLT f-dsp-48-u20 + ((parse "unsigned24")) () () +) (define-full-operand Dsp-48-u24 "unsigned 24 bit displacement at offset 48 bits" (all-isas) h-uint DFLT f-dsp-48-u24 ((parse "unsigned24")) () () @@ -1908,7 +1944,7 @@ ) (define-full-operand Imm-8-s4n "negated 4 bit immediate at offset 8 bits" (all-isas) h-sint DFLT f-imm-8-s4 - ((parse "signed4n")) () () + ((parse "signed4n") (print "signed4n")) () () ) (define-full-operand Imm-sh-8-s4 "signed 4 bit shift immediate at offset 8 bits" (all-isas) h-shimm DFLT f-imm-8-s4 @@ -2115,9 +2151,9 @@ (dnop Lab-8-16 "16 bit label" (all-isas RELAX) h-iaddr f-lab-8-16) (dnop Lab-8-24 "24 bit label" (all-isas RELAX) h-iaddr f-lab-8-24) (dnop Lab-16-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-16-8) -(dnop Lab-24-8 "8 bit label" (all-isas) h-iaddr f-lab-24-8) -(dnop Lab-32-8 "8 bit label" (all-isas) h-iaddr f-lab-32-8) -(dnop Lab-40-8 "8 bit label" (all-isas) h-iaddr f-lab-40-8) +(dnop Lab-24-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-24-8) +(dnop Lab-32-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-32-8) +(dnop Lab-40-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-40-8) ;------------------------------------------------------------- ; Condition code bits @@ -2209,6 +2245,9 @@ (define-pmacro (mem16 mode address) (mem mode (and #xffff address))) +(define-pmacro (mem20 mode address) + (mem mode (and #xfffff address))) + (define-pmacro (mem32 mode address) (mem mode (and #xffffff address))) @@ -2441,6 +2480,19 @@ (getter (mem16 xmode (add Dsp-16-u16 Src16An))) (setter (set (mem16 xmode (add Dsp-16-u16 Src16An)) newval)) ) + (define-derived-operand + (name (.sym src16-16-20-An-relative- xmode)) + (comment (.str "m16c dsp:20[An] relative destination " xmode)) + (attrs (machine 16)) + (mode xmode) + (args (Src16An Dsp-16-u20)) + (syntax "${Dsp-16-u20}[$Src16An]") + (base-ifield f-8-4) + (encoding (+ (f-8-2 3) (f-10-1 0) Dsp-16-u20 Src16An)) + (ifield-assertion (andif (eq f-8-2 3) (eq f-10-1 0))) + (getter (mem20 xmode (add Dsp-16-u20 Src16An))) + (setter (set (mem20 xmode (add Dsp-16-u20 Src16An)) newval)) + ) ) ) @@ -3157,6 +3209,19 @@ (getter (mem16 xmode (add (.sym Dsp- offset -u16) Dst16An))) (setter (set (mem16 xmode (add (.sym Dsp- offset -u16) Dst16An)) newval)) ) + (define-derived-operand + (name (.sym dst16- offset -20-An-relative- xmode)) + (comment (.str "m16c dsp:20[An] relative destination " xmode)) + (attrs (machine 16)) + (mode xmode) + (args (Dst16An (.sym Dsp- offset -u20))) + (syntax (.str "${Dsp-" offset "-u20}[$Dst16An]")) + (base-ifield f-12-4) + (encoding (+ (f-12-2 3) (f-14-1 0) (.sym Dsp- offset -u20) Dst16An)) + (ifield-assertion (andif (eq f-12-2 3) (eq f-14-1 0))) + (getter (mem16 xmode (add (.sym Dsp- offset -u20) Dst16An))) + (setter (set (mem16 xmode (add (.sym Dsp- offset -u20) Dst16An)) newval)) + ) ) ) @@ -4727,6 +4792,25 @@ (.sym dst16-16-16-absolute- xmode) ) ) + (define-anyof-operand + (name (.sym dst16-16-16sa- xmode)) + (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 16")) + (attrs (machine 16)) + (mode xmode) + (choices + (.sym dst16-16-16-SB-relative- xmode) + (.sym dst16-16-16-absolute- xmode) + ) + ) + (define-anyof-operand + (name (.sym dst16-16-20ar- xmode)) + (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 16")) + (attrs (machine 16)) + (mode xmode) + (choices + (.sym dst16-16-20-An-relative- xmode) + ) + ) ) ) @@ -5095,6 +5179,17 @@ (.sym dst32-16-16-absolute-Unprefixed- xmode) ) ) + (define-anyof-operand + (name (.sym dst32-16-16sa-Unprefixed- xmode)) + (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 16")) + (attrs (machine 32)) + (mode xmode) + (choices + (.sym dst32-16-16-SB-relative-Unprefixed- xmode) + (.sym dst32-16-16-FB-relative-Unprefixed- xmode) + (.sym dst32-16-16-absolute-Unprefixed- xmode) + ) + ) (define-anyof-operand (name (.sym dst32-16-24-Unprefixed- xmode)) (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 16")) @@ -6591,7 +6686,7 @@ (define-pmacro (arith-jnz-imm4-dst-defn mach src dstgroup label mode wstr op encoding sem) (dni (.sym op mach wstr - imm4 - dstgroup) (.str op wstr " " mach "-imm4-" dstgroup "-" label "-" mode) - ((machine mach)) + (RL_JUMP RELAXABLE (machine mach)) (.str op wstr " #${" src "},${dst" mach "-" dstgroup "-" mode "},${" label "}") encoding (sem mode src (.sym dst mach - dstgroup - mode) label) @@ -6605,10 +6700,10 @@ (+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-basic- mode) Lab-16-8) sem) (arith-jnz-imm4-dst-defn 16 (.sym Imm-8- i4n) 16-16 Lab-32-8 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-16-16- mode) Lab-16-8) + (+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-16-16- mode) Lab-32-8) sem) (arith-jnz-imm4-dst-defn 16 (.sym Imm-8- i4n) 16-8 Lab-24-8 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-16-8- mode) Lab-16-8) + (+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-16-8- mode) Lab-24-8) sem) ) ) @@ -8246,28 +8341,27 @@ ) ) ; jsri.w dst (m16 #1 m32 #1)) +(jsri-defn w dst16-16-20ar-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem + dst32-16-24-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 4) +(jsri-defn w dst16-16-16sa-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem + dst32-16-16sa-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 4) (jsri-defn w dst16-16-8-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem dst32-16-8-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 3) -(jsri-defn w dst16-16-16-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem - dst32-16-16-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 4) (jsri-defn w dst16-basic-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem dst32-basic-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 2) -(dni jsri32.w "jsr.w dst32-16-24-Unprefixed-HI" (RL_1ADDR (machine 32)) - ("jsri.w ${dst32-16-24-Unprefixed-HI}") - (+ (f-0-4 #xC) (f-7-1 1) dst32-16-24-Unprefixed-HI (f-10-2 #x1) (f-12-4 #xF)) - (jsr32-sem 6 dst32-16-24-Unprefixed-HI) - ()) ; jsri.a (m16 #2 m32 #2) +(jsri-defn a dst16-16-20ar-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem + dst32-16-24-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 4) (jsri-defn a dst16-16-8-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem dst32-16-8-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 3) -(jsri-defn a dst16-16-16-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem - dst32-16-16-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 4) +(jsri-defn a dst16-16-16sa-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem + dst32-16-16sa-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 4) (jsri-defn a dst16-basic-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem dst32-basic-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 2) (dni jsri32.a "jsr.w dst32-16-24-Unprefixed-HI" (RL_1ADDR (machine 32)) - ("jsri.w ${dst32-16-24-Unprefixed-SI}") + ("jsri.a ${dst32-16-24-Unprefixed-SI}") (+ (f-0-4 #x9) (f-7-1 0) dst32-16-24-Unprefixed-SI (f-10-2 #x0) (f-12-4 #x1)) (jsr32-sem 6 dst32-16-24-Unprefixed-SI) ()) @@ -10233,7 +10327,7 @@ ()) (dni stzx16-imm8-imm8-abs16 "stzx #Imm8,#Imm8,abs16" ((machine 16)) ("stzx #${Imm-8-QI},#${Imm-32-QI},${Dsp-16-u16}") - (+ (f-0-4 #xD) (f-4-4 #xE) Imm-8-QI Dsp-16-u16 Imm-32-QI) + (+ (f-0-4 #xD) (f-4-4 #xF) Imm-8-QI Dsp-16-u16 Imm-32-QI) (stzx-sem QI Imm-8-QI Imm-32-QI (mem16 QI Dsp-16-u16)) ()) ; stzx.BW #imm,dst (m32)