X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=drivers%2Fnet%2Fbnx2.h;h=11e9c55d1dd00a0132282ca329a7807e7cdbd2ef;hb=af3ee519c5d6bebbda9bf0ca3b81bc50b4dd2163;hp=5845e334941b4f8e71ca80ad5c674bf7a7ffd5e9;hpb=eef11427edcb821b63920219f89379fab84198b9;p=deliverable%2Flinux.git diff --git a/drivers/net/bnx2.h b/drivers/net/bnx2.h index 5845e334941b..11e9c55d1dd0 100644 --- a/drivers/net/bnx2.h +++ b/drivers/net/bnx2.h @@ -22,9 +22,9 @@ */ struct tx_bd { u32 tx_bd_haddr_hi; - u32 tx_bd_haddr_lo; - u32 tx_bd_mss_nbytes; - u32 tx_bd_vlan_tag_flags; + u32 tx_bd_haddr_lo; + u32 tx_bd_mss_nbytes; + u32 tx_bd_vlan_tag_flags; #define TX_BD_FLAGS_CONN_FAULT (1<<0) #define TX_BD_FLAGS_TCP_UDP_CKSUM (1<<1) #define TX_BD_FLAGS_IP_CKSUM (1<<2) @@ -3696,6 +3696,8 @@ struct l2_fhdr { /* 5708 Serdes PHY registers */ +#define BCM5708S_BMCR_FORCE_2500 0x20 + #define BCM5708S_UP1 0xb #define BCM5708S_UP1_2G5 0x1 @@ -3890,14 +3892,10 @@ struct bnx2 { u32 tx_prod_bseq __attribute__((aligned(L1_CACHE_BYTES))); u16 tx_prod; - struct tx_bd *tx_desc_ring; - struct sw_bd *tx_buf_ring; - int tx_ring_size; - u16 tx_cons __attribute__((aligned(L1_CACHE_BYTES))); u16 hw_tx_cons; -#ifdef BCM_VLAN +#ifdef BCM_VLAN struct vlan_group *vlgrp; #endif @@ -3916,9 +3914,11 @@ struct bnx2 { struct sw_bd *rx_buf_ring; struct rx_bd *rx_desc_ring[MAX_RX_RINGS]; - /* Only used to synchronize netif_stop_queue/wake_queue when tx */ - /* ring is full */ - spinlock_t tx_lock; + /* TX constants */ + struct tx_bd *tx_desc_ring; + struct sw_bd *tx_buf_ring; + int tx_ring_size; + u32 tx_wake_thresh; /* End of fields used in the performance code paths. */ @@ -3952,7 +3952,7 @@ struct bnx2 { #define CHIP_REV_Ax 0x00000000 #define CHIP_REV_Bx 0x00001000 #define CHIP_REV_Cx 0x00002000 - + #define CHIP_METAL(bp) (((bp)->chip_id) & 0x00000ff0) #define CHIP_BONDING(bp) (((bp)->chip_id) & 0x0000000f) @@ -3971,7 +3971,7 @@ struct bnx2 { u32 phy_addr; u32 phy_id; - + u16 bus_speed_mhz; u8 wol; @@ -4027,7 +4027,7 @@ struct bnx2 { u32 advertising; - u8 req_flow_ctrl; /* flow ctrl advertisement */ + u8 req_flow_ctrl; /* flow ctrl advertisement */ /* settings or forced */ /* settings */ u8 autoneg; @@ -4040,6 +4040,7 @@ struct bnx2 { u8 serdes_an_pending; #define SERDES_AN_TIMEOUT (HZ / 3) +#define SERDES_FORCED_TIMEOUT (HZ / 10) u8 mac_addr[8]; @@ -4106,41 +4107,43 @@ struct cpu_reg { }; struct fw_info { - u32 ver_major; - u32 ver_minor; - u32 ver_fix; + const u32 ver_major; + const u32 ver_minor; + const u32 ver_fix; - u32 start_addr; + const u32 start_addr; /* Text section. */ - u32 text_addr; - u32 text_len; - u32 text_index; + const u32 text_addr; + const u32 text_len; + const u32 text_index; u32 *text; + u8 *gz_text; + const u32 gz_text_len; /* Data section. */ - u32 data_addr; - u32 data_len; - u32 data_index; - u32 *data; + const u32 data_addr; + const u32 data_len; + const u32 data_index; + const u32 *data; /* SBSS section. */ - u32 sbss_addr; - u32 sbss_len; - u32 sbss_index; - u32 *sbss; + const u32 sbss_addr; + const u32 sbss_len; + const u32 sbss_index; + const u32 *sbss; /* BSS section. */ - u32 bss_addr; - u32 bss_len; - u32 bss_index; - u32 *bss; + const u32 bss_addr; + const u32 bss_len; + const u32 bss_index; + const u32 *bss; /* Read-only section. */ - u32 rodata_addr; - u32 rodata_len; - u32 rodata_index; - u32 *rodata; + const u32 rodata_addr; + const u32 rodata_len; + const u32 rodata_index; + const u32 *rodata; }; #define RV2P_PROC1 0 @@ -4174,13 +4177,14 @@ struct fw_info { #define BNX2_DRV_MSG_CODE_PULSE 0x06000000 #define BNX2_DRV_MSG_CODE_DIAG 0x07000000 #define BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL 0x09000000 +#define BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN 0x0b000000 #define BNX2_DRV_MSG_DATA 0x00ff0000 #define BNX2_DRV_MSG_DATA_WAIT0 0x00010000 #define BNX2_DRV_MSG_DATA_WAIT1 0x00020000 #define BNX2_DRV_MSG_DATA_WAIT2 0x00030000 #define BNX2_DRV_MSG_DATA_WAIT3 0x00040000 - + #define BNX2_DRV_MSG_SEQ 0x0000ffff #define BNX2_FW_MB 0x00000008 @@ -4190,38 +4194,38 @@ struct fw_info { #define BNX2_FW_MSG_STATUS_FAILURE 0x00ff0000 #define BNX2_LINK_STATUS 0x0000000c -#define BNX2_LINK_STATUS_INIT_VALUE 0xffffffff -#define BNX2_LINK_STATUS_LINK_UP 0x1 -#define BNX2_LINK_STATUS_LINK_DOWN 0x0 +#define BNX2_LINK_STATUS_INIT_VALUE 0xffffffff +#define BNX2_LINK_STATUS_LINK_UP 0x1 +#define BNX2_LINK_STATUS_LINK_DOWN 0x0 #define BNX2_LINK_STATUS_SPEED_MASK 0x1e -#define BNX2_LINK_STATUS_AN_INCOMPLETE (0<<1) -#define BNX2_LINK_STATUS_10HALF (1<<1) -#define BNX2_LINK_STATUS_10FULL (2<<1) -#define BNX2_LINK_STATUS_100HALF (3<<1) -#define BNX2_LINK_STATUS_100BASE_T4 (4<<1) -#define BNX2_LINK_STATUS_100FULL (5<<1) -#define BNX2_LINK_STATUS_1000HALF (6<<1) -#define BNX2_LINK_STATUS_1000FULL (7<<1) -#define BNX2_LINK_STATUS_2500HALF (8<<1) -#define BNX2_LINK_STATUS_2500FULL (9<<1) -#define BNX2_LINK_STATUS_AN_ENABLED (1<<5) -#define BNX2_LINK_STATUS_AN_COMPLETE (1<<6) -#define BNX2_LINK_STATUS_PARALLEL_DET (1<<7) -#define BNX2_LINK_STATUS_RESERVED (1<<8) -#define BNX2_LINK_STATUS_PARTNER_AD_1000FULL (1<<9) -#define BNX2_LINK_STATUS_PARTNER_AD_1000HALF (1<<10) -#define BNX2_LINK_STATUS_PARTNER_AD_100BT4 (1<<11) -#define BNX2_LINK_STATUS_PARTNER_AD_100FULL (1<<12) -#define BNX2_LINK_STATUS_PARTNER_AD_100HALF (1<<13) -#define BNX2_LINK_STATUS_PARTNER_AD_10FULL (1<<14) -#define BNX2_LINK_STATUS_PARTNER_AD_10HALF (1<<15) -#define BNX2_LINK_STATUS_TX_FC_ENABLED (1<<16) -#define BNX2_LINK_STATUS_RX_FC_ENABLED (1<<17) -#define BNX2_LINK_STATUS_PARTNER_SYM_PAUSE_CAP (1<<18) -#define BNX2_LINK_STATUS_PARTNER_ASYM_PAUSE_CAP (1<<19) -#define BNX2_LINK_STATUS_SERDES_LINK (1<<20) -#define BNX2_LINK_STATUS_PARTNER_AD_2500FULL (1<<21) -#define BNX2_LINK_STATUS_PARTNER_AD_2500HALF (1<<22) +#define BNX2_LINK_STATUS_AN_INCOMPLETE (0<<1) +#define BNX2_LINK_STATUS_10HALF (1<<1) +#define BNX2_LINK_STATUS_10FULL (2<<1) +#define BNX2_LINK_STATUS_100HALF (3<<1) +#define BNX2_LINK_STATUS_100BASE_T4 (4<<1) +#define BNX2_LINK_STATUS_100FULL (5<<1) +#define BNX2_LINK_STATUS_1000HALF (6<<1) +#define BNX2_LINK_STATUS_1000FULL (7<<1) +#define BNX2_LINK_STATUS_2500HALF (8<<1) +#define BNX2_LINK_STATUS_2500FULL (9<<1) +#define BNX2_LINK_STATUS_AN_ENABLED (1<<5) +#define BNX2_LINK_STATUS_AN_COMPLETE (1<<6) +#define BNX2_LINK_STATUS_PARALLEL_DET (1<<7) +#define BNX2_LINK_STATUS_RESERVED (1<<8) +#define BNX2_LINK_STATUS_PARTNER_AD_1000FULL (1<<9) +#define BNX2_LINK_STATUS_PARTNER_AD_1000HALF (1<<10) +#define BNX2_LINK_STATUS_PARTNER_AD_100BT4 (1<<11) +#define BNX2_LINK_STATUS_PARTNER_AD_100FULL (1<<12) +#define BNX2_LINK_STATUS_PARTNER_AD_100HALF (1<<13) +#define BNX2_LINK_STATUS_PARTNER_AD_10FULL (1<<14) +#define BNX2_LINK_STATUS_PARTNER_AD_10HALF (1<<15) +#define BNX2_LINK_STATUS_TX_FC_ENABLED (1<<16) +#define BNX2_LINK_STATUS_RX_FC_ENABLED (1<<17) +#define BNX2_LINK_STATUS_PARTNER_SYM_PAUSE_CAP (1<<18) +#define BNX2_LINK_STATUS_PARTNER_ASYM_PAUSE_CAP (1<<19) +#define BNX2_LINK_STATUS_SERDES_LINK (1<<20) +#define BNX2_LINK_STATUS_PARTNER_AD_2500FULL (1<<21) +#define BNX2_LINK_STATUS_PARTNER_AD_2500HALF (1<<22) #define BNX2_DRV_PULSE_MB 0x00000010 #define BNX2_DRV_PULSE_SEQ_MASK 0x00007fff @@ -4401,7 +4405,7 @@ struct fw_info { 0x00020000) #define BNX2_BC_STATE_RESET_TYPE_VAUX (BNX2_BC_STATE_RESET_TYPE_SIG | \ 0x00030000) -#define BNX2_BC_STATE_RESET_TYPE_DRV_MASK DRV_MSG_CODE +#define BNX2_BC_STATE_RESET_TYPE_DRV_MASK DRV_MSG_CODE #define BNX2_BC_STATE_RESET_TYPE_DRV_RESET (BNX2_BC_STATE_RESET_TYPE_SIG | \ DRV_MSG_CODE_RESET) #define BNX2_BC_STATE_RESET_TYPE_DRV_UNLOAD (BNX2_BC_STATE_RESET_TYPE_SIG | \ @@ -4444,7 +4448,7 @@ struct fw_info { #define BNX2_BC_STATE_ERR_DRV_DEAD (BNX2_BC_STATE_SIGN | 0x0500) #define BNX2_BC_STATE_ERR_NO_RXP (BNX2_BC_STATE_SIGN | 0x0600) #define BNX2_BC_STATE_ERR_TOO_MANY_RBUF (BNX2_BC_STATE_SIGN | 0x0700) - + #define BNX2_BC_STATE_DEBUG_CMD 0x1dc #define BNX2_BC_STATE_BC_DBG_CMD_SIGNATURE 0x42440000 #define BNX2_BC_STATE_BC_DBG_CMD_SIGNATURE_MASK 0xffff0000