X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=gas%2FChangeLog;h=c590a1876488e76724bb6a7a29cb030823386ad2;hb=03bf704fdb44661db7e0f61e875dd54fd678c5d0;hp=b8366948756883aa7b93e6258fd86bdb51bf7757;hpb=395fa56f0f2dadce73ce6bdefec80a3581d13590;p=deliverable%2Fbinutils-gdb.git diff --git a/gas/ChangeLog b/gas/ChangeLog index b836694875..c590a18764 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,910 @@ +2006-06-08 Alan Modra + + * configure.in (BFDLIB, BFDVER_H, ALL_OBJ_DEPS): Delete. + * Makefile.am (GASLIBS): Expand @BFDLIB@. + (BFDVER_H): Delete. + (OBJS): Expand @ALL_OBJ_DEPS@. Depend on all fopen-*.h variants. + (obj-aout.o): Depend on $(DEP_@target_get_type@_aout) + (obj-coff.o, obj-ecoff.o, obj-elf.o): Similarly. + Run "make dep-am". + * dep-in.sed: Don't substitute bfdver.h. Do remove symcat.h. + * Makefile.in: Regenerate. + * doc/Makefile.in: Regenerate. + * configure: Regenerate. + +2006-06-07 Joseph S. Myers + + * po/Make-in (pdf, ps): New dummy targets. + +2006-06-07 Julian Brown + + * config/tc-arm.c (stdarg.h): include. + (arm_it): Add uncond_value field. Add isvec and issingle to operand + array. + (arm_reg_type): Add REG_TYPE_VFSD (single or double VFP reg) and + REG_TYPE_NSDQ (single, double or quad vector reg). + (reg_expected_msgs): Update. + (BAD_FPU): Add macro for unsupported FPU instruction error. + (parse_neon_type): Support 'd' as an alias for .f64. + (parse_typed_reg_or_scalar): Support REG_TYPE_VFSD, REG_TYPE_NSDQ + sets of registers. + (parse_vfp_reg_list): Don't update first arg on error. + (parse_neon_mov): Support extra syntax for VFP moves. + (operand_parse_code): Add OP_RVSD, OP_RNSDQ, OP_VRSDLST, OP_RVSD_IO, + OP_RNSDQ_RNSC, OP_RVC_PSR, OP_APSR_RR, OP_oRNSDQ. + (parse_operands): Support isvec, issingle operands fields, new parse + codes above. + (do_vfp_nsyn_mrs, do_vfp_nsyn_msr): New functions. Support VFP mrs, + msr variants. + (do_mrs, do_msr, do_t_mrs, do_t_msr): Add support for above. + (NEON_ENC_TAB): Add vnmul, vnmla, vnmls, vcmp, vcmpz, vcmpe, vcmpez. + (NEON_ENC_SINGLE, NEON_ENC_DOUBLE): Define macros. + (NEON_SHAPE_DEF): New macro. Define table of possible instruction + shapes. + (neon_shape): Redefine in terms of above. + (neon_shape_class): New enumeration, table of shape classes. + (neon_shape_el): New enumeration. One element of a shape. + (neon_shape_el_size): Register widths of above, where appropriate. + (neon_shape_info): New struct. Info for shape table. + (neon_shape_tab): New array. + (neon_type_mask): Add N_F64, N_VFP. Update N_MAX_NONSPECIAL. + (neon_check_shape): Rewrite as... + (neon_select_shape): New function to classify instruction shapes, + driven by new table neon_shape_tab array. + (neon_quad): New function. Return 1 if shape should set Q flag in + instructions (or equivalent), 0 otherwise. + (type_chk_of_el_type): Support F64. + (el_type_of_type_chk): Likewise. + (neon_check_type): Add support for VFP type checking (VFP data + elements fill their containing registers). + (do_vfp_cond_or_thumb): Fill in condition field in ARM mode, or 0xE + in thumb mode for VFP instructions. + (do_vfp_nsyn_opcode): New function. Look up the opcode in argument, + and encode the current instruction as if it were that opcode. + (try_vfp_nsyn): New. If this looks like a VFP instruction with ARGS + arguments, call function in PFN. + (do_vfp_nsyn_add_sub, do_vfp_nsyn_mla_mls, do_vfp_nsyn_mul) + (do_vfp_nsyn_abs_neg, do_vfp_nsyn_ldm_stm, do_vfp_nsyn_ldr_str) + (do_vfp_nsyn_sqrt, do_vfp_nsyn_div, do_vfp_nsyn_nmul) + (do_vfp_nsyn_cmp, nsyn_insert_sp, do_vfp_nsyn_push) + (do_vfp_nsyn_pop, do_vfp_nsyn_cvt, do_vfp_nsyn_cvtz): New functions. + Redirect Neon-syntax VFP instructions to VFP instruction handlers. + (do_neon_dyadic_i_su, do_neon_dyadic_i64_su, do_neon_shl_imm) + (do_neon_qshl_imm, do_neon_logic, do_neon_bitfield) + (neon_dyadic_misc, neon_compare, do_neon_tst, do_neon_qdmulh) + (do_neon_fcmp_absolute, do_neon_step, do_neon_sli, do_neon_sri) + (do_neon_qshlu_imm, neon_move_immediate, do_neon_mvn, do_neon_ext) + (do_neon_rev, do_neon_dup, do_neon_rshift_round_imm, do_neon_trn) + (do_neon_zip_uzp, do_neon_sat_abs_neg, do_neon_pair_long) + (do_neon_recip_est, do_neon_cls, do_neon_clz, do_neon_cnt) + (do_neon_swp): Use neon_select_shape not neon_check_shape. Use + neon_quad. + (vfp_or_neon_is_neon): New function. Call if a mnemonic shared + between VFP and Neon turns out to belong to Neon. Perform + architecture check and fill in condition field if appropriate. + (do_neon_addsub_if_i, do_neon_mac_maybe_scalar, do_neon_abs_neg) + (do_neon_cvt): Add support for VFP variants of instructions. + (neon_cvt_flavour): Extend to cover VFP conversions. + (do_neon_mov): Rewrite to use neon_select_shape. Add support for VFP + vmov variants. + (do_neon_ldr_str): Handle single-precision VFP load/store. + (do_neon_ld_st_interleave, do_neon_ld_st_lane, do_neon_ld_dup): Use + NS_NULL not NS_IGNORE. + (opcode_tag): Add OT_csuffixF for operands which either take a + conditional suffix, or have 0xF in the condition field. + (md_assemble): Add support for OT_csuffixF. + (NCE): Replace macro with... + (NCE_tag, NCE, NCEF): New macros. + (nCE): Replace macro with... + (nCE_tag, nCE, nCEF): New macros. + (insns): Add support for VFP insns or VFP versions of insns msr, + mrs, vsqrt, vdiv, vnmul, vnmla, vnmls, vcmp, vcmpe, vpush, vpop, + vcvtz, vmul, vmla, vmls, vadd, vsub, vabs, vneg, vldm, vldmia, + vldbdb, vstm, vstmia, vstmdb, vldr, vstr, vcvt, vmov. Group shared + VFP/Neon insns together. + +2006-06-07 Alan Modra + Ladislav Michl + + * app.c: Don't include headers already included by as.h. + * as.c: Likewise. + * atof-generic.c: Likewise. + * cgen.c: Likewise. + * dwarf2dbg.c: Likewise. + * expr.c: Likewise. + * input-file.c: Likewise. + * input-scrub.c: Likewise. + * macro.c: Likewise. + * output-file.c: Likewise. + * read.c: Likewise. + * sb.c: Likewise. + * config/bfin-lex.l: Likewise. + * config/obj-coff.h: Likewise. + * config/obj-elf.h: Likewise. + * config/obj-som.h: Likewise. + * config/tc-arc.c: Likewise. + * config/tc-arm.c: Likewise. + * config/tc-avr.c: Likewise. + * config/tc-bfin.c: Likewise. + * config/tc-cris.c: Likewise. + * config/tc-d10v.c: Likewise. + * config/tc-d30v.c: Likewise. + * config/tc-dlx.h: Likewise. + * config/tc-fr30.c: Likewise. + * config/tc-frv.c: Likewise. + * config/tc-h8300.c: Likewise. + * config/tc-hppa.c: Likewise. + * config/tc-i370.c: Likewise. + * config/tc-i860.c: Likewise. + * config/tc-i960.c: Likewise. + * config/tc-ip2k.c: Likewise. + * config/tc-iq2000.c: Likewise. + * config/tc-m32c.c: Likewise. + * config/tc-m32r.c: Likewise. + * config/tc-maxq.c: Likewise. + * config/tc-mcore.c: Likewise. + * config/tc-mips.c: Likewise. + * config/tc-mmix.c: Likewise. + * config/tc-mn10200.c: Likewise. + * config/tc-mn10300.c: Likewise. + * config/tc-msp430.c: Likewise. + * config/tc-mt.c: Likewise. + * config/tc-ns32k.c: Likewise. + * config/tc-openrisc.c: Likewise. + * config/tc-ppc.c: Likewise. + * config/tc-s390.c: Likewise. + * config/tc-sh.c: Likewise. + * config/tc-sh64.c: Likewise. + * config/tc-sparc.c: Likewise. + * config/tc-tic30.c: Likewise. + * config/tc-tic4x.c: Likewise. + * config/tc-tic54x.c: Likewise. + * config/tc-v850.c: Likewise. + * config/tc-vax.c: Likewise. + * config/tc-xc16x.c: Likewise. + * config/tc-xstormy16.c: Likewise. + * config/tc-xtensa.c: Likewise. + * config/tc-z80.c: Likewise. + * config/tc-z8k.c: Likewise. + * macro.h: Don't include sb.h or ansidecl.h. + * sb.h: Don't include stdio.h or ansidecl.h. + * cond.c: Include sb.h. + * itbl-lex.l: Include as.h instead of other system headers. + * itbl-parse.y: Likewise. + * itbl-ops.c: Similarly. + * itbl-ops.h: Don't include as.h or ansidecl.h. + * config/bfin-defs.h: Don't include bfd.h or as.h. + * config/bfin-parse.y: Include as.h instead of other system headers. + +2006-06-06 Ben Elliston + Anton Blanchard + + * config/tc-ppc.c (parse_cpu): Handle "-mpower6". + (md_show_usage): Document it. + (ppc_setup_opcodes): Test power6 opcode flag bits. + * doc/c-ppc.texi (PowerPC-Opts): Document "-mpower6". + +2006-06-06 Thiemo Seufer + Chao-ying Fu + + * config/tc-mips.c (ISA_SUPPORTS_DSP64): New macro. + (CPU_HAS_MIPS3D, CPU_HAS_MDMX, CPU_HAS_DSP, CPU_HAS_MT): Delete. + (macro_build): Update comment. + (mips_ip): Allow DSP64 instructions for MIPS64R2. + (mips_after_parse_args): Remove uses of CPU_HAS_MIPS3D and + CPU_HAS_MDMX. + (mips_cpu_info): Fix formatting. Add MIPS_CPU_ASE_MIPS3D and + MIPS_CPU_ASE_MDMX flags for sb1. + +2006-06-05 Thiemo Seufer + + * config/tc-mips.c (macro_build): Use INSERT_OPERAND wherew + appropriate. + (mips16_macro_build): Use MIPS16_INSERT_OPERAND where appropriate. + (mips_ip): Make overflowed/underflowed constant arguments in DSP + and MT instructions a fatal error. Use INSERT_OPERAND where + appropriate. Improve warnings for break and wait code overflows. + Use symbolic constant of OP_MASK_COPZ. + (mips16_ip): Use MIPS16_INSERT_OPERAND where appropriate. + +2006-06-05 Daniel Jacobowitz + + * po/Make-in (top_builddir): Define. + +2006-06-02 Joseph S. Myers + + * doc/Makefile.am (TEXI2DVI): Define. + * doc/Makefile.in: Regenerate. + * doc/c-arc.texi: Fix typo. + +2006-06-01 Alan Modra + + * config/obj-ieee.c: Delete. + * config/obj-ieee.h: Delete. + * Makefile.am (OBJ_FORMATS): Remove ieee. + (OBJ_FORMAT_CFILES, OBJ_FORMAT_HFILES): Similarly. + (obj-ieee.o): Remove rule. + * Makefile.in: Regenerate. + * configure.in (atof): Remove tahoe. + (OBJ_MAYBE_IEEE): Don't define. + * configure: Regenerate. + * config.in: Regenerate. + * doc/Makefile.in: Regenerate. + * po/POTFILES.in: Regenerate. + +2006-05-31 Daniel Jacobowitz + + * Makefile.am: Replace INTLLIBS and INTLDEPS with LIBINTL + and LIBINTL_DEP everywhere. + (INTLLIBS): Remove. + (INCLUDES, DEP_INCLUDES): Use @INCINTL@. + * acinclude.m4: Include new gettext macros. + * configure.in: Use ZW_GNU_GETTEXT_SISTER_DIR and AM_PO_SUBDIRS. + Remove local code for po/Makefile. + * Makefile.in, configure, doc/Makefile.in: Regenerated. + +2006-05-30 Nick Clifton + + * po/es.po: Updated Spanish translation. + +2006-05-06 Denis Chertykov + + * doc/c-avr.texi: New file. + * doc/Makefile.am (CPU_DOCS): Add c-avr.texi + * doc/all.texi: Set AVR + * doc/as.texinfo: Include c-avr.texi + +2006-05-28 Jie Zhang + + * config/bfin-parse.y (check_macfunc): Loose the condition of + calling check_multiply_halfregs (). + +2006-05-25 Jie Zhang + + * config/bfin-parse.y (asm_1): Better check and deal with + vector and scalar Multiply 16-Bit Operands instructions. + +2006-05-24 Nick Clifton + + * config/tc-hppa.c: Convert to ISO C90 format. + * config/tc-hppa.h: Likewise. + +2006-05-24 Carlos O'Donell + Randolph Chung + + * config/tc-hppa.c (is_tls_gdidx, is_tls_ldidx, is_tls_dtpoff, + is_tls_ieoff, is_tls_leoff): Define. + (fix_new_hppa): Handle TLS. + (cons_fix_new_hppa): Likewise. + (pa_ip): Likewise. + (md_apply_fix): Handle TLS relocs. + * config/tc-hppa.h (hppa_fix_adjustable): Handle TLS. + +2006-05-24 Bjoern Haase + + * config/tc-avr.c: Add new cpu targets avr6, avr2560 and avr2561. + +2006-05-23 Thiemo Seufer + David Ung + Nigel Stephens + + [ gas/ChangeLog ] + * config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename. + (ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS, + ISA_HAS_MXHC1): New macros. + (HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of + ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments. + (mips_cpu_info): Change to use combined ASE/IS_ISA flag. + (MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP, + MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines. + (mips_after_parse_args): Change default handling of float register + size to account for 32bit code with 64bit FP. Better sanity checking + of ISA/ASE/ABI option combinations. + (s_mipsset): Support switching of GPR and FPR sizes via + .set {g,f}p={32,64,default}. Better sanity checking for .set ASE + options. + (mips_elf_final_processing): We should record the use of 64bit FP + registers in 32bit code but we don't, because ELF header flags are + a scarce ressource. + (mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE + extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef, + 24kex, 34kc, 34kf, 34kx, 25kf CPU definitions. + (mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA. + * doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document + missing -march options. Document .set arch=CPU. Move .set smartmips + to ASE page. Use @code for .set FOO examples. + +2006-05-23 Jie Zhang + + * config/tc-bfin.c (bfin_start_line_hook): Bump line counters + if needed. + +2006-05-23 Jie Zhang + + * config/bfin-defs.h (bfin_equals): Remove declaration. + * config/bfin-parse.y (asm_1): Remove "expr ASSIGN expr". + * config/tc-bfin.c (bfin_name_is_register): Remove. + (bfin_equals): Remove. + * config/tc-bfin.h (TC_EQUAL_IN_INSN): Redefine as 1. + (bfin_name_is_register): Remove declaration. + +2006-05-19 Thiemo Seufer + Nigel Stephens + + * config/tc-mipc.c (ISA_HAS_ODD_SINGLE_FPR): New define. + (mips_oddfpreg_ok): New function. + (mips_ip): Use it. + +2006-05-19 Thiemo Seufer + David Ung + + * config/tc-mips.h (tc_mips_regname_to_dw2regnum): Declare. + * config/tc-mipc.c (ABI_NEEDS_64BIT_REGS, ISA_HAS_64BIT_REGS, + ISA_HAS_DROR, ISA_HAS_ROR): Reformat. + (regname, RTYPE_MASK, RTYPE_NUM, RTYPE_FPU, RTYPE_FCC, RTYPE_VEC, + RTYPE_GP, RTYPE_CP0, RTYPE_PC, RTYPE_ACC, RTYPE_CCC, RNUM_MASK, + RWARN, GENERIC_REGISTER_NUMBERS, FPU_REGISTER_NAMES, + FPU_CONDITION_CODE_NAMES, COPROC_CONDITION_CODE_NAMES, + N32N64_SYMBOLIC_REGISTER_NAMES, O32_SYMBOLIC_REGISTER_NAMES, + SYMBOLIC_REGISTER_NAMES, MIPS16_SPECIAL_REGISTER_NAMES, + MDMX_VECTOR_REGISTER_NAMES, MIPS_DSP_ACCUMULATOR_NAMES, reg_names, + reg_names_o32, reg_names_n32n64): Define register classes. + (reg_lookup): New function, use register classes. + (md_begin): Reserve register names in the symbol table. Simplify + OBJ_ELF defines. + (mips_ip): Fix comment formatting. Handle symbolic COP0 registers. + Use reg_lookup. + (mips16_ip): Use reg_lookup. + (tc_get_register): Likewise. + (tc_mips_regname_to_dw2regnum): New function. + +2006-05-19 Thiemo Seufer + + * config/tc-arm.c, config/tc-arm.h (tc_arm_regname_to_dw2regnum): + Un-constify string argument. + * config/tc-i386.c, config/tc-i386.h (tc_x86_regname_to_dw2regnum): + Likewise. + * config/tc-m68k.c, config/tc-m68k.h (tc_m68k_regname_to_dw2regnum): + Likewise. + * config/tc-ppc.c, config/tc-ppc.h (tc_ppc_regname_to_dw2regnum): + Likewise. + * config/tc-s390.c, config/tc-s390.h (tc_s390_regname_to_dw2regnum): + Likewise. + * config/tc-sh.c, config/tc-sh.h (sh_regname_to_dw2regnum): + Likewise. + * config/tc-sparc.c, config/tc-sparc.h (sparc_regname_to_dw2regnum): + Likewise. + +2006-05-19 Nathan Sidwell + + * gas/config/tc-m68k.c (m68k_init_arch): Move checking of + cfloat/m68881 to correct architecture before using it. + +2006-05-16 Bjoern Haase + + * config/tc-avr.h (TC_VALIDATE_FIX): Allow fixups for immediate + constant values. + +2006-05-15 Paul Brook + + * config/tc-arm.c (arm_adjust_symtab): Use + bfd_is_arm_special_symbol_name. + +2006-05-15 Bob Wilson + + * config/tc-xtensa.c (is_direct_call_opcode, is_branch_jmp_to_next, + xg_assemble_vliw_tokens, xtensa_mark_narrow_branches, + xtensa_fix_short_loop_frags, is_local_forward_loop, relax_frag_immed): + Handle errors from calls to xtensa_opcode_is_* functions. + +2006-05-14 Thiemo Seufer + + * config/tc-mips.c (macro_build): Test for currently active + mips16 option. + (mips16_ip): Reject invalid opcodes. + +2006-05-11 Carlos O'Donell + + * doc/as.texinfo: Rename "Index" to "AS Index", + and "ABORT" to "ABORT (COFF)". + +2006-05-11 Paul Brook + + * config/tc-arm.c (parse_half): New function. + (operand_parse_code): Remove OP_Iffff. Add OP_HALF. + (parse_operands): Ditto. + (do_mov16): Reject invalid relocations. + (do_t_mov16): Ditto. Use Thumb reloc numbers. + (insns): Replace Iffff with HALF. + (md_apply_fix): Add MOVW and MOVT relocs. + (tc_gen_reloc): Ditto. + * doc/c-arm.texi: Document relocation operators + +2006-05-11 Paul Brook + + * config/tc-arm.c (arm_fix_adjustable): Return 0 for function symbols. + +2006-05-11 Thiemo Seufer + + * config/tc-mips.c (append_insn): Don't check the range of j or + jal addresses. + +2006-05-11 Pedro Alves + + * config/tc-arm.c (md_pcrel_from_section): Force a bias for + relocs against external symbols for WinCE targets. + (md_apply_fix): Likewise. + +2006-05-09 David Ung + + * config/tc-mips.c (append_insn): Only warn about an out-of-range + j or jal address. + +2006-05-09 Nick Clifton + + * config/tc-arm.c (arm_fix_adjustable): For COFF, convert fixups + against symbols which are not going to be placed into the symbol + table. + +2006-05-09 Ben Elliston + + * expr.c (operand): Remove `if (0 && ..)' statement and + subsequently unused target_op label. Collapse `if (1 || ..)' + statement. + * app.c (do_scrub_chars): Remove unused case 0, as it is handled + separately above the switch. + +2006-05-08 Nick Clifton + + PR gas/2623 + * config/tc-msp430.c (line_separator_character): Define as |. + +2006-05-08 Thiemo Seufer + Nigel Stephens + David Ung + + * config/tc-mips.c (mips_set_options): Add ase_smartmips flag. + (mips_opts): Likewise. + (file_ase_smartmips): New variable. + (ISA_HAS_ROR): SmartMIPS implements rotate instructions. + (macro_build): Handle SmartMIPS instructions. + (mips_ip): Likewise. + (md_longopts): Add argument handling for smartmips. + (md_parse_options, mips_after_parse_args): Likewise. + (s_mipsset): Add .set smartmips support. + (md_show_usage): Document -msmartmips/-mno-smartmips. + * doc/as.texinfo: Document -msmartmips/-mno-smartmips and + .set smartmips. + * doc/c-mips.texi: Likewise. + +2006-05-08 Alan Modra + + * write.c (relax_segment): Add pass count arg. Don't error on + negative org/space on first two passes. + (relax_seg_info): New struct. + (relax_seg, write_object_file): Adjust. + * write.h (relax_segment): Update prototype. + +2006-05-05 Julian Brown + + * config/tc-arm.c (parse_vfp_reg_list): Improve register bounds + checking. + (do_neon_mov): Enable several VMOV variants for VFP. Add suitable + architecture version checks. + (insns): Allow overlapping instructions to be used in VFP mode. + +2006-05-05 H.J. Lu + + PR gas/2598 + * config/obj-elf.c (obj_elf_change_section): Allow user + specified SHF_ALPHA_GPREL. + +2006-05-05 Bjoern Haase + + * gas/config/tc-avr.h (TC_VALIDATE_FIX): Define. Disable fixups + for PMEM related expressions. + +2006-05-05 Nick Clifton + + PR gas/2582 + * dwarf2dbg.c (INSERT_DIR_SEPARATOR): New macro. Handles the + insertion of a directory separator character into a string at a + given offset. Uses heuristics to decide when to use a backslash + character rather than a forward-slash character. + (dwarf2_directive_loc): Use the macro. + (out_debug_info): Likewise. + +2006-05-05 Thiemo Seufer + David Ung + + * config/tc-mips.c (macro_build): Add case 'k' to handle cache + instruction. + (macro): Add new case M_CACHE_AB. + +2006-05-04 Kazu Hirata + + * config/tc-arm.c (opcode_tag): Add OT_cinfix3_deprecated. + (opcode_lookup): Issue a warning for opcode with + OT_cinfix3_deprecated. Otherwise treat OT_cinfix3_deprecated + identical to OT_cinfix3. + (TxC3w, TC3w, tC3w): New. + (insns): Use tC3w and TC3w for comparison instructions with + 's' suffix. + +2006-05-04 Alan Modra + + * subsegs.h (struct frchain): Delete frch_seg. + (frchain_root): Delete. + (seg_info): Define as macro. + * subsegs.c (frchain_root): Delete. + (abs_seg_info, und_seg_info, absolute_frchain): Delete. + (subsegs_begin, subseg_change): Adjust for above. + (subseg_set_rest): Likewise. Add new frchain structs to seginfo + rather than to one big list. + (subseg_get): Don't special case abs, und sections. + (subseg_new, subseg_force_new): Don't set frchainP here. + (seg_info): Delete. + (subsegs_print_statistics): Adjust frag chain control list traversal. + * debug.c (dmp_frags): Likewise. + * dwarf2dbg.c (first_frag_for_seg): Don't start looking for frag + at frchain_root. Make use of known frchain ordering. + (last_frag_for_seg): Likewise. + (get_frag_fix): Likewise. Add seg param. + (process_entries, out_debug_aranges): Adjust get_frag_fix calls. + * write.c (chain_frchains_together_1): Adjust for struct frchain. + (SUB_SEGMENT_ALIGN): Likewise. + (subsegs_finish): Adjust frchain list traversal. + * config/tc-xtensa.c (xtensa_cleanup_align_frags): Likewise. + (xtensa_fix_target_frags, xtensa_mark_narrow_branches): Likewise. + (xtensa_mark_zcl_first_insns, xtensa_fix_a0_b_retw_frags): Likewise. + (xtensa_fix_b_j_loop_end_frags): Likewise. + (xtensa_fix_close_loop_end_frags): Likewise. + (xtensa_fix_short_loop_frags, xtensa_sanity_check): Likewise. + (retrieve_segment_info): Delete frch_seg initialisation. + +2006-05-03 Alan Modra + + * subsegs.c (subseg_get): Don't call obj_sec_set_private_data. + * config/obj-elf.h (obj_sec_set_private_data): Delete. + * config/tc-hppa.c (tc_gen_reloc): Don't use bfd_abs_symbol. + * config/tc-mn10300.c (tc_gen_reloc): Likewise. + +2006-05-02 Joseph Myers + + * config/tc-arm.c (do_iwmmxt_wldstbh): Don't multiply offset by 4 + here. + (md_apply_fix3): Multiply offset by 4 here for + BFD_RELOC_ARM_CP_OFF_IMM_S2 and BFD_RELOC_ARM_T32_CP_OFF_IMM_S2. + +2006-05-02 H.J. Lu + Jan Beulich + + * config/tc-i386.c (output_invalid_buf): Change size for + unsigned char. + * config/tc-tic30.c (output_invalid_buf): Likewise. + + * config/tc-i386.c (output_invalid): Cast none-ascii char to + unsigned char. + * config/tc-tic30.c (output_invalid): Likewise. + +2006-05-02 Daniel Jacobowitz + + * doc/Makefile.am (AM_MAKEINFOFLAGS): New. + (TEXI2POD): Use AM_MAKEINFOFLAGS. + (asconfig.texi): Don't set top_srcdir. + * doc/as.texinfo: Don't use top_srcdir. + * aclocal.m4, Makefile.in, doc/Makefile.in: Regenerated. + +2006-05-02 H.J. Lu + + * config/tc-i386.c (output_invalid_buf): Change size to 16. + * config/tc-tic30.c (output_invalid_buf): Likewise. + + * config/tc-i386.c (output_invalid): Use snprintf instead of + sprintf. + * config/tc-ia64.c (declare_register_set): Likewise. + (emit_one_bundle): Likewise. + (check_dependencies): Likewise. + * config/tc-tic30.c (output_invalid): Likewise. + +2006-05-02 Paul Brook + + * config/tc-arm.c (arm_optimize_expr): New function. + * config/tc-arm.h (md_optimize_expr): Define + (arm_optimize_expr): Add prototype. + (TC_FORCE_RELOCATION_SUB_SAME): Define. + +2006-05-02 Ben Elliston + + * config/obj-elf.h (ELF_TARGET_SYMBOL_FIELDS): Make single bit + field unsigned. + + * sb.h (sb_list_vector): Move to sb.c. + * sb.c (free_list): Use type of sb_list_vector directly. + (sb_build): Fix off-by-one error in assertion about `size'. + +2006-05-01 Ben Elliston + + * listing.c (listing_listing): Remove useless loop. + * macro.c (macro_expand): Remove is_positional local variable. + * read.c (s_comm_internal): Simplify `if' condition 1 || x -> 1 + and simplify surrounding expressions, where possible. + (assign_symbol): Likewise. + (s_weakref): Likewise. + * symbols.c (colon): Likewise. + +2006-05-01 James Lemke + + * subsegs.c (subseg_set_rest): Always set seginfp->frchainP if NULL. + +2006-04-30 Thiemo Seufer + David Ung + + * config/tc-mips.c (validate_mips_insn): Handling of udi cases. + (mips_immed): New table that records various handling of udi + instruction patterns. + (mips_ip): Adds udi handling. + +2006-04-28 Alan Modra + + * dwarf2dbg.c (get_line_subseg): Attach new struct line_seg to end + of list rather than beginning. + +2006-04-26 Julian Brown + + * gas/config/tc-arm.c (neon_is_quarter_float): Move, and rename to... + (is_quarter_float): Rename from above. Simplify slightly. + (parse_qfloat_immediate): Parse a "quarter precision" floating-point + number. + (parse_neon_mov): Parse floating-point constants. + (neon_qfloat_bits): Fix encoding. + (neon_cmode_for_move_imm): Tweak to use floating-point encoding in + preference to integer encoding when using the F32 type. + +2006-04-26 Julian Brown + + * config/tc-arm.c (neon_el_type): Make NT_invtype be the zero (so + zero-initialising structures containing it will lead to invalid types). + (arm_it): Add vectype to each operand. + (NTA_HASTYPE, NTA_HASINDEX): Constants used in neon_typed_alias + defined field. + (neon_typed_alias): New structure. Extra information for typed + register aliases. + (reg_entry): Add neon type info field. + (arm_reg_parse): Remove RTYPE argument (revert to previous arguments). + Break out alternative syntax for coprocessor registers, etc. into... + (arm_reg_alt_syntax): New function. Alternate syntax handling broken + out from arm_reg_parse. + (parse_neon_type): Move. Return SUCCESS/FAIL. + (first_error): New function. Call to ensure first error which occurs is + reported. + (parse_neon_operand_type): Parse exactly one type. + (NEON_ALL_LANES, NEON_INTERLEAVE_LANES): Move. + (parse_typed_reg_or_scalar): New function. Handle core of both + arm_typed_reg_parse and parse_scalar. + (arm_typed_reg_parse): Parse a register with an optional type. + (NEON_SCALAR_REG, NEON_SCALAR_INDEX): Extract parts of parse_scalar + result. + (parse_scalar): Parse a Neon scalar with optional type. + (parse_reg_list): Use first_error. + (parse_vfp_reg_list): Use arm_typed_reg_parse instead of arm_reg_parse. + (neon_alias_types_same): New function. Return true if two (alias) types + are the same. + (parse_neon_el_struct_list): Use parse_typed_reg_or_scalar. Return type + of elements. + (insert_reg_alias): Return new reg_entry not void. + (insert_neon_reg_alias): New function. Insert type/index information as + well as register for alias. + (create_neon_reg_alias): New function. Parse .dn/.qn directives and + make typed register aliases accordingly. + (s_dn, s_qn): New functions. Handle incorrectly used .dn/.qn at start + of line. + (s_unreq): Delete type information if present. + (s_arm_unwind_save_mmxwr): Remove arg 3 from arm_reg_parse calls. + (s_arm_unwind_save_mmxwcg): Likewise. + (s_arm_unwind_movsp): Likewise. + (s_arm_unwind_setfp): Likewise. + (parse_shift): Likewise. + (parse_shifter_operand): Likewise. + (parse_address): Likewise. + (parse_tb): Likewise. + (tc_arm_regname_to_dw2regnum): Likewise. + (md_pseudo_table): Add dn, qn. + (parse_neon_mov): Handle typed operands. + (parse_operands): Likewise. + (neon_type_mask): Add N_SIZ. + (N_ALLMODS): New macro. + (neon_check_shape): Fix typo in NS_DDD_QQQ case. Use first_error. + (el_type_of_type_chk): Add some safeguards. + (modify_types_allowed): Fix logic bug. + (neon_check_type): Handle operands with types. + (neon_three_same): Remove redundant optional arg handling. + (do_neon_dyadic_i64_su, do_neon_shl_imm, do_neon_qshl_imm) + (do_neon_logic, do_neon_qdmulh, do_neon_fcmp_absolute) + (do_neon_step): Adjust accordingly. + (neon_cmode_for_logic_imm): Use first_error. + (do_neon_bitfield): Call neon_check_type. + (neon_dyadic): Rename to... + (neon_dyadic_misc): ...this. New name for neon_dyadic. Add bitfield + to allow modification of type of the destination. + (do_neon_dyadic_if_su, do_neon_dyadic_if_i, do_neon_dyadic_if_i_d) + (do_neon_addsub_if_i, do_neon_mul): Adjust accordingly. + (do_neon_compare): Make destination be an untyped bitfield. + (neon_scalar_for_mul): Use NEON_SCALAR_REG, NEON_SCALAR_INDEX. + (neon_mul_mac): Return early in case of errors. + (neon_move_immediate): Use first_error. + (neon_mac_reg_scalar_long): Fix type to include scalar. + (do_neon_dup): Likewise. + (do_neon_mov): Likewise (in several places). + (do_neon_tbl_tbx): Fix type. + (do_neon_ld_st_interleave, neon_alignment_bit, do_neon_ld_st_lane) + (do_neon_ld_dup): Exit early in case of errors and/or use + first_error. + (opcode_lookup): Update for parse_neon_type returning SUCCESS/FAIL. + Handle .dn/.qn directives. + (REGDEF): Add zero for reg_entry neon field. + +2006-04-26 Julian Brown + + * config/tc-arm.c (limits.h): Include. + (fpu_arch_vfp_v3, fpu_vfp_ext_v3, fpu_neon_ext_v1) + (fpu_vfp_v3_or_neon_ext): Declare constants. + (neon_el_type): New enumeration of types for Neon vector elements. + (neon_type_el): New struct. Define type and size of a vector element. + (NEON_MAX_TYPE_ELS): Define constant. The maximum number of types per + instruction. + (neon_type): Define struct. The type of an instruction. + (arm_it): Add 'vectype' for the current instruction. + (isscalar, immisalign, regisimm, isquad): New predicates for operands. + (vfp_sp_reg_pos): Rename to... + (vfp_reg_pos): ...this, and add VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn + tags. + (arm_reg_type): Add REG_TYPE_NQ (Neon Q register) and REG_TYPE_NDQ + (Neon D or Q register). + (reg_expected_msgs): Sync with above. Allow VFD to mean VFP or Neon D + register. + (GE_OPT_PREFIX_BIG): Define constant, for use in... + (my_get_expression): Allow above constant as argument to accept + 64-bit constants with optional prefix. + (arm_reg_parse): Add extra argument to return the specific type of + register in when either a D or Q register (REG_TYPE_NDQ) is + requested. Can be NULL. + (parse_scalar): New function. Parse Neon scalar (vector reg and index). + (parse_reg_list): Update for new arm_reg_parse args. + (parse_vfp_reg_list): Allow parsing of Neon D/Q register lists. + (parse_neon_el_struct_list): New function. Parse element/structure + register lists for VLD/VST instructions. + (s_arm_unwind_save_vfp): Update for new parse_vfp_reg_list args. + (s_arm_unwind_save_mmxwr): Likewise. + (s_arm_unwind_save_mmxwcg): Likewise. + (s_arm_unwind_movsp): Likewise. + (s_arm_unwind_setfp): Likewise. + (parse_big_immediate): New function. Parse an immediate, which may be + 64 bits wide. Put results in inst.operands[i]. + (parse_shift): Update for new arm_reg_parse args. + (parse_address): Likewise. Add parsing of alignment specifiers. + (parse_neon_mov): Parse the operands of a VMOV instruction. + (operand_parse_code): Add OP_RND, OP_RNQ, OP_RNDQ, OP_RNSC, OP_NRDLST, + OP_NSTRLST, OP_NILO, OP_RNDQ_I0, OP_RR_RNSC, OP_RNDQ_RNSC, OP_RND_RNSC, + OP_VMOV, OP_RNDQ_IMVNb, OP_RNDQ_I63b, OP_I0, OP_I16z, OP_I32z, OP_I64, + OP_I64z, OP_oI32b, OP_oRND, OP_oRNQ, OP_oRNDQ. + (parse_operands): Handle new codes above. + (encode_arm_vfp_sp_reg): Rename to... + (encode_arm_vfp_reg): ...this. Handle D regs (0-31) too. Complain if + selected VFP version only supports D0-D15. + (do_vfp_sp_monadic, do_vfp_sp_dyadic, do_vfp_sp_compare_z) + (do_vfp_dp_sp_cvt, do_vfp_reg_from_sp, do_vfp_reg2_from_sp2) + (do_vfp_sp_from_reg, do_vfp_sp2_from_reg2, do_vfp_sp_ldst) + (do_vfp_dp_ldst, vfp_sp_ldstm, vfp_dp_ldstm): Update for new + encode_arm_vfp_reg name, and allow 32 D regs. + (do_vfp_dp_rd_rm, do_vfp_dp_rn_rd, do_vfp_dp_rd_rn, do_vfp_dp_rd_rn_rm) + (do_vfp_rm_rd_rn): New functions to encode VFP insns allowing 32 D + regs. + (do_vfp_sp_const, do_vfp_dp_const, vfp_conv, do_vfp_sp_conv_16) + (do_vfp_dp_conv_16, do_vfp_sp_conv_32, do_vfp_dp_conv_32): Handle + constant-load and conversion insns introduced with VFPv3. + (neon_tab_entry): New struct. + (NEON_ENC_TAB): Bit patterns for overloaded Neon instructions, and + those which are the targets of pseudo-instructions. + (neon_opc): Enumerate opcodes, use as indices into... + (neon_enc_tab): ...this. Hold data from NEON_ENC_TAB. + (NEON_ENC_INTEGER, NEON_ENC_ARMREG, NEON_ENC_POLY, NEON_ENC_FLOAT) + (NEON_ENC_SCALAR, NEON_ENC_IMMED, NEON_ENC_INTERLV, NEON_ENC_LANE) + (NEON_ENC_DUP): Define meaningful helper macros to look up values in + neon_enc_tab. + (neon_shape): Enumerate shapes (permitted register widths, etc.) for + Neon instructions. + (neon_type_mask): New. Compact type representation for type checking. + (N_SU_ALL, N_SU_32, N_SU_16_64, N_SUF_32, N_I_ALL, N_IF_32): Common + permitted type combinations. + (N_IGNORE_TYPE): New macro. + (neon_check_shape): New function. Check an instruction shape for + multiple alternatives. Return the specific shape for the current + instruction. + (neon_modify_type_size): New function. Modify a vector type and size, + depending on the bit mask in argument 1. + (neon_type_promote): New function. Convert a given "key" type (of an + operand) into the correct type for a different operand, based on a bit + mask. + (type_chk_of_el_type): New function. Convert a type and size into the + compact representation used for type checking. + (el_type_of_type_ckh): New function. Reverse of above (only when a + single bit is set in the bit mask). + (modify_types_allowed): New function. Alter a mask of allowed types + based on a bit mask of modifications. + (neon_check_type): New function. Check the type of the current + instruction against the variable argument list. The "key" type of the + instruction is returned. + (neon_dp_fixup): New function. Fill in and modify instruction bits for + a Neon data-processing instruction depending on whether we're in ARM + mode or Thumb-2 mode. + (neon_logbits): New function. + (neon_three_same, neon_two_same, do_neon_dyadic_i_su) + (do_neon_dyadic_i64_su, neon_imm_shift, do_neon_shl_imm) + (do_neon_qshl_imm, neon_cmode_for_logic_imm, neon_bits_same_in_bytes) + (neon_squash_bits, neon_is_quarter_float, neon_qfloat_bits) + (neon_cmode_for_move_imm, neon_write_immbits, neon_invert_size) + (do_neon_logic, do_neon_bitfield, neon_dyadic, do_neon_dyadic_if_su) + (do_neon_dyadic_if_su_d, do_neon_dyadic_if_i, do_neon_dyadic_if_i_d) + (do_neon_addsub_if_i, neon_exchange_operands, neon_compare) + (do_neon_cmp, do_neon_cmp_inv, do_neon_ceq, neon_scalar_for_mul) + (neon_mul_mac, do_neon_mac_maybe_scalar, do_neon_tst, do_neon_mul) + (do_neon_qdmulh, do_neon_fcmp_absolute, do_neon_fcmp_absolute_inv) + (do_neon_step, do_neon_abs_neg, do_neon_sli, do_neon_sri) + (do_neon_qshlu_imm, do_neon_qmovn, do_neon_qmovun) + (do_neon_rshift_sat_narrow, do_neon_rshift_sat_narrow_u, do_neon_movn) + (do_neon_rshift_narrow, do_neon_shll, neon_cvt_flavour, do_neon_cvt) + (neon_move_immediate, do_neon_mvn, neon_mixed_length) + (do_neon_dyadic_long, do_neon_abal, neon_mac_reg_scalar_long) + (do_neon_mac_maybe_scalar_long, do_neon_dyadic_wide, do_neon_vmull) + (do_neon_ext, do_neon_rev, do_neon_dup, do_neon_mov) + (do_neon_rshift_round_imm, do_neon_movl, do_neon_trn, do_neon_zip_uzp) + (do_neon_sat_abs_neg, do_neon_pair_long, do_neon_recip_est) + (do_neon_cls, do_neon_clz, do_neon_cnt, do_neon_swp, do_neon_tbl_tbx) + (do_neon_ldm_stm, do_neon_ldr_str, do_neon_ld_st_interleave) + (neon_alignment_bit, do_neon_ld_st_lane, do_neon_ld_dup) + (do_neon_ldx_stx): New functions. Neon bit encoding and encoding + helpers. + (parse_neon_type): New function. Parse Neon type specifier. + (opcode_lookup): Allow parsing of Neon type specifiers. + (REGNUM2, REGSETH, REGSET2): New macros. + (reg_names): Add new VFPv3 and Neon registers. + (NUF, nUF, NCE, nCE): New macros for opcode table. + (insns): More VFP registers allowed in fcpyd, fmdhr, fmdlr, fmrdh, + fmrdl, fabsd, fnegd, fsqrtd, faddd, fsubd, fmuld, fdivd, fmacd, fmscd, + fnmuld, fnmacd, fnmscd, fcmpd, fcmpzd, fcmped, fcmpezd, fmdrr, fmrrd. + Add Neon instructions vaba, vhadd, vrhadd, vhsub, vqadd, vqsub, vrshl, + vqrshl, vshl, vqshl{u}, vand, vbic, vorr, vorn, veor, vbsl, vbit, vbif, + vabd, vmax, vmin, vcge, vcgt, vclt, vcle, vceq, vpmax, vpmin, vmla, + vmls, vpadd, vadd, vsub, vtst, vmul, vqdmulh, vqrdmulh, vacge, vacgt, + vaclt, vacle, vrecps, vrsqrts, vabs, vneg, v{r}shr, v{r}sra, vsli, + vsri, vqshrn, vq{r}shr{u}n, v{r}shrn, vshll, vcvt, vmov, vmvn, vabal, + vabdl, vaddl, vsubl, vmlal, vmlsl, vaddw, vsubw, v{r}addhn, v{r}subhn, + vqdmlal, vqdmlsl, vqdmull, vmull, vext, vrev64, vrev32, vrev16, vdup, + vmovl, v{q}movn, vzip, vuzp, vqabs, vqneg, vpadal, vpaddl, vrecpe, + vrsqrte, vcls, vclz, vcnt, vswp, vtrn, vtbl, vtbx, vldm, vstm, vldr, + vstr, vld[1234], vst[1234], fconst[sd], f[us][lh]to[sd], + fto[us][lh][sd]. + (tc_arm_regname_to_dw2regnum): Update for arm_reg_parse args. + (arm_cpu_option_table): Add Neon and VFPv3 to Cortex-A8. + (arm_option_cpu_value): Add vfp3 and neon. + (aeabi_set_public_attributes): Support VFPv3 and NEON attributes. Fix + VFPv1 attribute. + +2006-04-25 Bob Wilson + + * config/xtensa-relax.c (widen_spec_list): Use new "WIDE." + syntax instead of hardcoded opcodes with ".w18" suffixes. + (wide_branch_opcode): New. + (build_transition): Use it to check for wide branch opcodes with + either ".w18" or ".w15" suffixes. + +2006-04-25 Bob Wilson + + * config/tc-xtensa.c (xtensa_create_literal_symbol, + xg_assemble_literal, xg_assemble_literal_space): Do not set the + frag's is_literal flag. + 2006-04-25 Bob Wilson * config/xtensa-relax.c (XCHAL_HAVE_WIDE_BRANCHES): Provide default. @@ -214,6 +1121,24 @@ * config/tc-m68k.c (m68k_cpus): Change cpu_cf5208 entries to use mcfemac instead of mcfmac. +2006-03-23 Michael Matz + + * config/tc-i386.c (type_names): Correct placement of 'static'. + (reloc): Map some more relocs to their 64 bit counterpart when + size is 8. + (output_insn): Work around breakage if DEBUG386 is defined. + (output_disp): A BFD_RELOC_64 with GOT_symbol as operand also + needs to be mapped to BFD_RELOC_X86_64_GOTPC64 or + BFD_RELOC_X86_64_GOTPC32. Also x86-64 handles pcrel addressing + different from i386. + (output_imm): Ditto. + (lex_got): Recognize @PLTOFF and @GOTPLT. Make @GOT accept also + Imm64. + (md_convert_frag): Jumps can now be larger than 2GB away, error + out in that case. + (tc_gen_reloc): New relocs are passed through. BFD_RELOC_64 + and BFD_RELOC_64_PCREL are mapped to BFD_RELOC_X86_64_GOTPC64. + 2006-03-22 Richard Sandiford Daniel Jacobowitz Phil Edwards