X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=gas%2Fconfig%2Ftc-arc.c;h=ed1e3fb5dd5c9504c66e1f377f3d85a4f322a33b;hb=2a1ebfb221f5f52a743b7ea4c504a7318956c49c;hp=c0bc3e45a4fffedb688911c8f5fd1803aa5ce541;hpb=bdfe53e3cfebb392b1a0ef50fdd02faafec6dc63;p=deliverable%2Fbinutils-gdb.git diff --git a/gas/config/tc-arc.c b/gas/config/tc-arc.c index c0bc3e45a4..ed1e3fb5dd 100644 --- a/gas/config/tc-arc.c +++ b/gas/config/tc-arc.c @@ -1,5 +1,5 @@ /* tc-arc.c -- Assembler for the ARC - Copyright (C) 1994-2016 Free Software Foundation, Inc. + Copyright (C) 1994-2020 Free Software Foundation, Inc. Contributor: Claudiu Zissulescu @@ -22,12 +22,12 @@ #include "as.h" #include "subsegs.h" -#include "struc-symbol.h" #include "dwarf2dbg.h" #include "dw2gencfi.h" #include "safe-ctype.h" #include "opcode/arc.h" +#include "opcode/arc-attrs.h" #include "elf/arc.h" #include "../opcodes/arc-ext.h" @@ -48,13 +48,14 @@ #define LP_INSN(x) ((MAJOR_OPCODE (x) == 0x4) \ && (SUB_OPCODE (x) == 0x28)) -/* Equal to MAX_PRECISION in atof-ieee.c. */ -#define MAX_LITTLENUMS 6 - #ifndef TARGET_WITH_CPU #define TARGET_WITH_CPU "arc700" #endif /* TARGET_WITH_CPU */ +#define ARC_GET_FLAG(s) (*symbol_get_tc (s)) +#define ARC_SET_FLAG(s,v) (*symbol_get_tc (s) |= (v)) +#define streq(a, b) (strcmp (a, b) == 0) + /* Enum used to enumerate the relaxable ins operands. */ enum rlx_operand_type { @@ -102,8 +103,18 @@ enum arc_rlx_types #define is_spfp_p(op) (((sc) == SPX)) #define is_dpfp_p(op) (((sc) == DPX)) #define is_fpuda_p(op) (((sc) == DPA)) -#define is_br_jmp_insn_p(op) (((op)->insn_class == BRANCH \ - || (op)->insn_class == JUMP)) +#define is_br_jmp_insn_p(op) (((op)->insn_class == BRANCH \ + || (op)->insn_class == JUMP \ + || (op)->insn_class == BRCC \ + || (op)->insn_class == BBIT0 \ + || (op)->insn_class == BBIT1 \ + || (op)->insn_class == BI \ + || (op)->insn_class == EI \ + || (op)->insn_class == ENTER \ + || (op)->insn_class == JLI \ + || (op)->insn_class == LOOP \ + || (op)->insn_class == LEAVE \ + )) #define is_kernel_insn_p(op) (((op)->insn_class == KERNEL)) #define is_nps400_p(op) (((sc) == NPS400)) @@ -147,6 +158,7 @@ static void arc_option (int); static void arc_extra_reloc (int); static void arc_extinsn (int); static void arc_extcorereg (int); +static void arc_attribute (int); const pseudo_typeS md_pseudo_table[] = { @@ -158,6 +170,7 @@ const pseudo_typeS md_pseudo_table[] = { "lcommon", arc_lcomm, 0 }, { "cpu", arc_option, 0 }, + { "arc_attribute", arc_attribute, 0 }, { "extinstruction", arc_extinsn, 0 }, { "extcoreregister", arc_extcorereg, EXT_CORE_REGISTER }, { "extauxregister", arc_extcorereg, EXT_AUX_REGISTER }, @@ -426,6 +439,21 @@ static struct hash_control *arc_aux_hash; /* The hash table of address types. */ static struct hash_control *arc_addrtype_hash; +#define ARC_CPU_TYPE_A6xx(NAME,EXTRA) \ + { #NAME, ARC_OPCODE_ARC600, bfd_mach_arc_arc600, \ + E_ARC_MACH_ARC600, EXTRA} +#define ARC_CPU_TYPE_A7xx(NAME,EXTRA) \ + { #NAME, ARC_OPCODE_ARC700, bfd_mach_arc_arc700, \ + E_ARC_MACH_ARC700, EXTRA} +#define ARC_CPU_TYPE_AV2EM(NAME,EXTRA) \ + { #NAME, ARC_OPCODE_ARCv2EM, bfd_mach_arc_arcv2, \ + EF_ARC_CPU_ARCV2EM, EXTRA} +#define ARC_CPU_TYPE_AV2HS(NAME,EXTRA) \ + { #NAME, ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2, \ + EF_ARC_CPU_ARCV2HS, EXTRA} +#define ARC_CPU_TYPE_NONE \ + { 0, 0, 0, 0, 0 } + /* A table of CPU names and opcode sets. */ static const struct cpu_type { @@ -437,21 +465,29 @@ static const struct cpu_type } cpu_types[] = { - { "arc600", ARC_OPCODE_ARC600, bfd_mach_arc_arc600, - E_ARC_MACH_ARC600, 0x00}, - { "arc700", ARC_OPCODE_ARC700, bfd_mach_arc_arc700, - E_ARC_MACH_ARC700, 0x00}, - { "nps400", ARC_OPCODE_ARC700 , bfd_mach_arc_arc700, - E_ARC_MACH_ARC700, ARC_NPS400}, - { "arcem", ARC_OPCODE_ARCv2EM, bfd_mach_arc_arcv2, - EF_ARC_CPU_ARCV2EM, 0x00}, - { "archs", ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2, - EF_ARC_CPU_ARCV2HS, ARC_CD}, - { 0, 0, 0, 0, 0 } + #include "elf/arc-cpu.def" }; /* Information about the cpu/variant we're assembling for. */ -static struct cpu_type selected_cpu; +static struct cpu_type selected_cpu = { 0, 0, 0, E_ARC_OSABI_CURRENT, 0 }; + +/* TRUE if current assembly code uses RF16 only registers. */ +static bfd_boolean rf16_only = TRUE; + +/* MPY option. */ +static unsigned mpy_option = 0; + +/* Use PIC. */ +static unsigned pic_option = 0; + +/* Use small data. */ +static unsigned sda_option = 0; + +/* Use TLS. */ +static unsigned tls_option = 0; + +/* Command line given features. */ +static unsigned cl_features = 0; /* Used by the arc_reloc_op table. Order is important. */ #define O_gotoff O_md1 /* @gotoff relocation. */ @@ -648,15 +684,15 @@ const struct arc_relaxable_ins arc_relaxable_insns[] = const unsigned arc_num_relaxable_ins = ARRAY_SIZE (arc_relaxable_insns); -/* Flags to set in the elf header. */ -static const flagword arc_initial_eflag = 0x00; - /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ symbolS * GOT_symbol = 0; /* Set to TRUE when we assemble instructions. */ static bfd_boolean assembling_insn = FALSE; +/* List with attributes set explicitly. */ +static bfd_boolean attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES]; + /* Functions implementation. */ /* Return a pointer to ARC_OPCODE_HASH_ENTRY that identifies all @@ -759,7 +795,7 @@ md_number_to_chars_midend (char *buf, unsigned long long val, int n) md_number_to_chars (buf, val, n); break; case 6: - md_number_to_chars (buf, (val & 0xffff00000000) >> 32, 2); + md_number_to_chars (buf, (val & 0xffff00000000ull) >> 32, 2); md_number_to_chars_midend (buf + 2, (val & 0xffffffff), 4); break; case 4: @@ -767,7 +803,7 @@ md_number_to_chars_midend (char *buf, unsigned long long val, int n) md_number_to_chars (buf + 2, (val & 0xffff), 2); break; case 8: - md_number_to_chars_midend (buf, (val & 0xffffffff00000000) >> 32, 4); + md_number_to_chars_midend (buf, (val & 0xffffffff00000000ull) >> 32, 4); md_number_to_chars_midend (buf + 4, (val & 0xffffffff), 4); break; default: @@ -775,6 +811,28 @@ md_number_to_chars_midend (char *buf, unsigned long long val, int n) } } +/* Check if a feature is allowed for a specific CPU. */ + +static void +arc_check_feature (void) +{ + unsigned i; + + if (!selected_cpu.features + || !selected_cpu.name) + return; + + for (i = 0; i < ARRAY_SIZE (feature_list); i++) + if ((selected_cpu.features & feature_list[i].feature) + && !(selected_cpu.flags & feature_list[i].cpus)) + as_bad (_("invalid %s option for %s cpu"), feature_list[i].name, + selected_cpu.name); + + for (i = 0; i < ARRAY_SIZE (conflict_list); i++) + if ((selected_cpu.features & conflict_list[i]) == conflict_list[i]) + as_bad(_("conflicting ISA extension attributes.")); +} + /* Select an appropriate entry from CPU_TYPES based on ARG and initialise the relevant static global variables. Parameter SEL describes where this selection originated from. */ @@ -782,7 +840,6 @@ md_number_to_chars_midend (char *buf, unsigned long long val, int n) static void arc_select_cpu (const char *arg, enum mach_selection_type sel) { - int cpu_flags = 0; int i; /* We should only set a default if we've not made a selection from some @@ -790,6 +847,10 @@ arc_select_cpu (const char *arg, enum mach_selection_type sel) gas_assert (sel != MACH_SELECTION_FROM_DEFAULT || mach_selection_mode == MACH_SELECTION_NONE); + if ((mach_selection_mode == MACH_SELECTION_FROM_CPU_DIRECTIVE) + && (sel == MACH_SELECTION_FROM_CPU_DIRECTIVE)) + as_bad (_("Multiple .cpu directives found")); + /* Look for a matching entry in CPU_TYPES array. */ for (i = 0; cpu_types[i].name; ++i) { @@ -807,24 +868,27 @@ arc_select_cpu (const char *arg, enum mach_selection_type sel) && selected_cpu.mach != cpu_types[i].mach) { as_warn (_("Command-line value overrides \".cpu\" directive")); - return; } + return; } - /* Initialise static global data about selected machine type. */ - selected_cpu.flags = cpu_types[i].flags; - selected_cpu.name = cpu_types[i].name; - selected_cpu.features = cpu_types[i].features; - selected_cpu.mach = cpu_types[i].mach; - cpu_flags = cpu_types[i].eflags; + /* Initialise static global data about selected machine type. */ + selected_cpu.flags = cpu_types[i].flags; + selected_cpu.name = cpu_types[i].name; + selected_cpu.features = cpu_types[i].features | cl_features; + selected_cpu.mach = cpu_types[i].mach; + selected_cpu.eflags = ((selected_cpu.eflags & ~EF_ARC_MACH_MSK) + | cpu_types[i].eflags); break; } } if (!cpu_types[i].name) as_fatal (_("unknown architecture: %s\n"), arg); - gas_assert (cpu_flags != 0); - selected_cpu.eflags = (arc_initial_eflag & ~EF_ARC_MACH_MSK) | cpu_flags; + + /* Check if set features are compatible with the chosen CPU. */ + arc_check_feature (); + mach_selection_mode = sel; } @@ -934,6 +998,7 @@ arc_option (int ignore ATTRIBUTE_UNUSED) c = get_symbol_name (&cpu); + cpu_name = cpu; if ((!strcmp ("ARC600", cpu)) || (!strcmp ("ARC601", cpu)) || (!strcmp ("A6", cpu))) @@ -947,19 +1012,8 @@ arc_option (int ignore ATTRIBUTE_UNUSED) cpu_name = "archs"; else if (!strcmp ("NPS400", cpu)) cpu_name = "nps400"; - else - cpu_name = NULL; - - if (cpu_name != NULL) - arc_select_cpu (cpu_name, MACH_SELECTION_FROM_CPU_DIRECTIVE); - else - as_fatal (_("invalid architecture `%s' in .cpu directive"), cpu); - - if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, selected_cpu.mach)) - as_fatal (_("could not set architecture and machine")); - /* Set elf header flags. */ - bfd_set_private_flags (stdoutput, selected_cpu.eflags); + arc_select_cpu (cpu_name, MACH_SELECTION_FROM_CPU_DIRECTIVE); restore_line_pointer (c); demand_empty_rest_of_line (); @@ -1038,6 +1092,102 @@ debug_exp (expressionS *t) fflush (stderr); } +/* Helper for parsing an argument, used for sorting out the relocation + type. */ + +static void +parse_reloc_symbol (expressionS *resultP) +{ + char *reloc_name, c, *sym_name; + size_t len; + int i; + const struct arc_reloc_op_tag *r; + expressionS right; + symbolS *base; + + /* A relocation operand has the following form + @identifier@relocation_type. The identifier is already in + tok! */ + if (resultP->X_op != O_symbol) + { + as_bad (_("No valid label relocation operand")); + resultP->X_op = O_illegal; + return; + } + + /* Parse @relocation_type. */ + input_line_pointer++; + c = get_symbol_name (&reloc_name); + len = input_line_pointer - reloc_name; + if (len == 0) + { + as_bad (_("No relocation operand")); + resultP->X_op = O_illegal; + return; + } + + /* Go through known relocation and try to find a match. */ + r = &arc_reloc_op[0]; + for (i = arc_num_reloc_op - 1; i >= 0; i--, r++) + if (len == r->length + && memcmp (reloc_name, r->name, len) == 0) + break; + if (i < 0) + { + as_bad (_("Unknown relocation operand: @%s"), reloc_name); + resultP->X_op = O_illegal; + return; + } + + *input_line_pointer = c; + SKIP_WHITESPACE_AFTER_NAME (); + /* Extra check for TLS: base. */ + if (*input_line_pointer == '@') + { + if (resultP->X_op_symbol != NULL + || resultP->X_op != O_symbol) + { + as_bad (_("Unable to parse TLS base: %s"), + input_line_pointer); + resultP->X_op = O_illegal; + return; + } + input_line_pointer++; + c = get_symbol_name (&sym_name); + base = symbol_find_or_make (sym_name); + resultP->X_op = O_subtract; + resultP->X_op_symbol = base; + restore_line_pointer (c); + right.X_add_number = 0; + } + + if ((*input_line_pointer != '+') + && (*input_line_pointer != '-')) + right.X_add_number = 0; + else + { + /* Parse the constant of a complex relocation expression + like @identifier@reloc +/- const. */ + if (! r->complex_expr) + { + as_bad (_("@%s is not a complex relocation."), r->name); + resultP->X_op = O_illegal; + return; + } + expression (&right); + if (right.X_op != O_constant) + { + as_bad (_("Bad expression: @%s + %s."), + r->name, input_line_pointer); + resultP->X_op = O_illegal; + return; + } + } + + resultP->X_md = r->op; + resultP->X_add_number = right.X_add_number; +} + /* Parse the arguments to an opcode. */ static int @@ -1050,11 +1200,6 @@ tokenize_arguments (char *str, bfd_boolean saw_arg = FALSE; int brk_lvl = 0; int num_args = 0; - int i; - size_t len; - const struct arc_reloc_op_tag *r; - expressionS tmpE; - char *reloc_name, c; memset (tok, 0, sizeof (*tok) * ntok); @@ -1116,95 +1261,21 @@ tokenize_arguments (char *str, goto err; /* Parse @label. */ + input_line_pointer++; tok->X_op = O_symbol; tok->X_md = O_absent; expression (tok); - if (*input_line_pointer != '@') - goto normalsymbol; /* This is not a relocation. */ - relocationsym: - - /* A relocation opernad has the following form - @identifier@relocation_type. The identifier is already - in tok! */ - if (tok->X_op != O_symbol) - { - as_bad (_("No valid label relocation operand")); - goto err; - } - - /* Parse @relocation_type. */ - input_line_pointer++; - c = get_symbol_name (&reloc_name); - len = input_line_pointer - reloc_name; - if (len == 0) - { - as_bad (_("No relocation operand")); - goto err; - } - - /* Go through known relocation and try to find a match. */ - r = &arc_reloc_op[0]; - for (i = arc_num_reloc_op - 1; i >= 0; i--, r++) - if (len == r->length - && memcmp (reloc_name, r->name, len) == 0) - break; - if (i < 0) - { - as_bad (_("Unknown relocation operand: @%s"), reloc_name); - goto err; - } - - *input_line_pointer = c; - SKIP_WHITESPACE_AFTER_NAME (); - /* Extra check for TLS: base. */ if (*input_line_pointer == '@') - { - symbolS *base; - if (tok->X_op_symbol != NULL - || tok->X_op != O_symbol) - { - as_bad (_("Unable to parse TLS base: %s"), - input_line_pointer); - goto err; - } - input_line_pointer++; - char *sym_name; - c = get_symbol_name (&sym_name); - base = symbol_find_or_make (sym_name); - tok->X_op = O_subtract; - tok->X_op_symbol = base; - restore_line_pointer (c); - tmpE.X_add_number = 0; - } - if ((*input_line_pointer != '+') - && (*input_line_pointer != '-')) - { - tmpE.X_add_number = 0; - } - else - { - /* Parse the constant of a complex relocation expression - like @identifier@reloc +/- const. */ - if (! r->complex_expr) - { - as_bad (_("@%s is not a complex relocation."), r->name); - goto err; - } - expression (&tmpE); - if (tmpE.X_op != O_constant) - { - as_bad (_("Bad expression: @%s + %s."), - r->name, input_line_pointer); - goto err; - } - } - - tok->X_md = r->op; - tok->X_add_number = tmpE.X_add_number; + parse_reloc_symbol (tok); debug_exp (tok); + if (tok->X_op == O_illegal + || tok->X_op == O_absent + || num_args == ntok) + goto err; + saw_comma = FALSE; saw_arg = TRUE; tok++; @@ -1228,9 +1299,8 @@ tokenize_arguments (char *str, identifier@relocation_type, if it is the case parse the relocation type as well. */ if (*input_line_pointer == '@') - goto relocationsym; + parse_reloc_symbol (tok); - normalsymbol: debug_exp (tok); if (tok->X_op == O_illegal @@ -1541,7 +1611,7 @@ allocate_tok (expressionS *tok, int ntok, int cidx) return 0; /* No space left. */ if (cidx > ntok) - return 0; /* Incorect args. */ + return 0; /* Incorrect args. */ memcpy (&tok[ntok+1], &tok[ntok], sizeof (*tok)); @@ -1555,19 +1625,19 @@ allocate_tok (expressionS *tok, int ntok, int cidx) static bfd_boolean check_cpu_feature (insn_subclass_t sc) { - if (is_code_density_p (sc) && !(selected_cpu.features & ARC_CD)) + if (is_code_density_p (sc) && !(selected_cpu.features & CD)) return FALSE; - if (is_spfp_p (sc) && !(selected_cpu.features & ARC_SPFP)) + if (is_spfp_p (sc) && !(selected_cpu.features & SPX)) return FALSE; - if (is_dpfp_p (sc) && !(selected_cpu.features & ARC_DPFP)) + if (is_dpfp_p (sc) && !(selected_cpu.features & DPX)) return FALSE; - if (is_fpuda_p (sc) && !(selected_cpu.features & ARC_FPUDA)) + if (is_fpuda_p (sc) && !(selected_cpu.features & DPA)) return FALSE; - if (is_nps400_p (sc) && !(selected_cpu.features & ARC_NPS400)) + if (is_nps400_p (sc) && !(selected_cpu.features & NPS400)) return FALSE; return TRUE; @@ -1600,6 +1670,10 @@ parse_opcode_flags (const struct arc_opcode *opcode, int cl_matches = 0; struct arc_flags *pflag = NULL; + /* Check if opcode has implicit flag classes. */ + if (cl_flags->flag_class & F_CLASS_IMPLICIT) + continue; + /* Check for extension conditional codes. */ if (ext_condcode.arc_ext_condcode && cl_flags->flag_class & F_CLASS_EXTEND) @@ -1666,7 +1740,8 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry, int *pntok, struct arc_flags *first_pflag, int nflgs, - int *pcpumatch) + int *pcpumatch, + const char **errmsg) { const struct arc_opcode *opcode; struct arc_opcode_hash_entry_iterator iter; @@ -1720,9 +1795,22 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry, switch (operand->flags & ARC_OPERAND_TYPECHECK_MASK) { case ARC_OPERAND_ADDRTYPE: - /* Check to be an address type. */ - if (tok[tokidx].X_op != O_addrtype) - goto match_failed; + { + *errmsg = NULL; + + /* Check to be an address type. */ + if (tok[tokidx].X_op != O_addrtype) + goto match_failed; + + /* All address type operands need to have an insert + method in order to check that we have the correct + address type. */ + gas_assert (operand->insert != NULL); + (*operand->insert) (0, tok[tokidx].X_add_number, + errmsg); + if (*errmsg != NULL) + goto match_failed; + } break; case ARC_OPERAND_IR: @@ -1746,11 +1834,11 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry, /* Special handling? */ if (operand->insert) { - const char *errmsg = NULL; + *errmsg = NULL; (*operand->insert)(0, regno (tok[tokidx].X_add_number), - &errmsg); - if (errmsg) + errmsg); + if (*errmsg) { if (operand->flags & ARC_OPERAND_IGNORE) { @@ -1809,13 +1897,20 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry, case O_symbol: { const char *p; + char *tmpp, *pp; const struct arc_aux_reg *auxr; if (opcode->insn_class != AUXREG) goto de_fault; p = S_GET_NAME (tok[tokidx].X_add_symbol); - auxr = hash_find (arc_aux_hash, p); + /* For compatibility reasons, an aux register can + be spelled with upper or lower case + letters. */ + tmpp = strdup (p); + for (pp = tmpp; *pp; ++pp) *pp = TOLOWER (*pp); + + auxr = hash_find (arc_aux_hash, tmpp); if (auxr) { /* We modify the token array here, safe in the @@ -1826,6 +1921,7 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry, tok[tokidx].X_add_number = auxr->address; ARC_SET_FLAG (tok[tokidx].X_add_symbol, ARC_FLAG_AUX); } + free (tmpp); if (tok[tokidx].X_op != O_constant) goto de_fault; @@ -1853,7 +1949,7 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry, if (val < min || val > max) goto match_failed; - /* Check alignmets. */ + /* Check alignments. */ if ((operand->flags & ARC_OPERAND_ALIGNED32) && (val & 0x03)) goto match_failed; @@ -1866,11 +1962,11 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry, { if (operand->insert) { - const char *errmsg = NULL; + *errmsg = NULL; (*operand->insert)(0, tok[tokidx].X_add_number, - &errmsg); - if (errmsg) + errmsg); + if (*errmsg) goto match_failed; } else if (!(operand->flags & ARC_OPERAND_IGNORE)) @@ -1891,11 +1987,11 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry, regs |= get_register (tok[tokidx].X_op_symbol); if (operand->insert) { - const char *errmsg = NULL; + *errmsg = NULL; (*operand->insert)(0, regs, - &errmsg); - if (errmsg) + errmsg); + if (*errmsg) goto match_failed; } else @@ -2256,6 +2352,66 @@ find_special_case (const char *opname, return entry; } +/* Autodetect cpu attribute list. */ + +static void +autodetect_attributes (const struct arc_opcode *opcode, + const expressionS *tok, + int ntok) +{ + unsigned i; + struct mpy_type + { + unsigned feature; + unsigned encoding; + } mpy_list[] = {{ MPY1E, 1 }, { MPY6E, 6 }, { MPY7E, 7 }, { MPY8E, 8 }, + { MPY9E, 9 }}; + + for (i = 0; i < ARRAY_SIZE (feature_list); i++) + if (opcode->subclass == feature_list[i].feature) + selected_cpu.features |= feature_list[i].feature; + + for (i = 0; i < ARRAY_SIZE (mpy_list); i++) + if (opcode->subclass == mpy_list[i].feature) + mpy_option = mpy_list[i].encoding; + + for (i = 0; i < (unsigned) ntok; i++) + { + switch (tok[i].X_md) + { + case O_gotoff: + case O_gotpc: + case O_plt: + pic_option = 2; + break; + case O_sda: + sda_option = 2; + break; + case O_tlsgd: + case O_tlsie: + case O_tpoff9: + case O_tpoff: + case O_dtpoff9: + case O_dtpoff: + tls_option = 1; + break; + default: + break; + } + + switch (tok[i].X_op) + { + case O_register: + if ((tok[i].X_add_number >= 4 && tok[i].X_add_number <= 9) + || (tok[i].X_add_number >= 16 && tok[i].X_add_number <= 25)) + rf16_only = FALSE; + break; + default: + break; + } + } +} + /* Given an opcode name, pre-tockenized set of argumenst and the opcode flags, take it all the way through emission. */ @@ -2269,6 +2425,7 @@ assemble_tokens (const char *opname, bfd_boolean found_something = FALSE; const struct arc_opcode_hash_entry *entry; int cpumatch = 1; + const char *errmsg = NULL; /* Search opcodes. */ entry = arc_find_opcode (opname); @@ -2285,11 +2442,12 @@ assemble_tokens (const char *opname, frag_now->fr_file, frag_now->fr_line, opname); found_something = TRUE; opcode = find_opcode_match (entry, tok, &ntok, pflags, - nflgs, &cpumatch); + nflgs, &cpumatch, &errmsg); if (opcode != NULL) { struct arc_insn insn; + autodetect_attributes (opcode, tok, ntok); assemble_insn (opcode, tok, ntok, pflags, nflgs, &insn); emit_insn (&insn); return; @@ -2299,7 +2457,10 @@ assemble_tokens (const char *opname, if (found_something) { if (cpumatch) - as_bad (_("inappropriate arguments for opcode '%s'"), opname); + if (errmsg) + as_bad (_("%s for instruction '%s'"), errmsg, opname); + else + as_bad (_("inappropriate arguments for opcode '%s'"), opname); else as_bad (_("opcode '%s' not supported for target %s"), opname, selected_cpu.name); @@ -2323,7 +2484,7 @@ md_assemble (char *str) opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_0123468"); opname = xmemdup0 (str, opnamelen); - /* Signalize we are assmbling the instructions. */ + /* Signalize we are assembling the instructions. */ assembling_insn = TRUE; /* Tokenize the flags. */ @@ -2561,7 +2722,7 @@ valueT md_section_align (segT segment, valueT size) { - int align = bfd_get_section_alignment (stdoutput, segment); + int align = bfd_section_alignment (segment); return ((size + (1 << align) - 1) & (-((valueT) 1 << align))); } @@ -2602,7 +2763,7 @@ md_pcrel_from_section (fixS *fixP, /* The hardware calculates relative to the start of the insn, but this relocation is relative to location of the LIMM, compensate. The base always needs to be - substracted by 4 as we do not support this type of PCrel + subtracted by 4 as we do not support this type of PCrel relocation for short instructions. */ base -= 4; /* Fall through. */ @@ -2636,7 +2797,7 @@ md_pcrel_from_section (fixS *fixP, return base; } -/* Given a BFD relocation find the coresponding operand. */ +/* Given a BFD relocation find the corresponding operand. */ static const struct arc_operand * find_operand_for_reloc (extended_bfd_reloc_code_real_type reloc) @@ -2680,7 +2841,7 @@ insert_operand (unsigned long long insn, val, min, max, file, line); } - pr_debug ("insert field: %ld <= %ld <= %ld in 0x%08llx\n", + pr_debug ("insert field: %ld <= %lld <= %ld in 0x%08llx\n", min, val, max, insn); if ((operand->flags & ARC_OPERAND_ALIGNED32) @@ -2813,7 +2974,7 @@ md_apply_fix (fixS *fixP, case BFD_RELOC_ARC_32_ME: /* This is a pc-relative value in a LIMM. Adjust it to the address of the instruction not to the address of the - LIMM. Note: it is not anylonger valid this afirmation as + LIMM. Note: it is not any longer valid this affirmation as the linker consider ARC_PC32 a fixup to entire 64 bit insn. */ fixP->fx_offset += fixP->fx_frag->fr_address; @@ -2826,8 +2987,10 @@ md_apply_fix (fixS *fixP, break; default: if ((int) fixP->fx_r_type < 0) - as_fatal (_("PC relative relocation not allowed for (internal) type %d"), - fixP->fx_r_type); + as_bad_where (fixP->fx_file, fixP->fx_line, + _("PC relative relocation not allowed for (internal)" + " type %d"), + fixP->fx_r_type); break; } } @@ -2882,7 +3045,7 @@ md_apply_fix (fixS *fixP, return; } - /* Addjust the value if we have a constant. */ + /* Adjust the value if we have a constant. */ value += fx_offset; /* For hosts with longs bigger than 32-bits make sure that the top @@ -3121,7 +3284,7 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, int size, fix; struct arc_relax_type *relax_arg = &fragP->tc_frag_data; - fix = (fragP->fr_fix < 0 ? 0 : fragP->fr_fix); + fix = fragP->fr_fix; dest = fragP->fr_literal + fix; table_entry = TC_GENERIC_RELAX_TABLE + fragP->fr_subtype; @@ -3161,10 +3324,7 @@ md_undefined_symbol (char *name) GOTPC reference to _GLOBAL_OFFSET_TABLE_. */ if (((*name == '_') && (*(name+1) == 'G') - && (strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)) - || ((*name == '_') - && (*(name+1) == 'D') - && (strcmp (name, DYNAMIC_STRUCT_NAME) == 0))) + && (strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0))) { if (!GOT_symbol) { @@ -3192,16 +3352,18 @@ md_atof (int type, char *litP, int *sizeP) /* Called for any expression that can not be recognized. When the function is called, `input_line_pointer' will point to the start of - the expression. */ + the expression. We use it when we have complex operations like + @label1 - @label2. */ void -md_operand (expressionS *expressionP ATTRIBUTE_UNUSED) +md_operand (expressionS *expressionP) { char *p = input_line_pointer; if (*p == '@') { input_line_pointer++; expressionP->X_op = O_symbol; + expressionP->X_md = O_absent; expression (expressionP); } } @@ -3220,7 +3382,8 @@ arc_parse_name (const char *name, if (!assembling_insn) return FALSE; - if (e->X_op == O_symbol) + if (e->X_op == O_symbol + && e->X_md == O_absent) return FALSE; sym = hash_find (arc_reg_hash, name); @@ -3291,11 +3454,9 @@ md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED) break; case OPTION_CD: - /* This option has an effect only on ARC EM. */ - if (selected_cpu.flags & ARC_OPCODE_ARCv2EM) - selected_cpu.features |= ARC_CD; - else - as_warn (_("Code density option invalid for selected CPU")); + selected_cpu.features |= CD; + cl_features |= CD; + arc_check_feature (); break; case OPTION_RELAX: @@ -3303,23 +3464,27 @@ md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED) break; case OPTION_NPS400: - selected_cpu.features |= ARC_NPS400; + selected_cpu.features |= NPS400; + cl_features |= NPS400; + arc_check_feature (); break; case OPTION_SPFP: - selected_cpu.features |= ARC_SPFP; + selected_cpu.features |= SPX; + cl_features |= SPX; + arc_check_feature (); break; case OPTION_DPFP: - selected_cpu.features |= ARC_DPFP; + selected_cpu.features |= DPX; + cl_features |= DPX; + arc_check_feature (); break; case OPTION_FPUDA: - /* This option has an effect only on ARC EM. */ - if (selected_cpu.flags & ARC_OPCODE_ARCv2EM) - selected_cpu.features |= ARC_FPUDA; - else - as_warn (_("FPUDA invalid for selected CPU")); + selected_cpu.features |= DPA; + cl_features |= DPA; + arc_check_feature (); break; /* Dummy options are accepted but have no effect. */ @@ -3352,22 +3517,53 @@ md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED) return 1; } +/* Display the list of cpu names for use in the help text. */ + +static void +arc_show_cpu_list (FILE *stream) +{ + int i, offset; + static const char *space_buf = " "; + + fprintf (stream, "%s", space_buf); + offset = strlen (space_buf); + for (i = 0; cpu_types[i].name != NULL; ++i) + { + bfd_boolean last = (cpu_types[i + 1].name == NULL); + + /* If displaying the new cpu name string, and the ', ' (for all + but the last one) will take us past a target width of 80 + characters, then it's time for a new line. */ + if (offset + strlen (cpu_types[i].name) + (last ? 0 : 2) > 80) + { + fprintf (stream, "\n%s", space_buf); + offset = strlen (space_buf); + } + + fprintf (stream, "%s%s", cpu_types[i].name, (last ? "\n" : ", ")); + offset += strlen (cpu_types [i].name) + (last ? 0 : 2); + } +} + void md_show_usage (FILE *stream) { fprintf (stream, _("ARC-specific assembler options:\n")); - fprintf (stream, " -mcpu=\t assemble for CPU " - "(default: %s)\n", TARGET_WITH_CPU); - fprintf (stream, " -mcpu=nps400\t\t same as -mcpu=arc700 -mnps400\n"); + fprintf (stream, " -mcpu=\t (default: %s), assemble for" + " CPU , one of:\n", TARGET_WITH_CPU); + arc_show_cpu_list (stream); + fprintf (stream, "\n"); fprintf (stream, " -mA6/-mARC600/-mARC601 same as -mcpu=arc600\n"); fprintf (stream, " -mA7/-mARC700\t\t same as -mcpu=arc700\n"); fprintf (stream, " -mEM\t\t\t same as -mcpu=arcem\n"); fprintf (stream, " -mHS\t\t\t same as -mcpu=archs\n"); fprintf (stream, " -mnps400\t\t enable NPS-400 extended instructions\n"); - fprintf (stream, " -mspfp\t\t enable single-precision floating point instructions\n"); - fprintf (stream, " -mdpfp\t\t enable double-precision floating point instructions\n"); + fprintf (stream, " -mspfp\t\t enable single-precision floating point" + " instructions\n"); + fprintf (stream, " -mdpfp\t\t enable double-precision floating point" + " instructions\n"); fprintf (stream, " -mfpuda\t\t enable double-precision assist floating " "point\n\t\t\t instructions for ARC EM\n"); @@ -3769,9 +3965,8 @@ assemble_insn (const struct arc_opcode *opcode, { case O_plt: if (opcode->insn_class == JUMP) - as_bad_where (frag_now->fr_file, frag_now->fr_line, - _("Unable to use @plt relocatio for insn %s"), - opcode->name); + as_bad (_("Unable to use @plt relocation for insn %s"), + opcode->name); needGOTSymbol = TRUE; reloc = find_reloc ("plt", opcode->name, pflags, nflg, @@ -3784,12 +3979,21 @@ assemble_insn (const struct arc_opcode *opcode, reloc = ARC_RELOC_TABLE (t->X_md)->reloc; break; case O_pcl: - reloc = ARC_RELOC_TABLE (t->X_md)->reloc; - if (arc_opcode_len (opcode) == 2 - || opcode->insn_class == JUMP) - as_bad_where (frag_now->fr_file, frag_now->fr_line, - _("Unable to use @pcl relocation for insn %s"), - opcode->name); + if (operand->flags & ARC_OPERAND_LIMM) + { + reloc = ARC_RELOC_TABLE (t->X_md)->reloc; + if (arc_opcode_len (opcode) == 2 + || opcode->insn_class == JUMP) + as_bad (_("Unable to use @pcl relocation for insn %s"), + opcode->name); + } + else + { + /* This is a relaxed operand which initially was + limm, choose whatever we have defined in the + opcode as reloc. */ + reloc = operand->default_reloc; + } break; case O_sda: reloc = find_reloc ("sda", opcode->name, @@ -3849,7 +4053,15 @@ assemble_insn (const struct arc_opcode *opcode, fixup = &insn->fixups[insn->nfixups++]; fixup->exp = *t; fixup->reloc = reloc; - pcrel = (operand->flags & ARC_OPERAND_PCREL) ? 1 : 0; + if ((int) reloc < 0) + pcrel = (operand->flags & ARC_OPERAND_PCREL) ? 1 : 0; + else + { + reloc_howto_type *reloc_howto = + bfd_reloc_type_lookup (stdoutput, + (bfd_reloc_code_real_type) fixup->reloc); + pcrel = reloc_howto->pc_relative; + } fixup->pcrel = pcrel; fixup->islong = (operand->flags & ARC_OPERAND_LIMM) ? TRUE : FALSE; @@ -3866,11 +4078,19 @@ assemble_insn (const struct arc_opcode *opcode, if (!strcmp (flg_operand->name, "d")) has_delay_slot = TRUE; - /* There is an exceptional case when we cannot insert a flag - just as it is. The .T flag must be handled in relation with - the relative address. */ - if (!strcmp (flg_operand->name, "t") - || !strcmp (flg_operand->name, "nt")) + /* There is an exceptional case when we cannot insert a flag just as + it is. On ARCv2 the '.t' and '.nt' flags must be handled in + relation with the relative address. Unfortunately, some of the + ARC700 extensions (NPS400) also have a '.nt' flag that should be + handled in the normal way. + + Flag operands don't have an architecture field, so we can't + directly validate that FLAG_OPERAND is valid for the current + architecture, what we do instead is just validate that we're + assembling for an ARCv2 architecture. */ + if ((selected_cpu.flags & ARC_OPCODE_ARCV2) + && (!strcmp (flg_operand->name, "t") + || !strcmp (flg_operand->name, "nt"))) { unsigned bitYoperand = 0; /* FIXME! move selection bbit/brcc in arc-opc.c. */ @@ -3931,8 +4151,14 @@ assemble_insn (const struct arc_opcode *opcode, /* Check if the current instruction is legally used. */ if (arc_last_insns[1].has_delay_slot && is_br_jmp_insn_p (arc_last_insns[0].opcode)) - as_bad_where (frag_now->fr_file, frag_now->fr_line, - _("A jump/branch instruction in delay slot.")); + as_bad (_("Insn %s has a jump/branch instruction %s in its delay slot."), + arc_last_insns[1].opcode->name, + arc_last_insns[0].opcode->name); + if (arc_last_insns[1].has_delay_slot + && arc_last_insns[0].has_limm) + as_bad (_("Insn %s has an instruction %s with limm in its delay slot."), + arc_last_insns[1].opcode->name, + arc_last_insns[0].opcode->name); } void @@ -4000,7 +4226,7 @@ arc_check_reloc (expressionS *exp, if (*r_type_p == BFD_RELOC_32 && exp->X_op == O_subtract && exp->X_op_symbol != NULL - && exp->X_op_symbol->bsym->section == now_seg) + && S_GET_SEGMENT (exp->X_op_symbol) == now_seg) *r_type_p = BFD_RELOC_ARC_32_PCREL; } @@ -4108,10 +4334,15 @@ arc_frob_label (symbolS * sym) int arc_pcrel_adjust (fragS *fragP) { + pr_debug ("arc_pcrel_adjust: address=%ld, fix=%ld, PCrel %s\n", + fragP->fr_address, fragP->fr_fix, + fragP->tc_frag_data.pcrel ? "Y" : "N"); + if (!fragP->tc_frag_data.pcrel) return fragP->fr_address + fragP->fr_fix; - return 0; + /* Take into account the PCL rounding. */ + return (fragP->fr_address + fragP->fr_fix) & 0x03; } /* Initialize the DWARF-2 unwind information for this procedure. */ @@ -4175,6 +4406,10 @@ tokenize_extinsn (extInstruction_t *einsn) insn_name = xstrdup (p); restore_line_pointer (c); + /* Convert to lower case. */ + for (p = insn_name; *p; ++p) + *p = TOLOWER (*p); + /* 2nd: get major opcode. */ if (*input_line_pointer != ',') { @@ -4313,8 +4548,7 @@ arc_set_ext_seg (void) if (!arcext_section) { arcext_section = subseg_new (".arcextmap", 0); - bfd_set_section_flags (stdoutput, arcext_section, - SEC_READONLY | SEC_HAS_CONTENTS); + bfd_set_section_flags (arcext_section, SEC_READONLY | SEC_HAS_CONTENTS); } else subseg_set (arcext_section, 0); @@ -4423,7 +4657,7 @@ arc_extinsn (int ignore ATTRIBUTE_UNUSED) create_extinst_section (&einsn); } -static void +static bfd_boolean tokenize_extregister (extRegister_t *ereg, int opertype) { char *name; @@ -4448,20 +4682,23 @@ tokenize_extregister (extRegister_t *ereg, int opertype) if (*input_line_pointer != ',') { - as_bad (_("expected comma after register name")); + as_bad (_("expected comma after name")); ignore_rest_of_line (); free (name); - return; + return FALSE; } input_line_pointer++; number = get_absolute_expression (); - if (number < 0) + if ((number < 0) + && (opertype != EXT_AUX_REGISTER)) { - as_bad (_("negative operand number %d"), number); + as_bad (_("%s second argument cannot be a negative number %d"), + isCore_p ? "extCoreRegister's" : "extCondCode's", + number); ignore_rest_of_line (); free (name); - return; + return FALSE; } if (isReg_p) @@ -4474,7 +4711,7 @@ tokenize_extregister (extRegister_t *ereg, int opertype) as_bad (_("expected comma after register number")); ignore_rest_of_line (); free (name); - return; + return FALSE; } input_line_pointer++; @@ -4495,7 +4732,7 @@ tokenize_extregister (extRegister_t *ereg, int opertype) as_bad (_("invalid mode")); ignore_rest_of_line (); free (name); - return; + return FALSE; } else { @@ -4513,7 +4750,7 @@ tokenize_extregister (extRegister_t *ereg, int opertype) as_bad (_("expected comma after register mode")); ignore_rest_of_line (); free (name); - return; + return FALSE; } input_line_pointer++; @@ -4528,7 +4765,7 @@ tokenize_extregister (extRegister_t *ereg, int opertype) as_bad (_("shortcut designator invalid")); ignore_rest_of_line (); free (name); - return; + return FALSE; } else { @@ -4540,6 +4777,7 @@ tokenize_extregister (extRegister_t *ereg, int opertype) ereg->name = name; ereg->number = number; ereg->imode = imode; + return TRUE; } /* Create an extension register/condition description in the arc @@ -4553,7 +4791,7 @@ tokenize_extregister (extRegister_t *ereg, int opertype) [2]: Value. [3]+ Name. - For auxilirary registers: + For auxiliary registers: [2..5]: Value. [6]+ Name @@ -4615,7 +4853,8 @@ arc_extcorereg (int opertype) struct arc_flag_operand *ccode; memset (&ereg, 0, sizeof (ereg)); - tokenize_extregister (&ereg, opertype); + if (!tokenize_extregister (&ereg, opertype)) + return; switch (opertype) { @@ -4666,6 +4905,217 @@ arc_extcorereg (int opertype) create_extcore_section (&ereg, opertype); } +/* Parse a .arc_attribute directive. */ + +static void +arc_attribute (int ignored ATTRIBUTE_UNUSED) +{ + int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC); + + if (tag < NUM_KNOWN_OBJ_ATTRIBUTES) + attributes_set_explicitly[tag] = TRUE; +} + +/* Set an attribute if it has not already been set by the user. */ + +static void +arc_set_attribute_int (int tag, int value) +{ + if (tag < 1 + || tag >= NUM_KNOWN_OBJ_ATTRIBUTES + || !attributes_set_explicitly[tag]) + bfd_elf_add_proc_attr_int (stdoutput, tag, value); +} + +static void +arc_set_attribute_string (int tag, const char *value) +{ + if (tag < 1 + || tag >= NUM_KNOWN_OBJ_ATTRIBUTES + || !attributes_set_explicitly[tag]) + bfd_elf_add_proc_attr_string (stdoutput, tag, value); +} + +/* Allocate and concatenate two strings. s1 can be NULL but not + s2. s1 pointer is freed at end of this procedure. */ + +static char * +arc_stralloc (char * s1, const char * s2) +{ + char * p; + int len = 0; + + if (s1) + len = strlen (s1) + 1; + + /* Only s1 can be null. */ + gas_assert (s2); + len += strlen (s2) + 1; + + p = (char *) xmalloc (len); + if (p == NULL) + as_fatal (_("Virtual memory exhausted")); + + if (s1) + { + strcpy (p, s1); + strcat (p, ","); + strcat (p, s2); + free (s1); + } + else + strcpy (p, s2); + + return p; +} + +/* Set the public ARC object attributes. */ + +static void +arc_set_public_attributes (void) +{ + int base = 0; + char *s = NULL; + unsigned int i; + + /* Tag_ARC_CPU_name. */ + arc_set_attribute_string (Tag_ARC_CPU_name, selected_cpu.name); + + /* Tag_ARC_CPU_base. */ + switch (selected_cpu.eflags & EF_ARC_MACH_MSK) + { + case E_ARC_MACH_ARC600: + case E_ARC_MACH_ARC601: + base = TAG_CPU_ARC6xx; + break; + case E_ARC_MACH_ARC700: + base = TAG_CPU_ARC7xx; + break; + case EF_ARC_CPU_ARCV2EM: + base = TAG_CPU_ARCEM; + break; + case EF_ARC_CPU_ARCV2HS: + base = TAG_CPU_ARCHS; + break; + default: + base = 0; + break; + } + if (attributes_set_explicitly[Tag_ARC_CPU_base] + && (base != bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_PROC, + Tag_ARC_CPU_base))) + as_warn (_("Overwrite explicitly set Tag_ARC_CPU_base")); + bfd_elf_add_proc_attr_int (stdoutput, Tag_ARC_CPU_base, base); + + /* Tag_ARC_ABI_osver. */ + if (attributes_set_explicitly[Tag_ARC_ABI_osver]) + { + int val = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_PROC, + Tag_ARC_ABI_osver); + + selected_cpu.eflags = ((selected_cpu.eflags & ~EF_ARC_OSABI_MSK) + | (val & 0x0f << 8)); + } + else + { + arc_set_attribute_int (Tag_ARC_ABI_osver, E_ARC_OSABI_CURRENT >> 8); + } + + /* Tag_ARC_ISA_config. */ + arc_check_feature(); + + for (i = 0; i < ARRAY_SIZE (feature_list); i++) + if (selected_cpu.features & feature_list[i].feature) + s = arc_stralloc (s, feature_list[i].attr); + + if (s) + arc_set_attribute_string (Tag_ARC_ISA_config, s); + + /* Tag_ARC_ISA_mpy_option. */ + arc_set_attribute_int (Tag_ARC_ISA_mpy_option, mpy_option); + + /* Tag_ARC_ABI_pic. */ + arc_set_attribute_int (Tag_ARC_ABI_pic, pic_option); + + /* Tag_ARC_ABI_sda. */ + arc_set_attribute_int (Tag_ARC_ABI_sda, sda_option); + + /* Tag_ARC_ABI_tls. */ + arc_set_attribute_int (Tag_ARC_ABI_tls, tls_option); + + /* Tag_ARC_ATR_version. */ + arc_set_attribute_int (Tag_ARC_ATR_version, 1); + + /* Tag_ARC_ABI_rf16. */ + if (attributes_set_explicitly[Tag_ARC_ABI_rf16] + && bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_PROC, + Tag_ARC_ABI_rf16) + && !rf16_only) + { + as_warn (_("Overwrite explicitly set Tag_ARC_ABI_rf16 to full " + "register file")); + bfd_elf_add_proc_attr_int (stdoutput, Tag_ARC_ABI_rf16, 0); + } +} + +/* Add the default contents for the .ARC.attributes section. */ + +void +arc_md_end (void) +{ + arc_set_public_attributes (); + + if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, selected_cpu.mach)) + as_fatal (_("could not set architecture and machine")); + + bfd_set_private_flags (stdoutput, selected_cpu.eflags); +} + +void arc_copy_symbol_attributes (symbolS *dest, symbolS *src) +{ + ARC_GET_FLAG (dest) = ARC_GET_FLAG (src); +} + +int arc_convert_symbolic_attribute (const char *name) +{ + static const struct + { + const char * name; + const int tag; + } + attribute_table[] = + { +#define T(tag) {#tag, tag} + T (Tag_ARC_PCS_config), + T (Tag_ARC_CPU_base), + T (Tag_ARC_CPU_variation), + T (Tag_ARC_CPU_name), + T (Tag_ARC_ABI_rf16), + T (Tag_ARC_ABI_osver), + T (Tag_ARC_ABI_sda), + T (Tag_ARC_ABI_pic), + T (Tag_ARC_ABI_tls), + T (Tag_ARC_ABI_enumsize), + T (Tag_ARC_ABI_exceptions), + T (Tag_ARC_ABI_double_size), + T (Tag_ARC_ISA_config), + T (Tag_ARC_ISA_apex), + T (Tag_ARC_ISA_mpy_option), + T (Tag_ARC_ATR_version) +#undef T + }; + unsigned int i; + + if (name == NULL) + return -1; + + for (i = 0; i < ARRAY_SIZE (attribute_table); i++) + if (streq (name, attribute_table[i].name)) + return attribute_table[i].tag; + + return -1; +} + /* Local variables: eval: (c-set-style "gnu") indent-tabs-mode: t