X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=gas%2Fconfig%2Ftc-i386.c;h=aff7f9b8f7c0e2c22a74fcc90c687afc299ab530;hb=48521003d5300e1390d78dbbcae83febe5808aaf;hp=d7102163b778c980b5fef3d6b9701989aab3e32f;hpb=80b8656cbaaf09b685c2f3c9dd96f61274ed7fb7;p=deliverable%2Fbinutils-gdb.git diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index d7102163b7..aff7f9b8f7 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -1,5 +1,5 @@ /* tc-i386.c -- Assemble code for the Intel 80386 - Copyright (C) 1989-2015 Free Software Foundation, Inc. + Copyright (C) 1989-2017 Free Software Foundation, Inc. This file is part of GAS, the GNU Assembler. @@ -33,11 +33,6 @@ #include "elf/x86-64.h" #include "opcodes/i386-init.h" -#ifdef TE_LINUX -/* Default to compress debug sections for Linux. */ -int flag_compress_debug = 1; -#endif - #ifndef REGISTER_WARNINGS #define REGISTER_WARNINGS 1 #endif @@ -138,10 +133,18 @@ typedef struct enum processor_type type; /* arch type */ i386_cpu_flags flags; /* cpu feature flags */ unsigned int skip; /* show_arch should skip this. */ - unsigned int negated; /* turn off indicated flags. */ } arch_entry; +/* Used to turn off indicated flags. */ +typedef struct +{ + const char *name; /* arch name */ + unsigned int len; /* arch string length */ + i386_cpu_flags flags; /* cpu feature flags */ +} +noarch_entry; + static void update_code_flag (int, int); static void set_code_flag (int); static void set_16bit_gcc_code_flag (int); @@ -170,7 +173,7 @@ static void swap_operands (void); static void swap_2_operands (int, int); static void optimize_imm (void); static void optimize_disp (void); -static const insn_template *match_template (void); +static const insn_template *match_template (char); static int check_string (void); static int process_suffix (void); static int check_byte_reg (void); @@ -323,6 +326,9 @@ struct _i386_insn explicit segment overrides are given. */ const seg_entry *seg[2]; + /* Copied first memory operand string, for re-checking. */ + char *memop1_string; + /* PREFIX holds all the given prefix opcodes (usually null). PREFIXES is the number of prefix opcodes. */ unsigned int prefixes; @@ -348,8 +354,13 @@ struct _i386_insn /* Compressed disp8*N attribute. */ unsigned int memshift; - /* Swap operand in encoding. */ - unsigned int swap_operand; + /* Prefer load or store in encoding. */ + enum + { + dir_encoding_default = 0, + dir_encoding_load, + dir_encoding_store + } dir_encoding; /* Prefer 8bit or 32bit displacement in encoding. */ enum @@ -359,6 +370,15 @@ struct _i386_insn disp_encoding_32bit } disp_encoding; + /* How to encode vector instructions. */ + enum + { + vex_encoding_default = 0, + vex_encoding_vex2, + vex_encoding_vex3, + vex_encoding_evex + } vec_encoding; + /* REP prefix. */ const char *rep_prefix; @@ -368,8 +388,8 @@ struct _i386_insn /* Have BND prefix. */ const char *bnd_prefix; - /* Need VREX to support upper 16 registers. */ - int need_vrex; + /* Have NOTRACK prefix. */ + const char *notrack_prefix; /* Error message. */ enum i386_error error; @@ -397,7 +417,7 @@ static const struct RC_name RC_NamesTable[] = /* List of chars besides those in app.c:symbol_chars that can start an operand. Used to prevent the scrubber eating vital white-space. */ -const char extra_symbol_chars[] = "*%-([{" +const char extra_symbol_chars[] = "*%-([{}" #ifdef LEX_AT "@" #endif @@ -523,10 +543,19 @@ static enum x86_elf_abi x86_elf_abi = I386_ABI; static int use_big_obj = 0; #endif +#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) +/* 1 if generating code for a shared library. */ +static int shared = 0; +#endif + /* 1 for intel syntax, 0 if att syntax. */ static int intel_syntax = 0; +/* 1 for Intel64 ISA, + 0 if AMD64 ISA. */ +static int intel64; + /* 1 for intel mnemonic, 0 if att mnemonic. */ static int intel_mnemonic = !SYSV386_COMPAT; @@ -540,7 +569,7 @@ static int allow_pseudo_reg = 0; /* 1 if register prefix % not required. */ static int allow_naked_reg = 0; -/* 1 if the assembler should add BND prefix for all control-tranferring +/* 1 if the assembler should add BND prefix for all control-transferring instructions supporting it, even if this prefix wasn't specified explicitly. */ static int add_bnd_prefix = 0; @@ -552,6 +581,15 @@ static int allow_index_reg = 0; specified explicitly. */ static int omit_lock_prefix = 0; +/* 1 if the assembler should encode lfence, mfence, and sfence as + "lock addl $0, (%{re}sp)". */ +static int avoid_fence = 0; + +/* 1 if the assembler should generate relax relocations. */ + +static int generate_relax_relocations + = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS; + static enum check_kind { check_none = 0, @@ -721,231 +759,276 @@ static const arch_entry cpu_arch[] = /* Do not replace the first two entries - i386_target_format() relies on them being there in this order. */ { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32, - CPU_GENERIC32_FLAGS, 0, 0 }, + CPU_GENERIC32_FLAGS, 0 }, { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64, - CPU_GENERIC64_FLAGS, 0, 0 }, + CPU_GENERIC64_FLAGS, 0 }, { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN, - CPU_NONE_FLAGS, 0, 0 }, + CPU_NONE_FLAGS, 0 }, { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN, - CPU_I186_FLAGS, 0, 0 }, + CPU_I186_FLAGS, 0 }, { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN, - CPU_I286_FLAGS, 0, 0 }, + CPU_I286_FLAGS, 0 }, { STRING_COMMA_LEN ("i386"), PROCESSOR_I386, - CPU_I386_FLAGS, 0, 0 }, + CPU_I386_FLAGS, 0 }, { STRING_COMMA_LEN ("i486"), PROCESSOR_I486, - CPU_I486_FLAGS, 0, 0 }, + CPU_I486_FLAGS, 0 }, { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM, - CPU_I586_FLAGS, 0, 0 }, + CPU_I586_FLAGS, 0 }, { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO, - CPU_I686_FLAGS, 0, 0 }, + CPU_I686_FLAGS, 0 }, { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM, - CPU_I586_FLAGS, 0, 0 }, + CPU_I586_FLAGS, 0 }, { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO, - CPU_PENTIUMPRO_FLAGS, 0, 0 }, + CPU_PENTIUMPRO_FLAGS, 0 }, { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO, - CPU_P2_FLAGS, 0, 0 }, + CPU_P2_FLAGS, 0 }, { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO, - CPU_P3_FLAGS, 0, 0 }, + CPU_P3_FLAGS, 0 }, { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4, - CPU_P4_FLAGS, 0, 0 }, + CPU_P4_FLAGS, 0 }, { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA, - CPU_CORE_FLAGS, 0, 0 }, + CPU_CORE_FLAGS, 0 }, { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA, - CPU_NOCONA_FLAGS, 0, 0 }, + CPU_NOCONA_FLAGS, 0 }, { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE, - CPU_CORE_FLAGS, 1, 0 }, + CPU_CORE_FLAGS, 1 }, { STRING_COMMA_LEN ("core"), PROCESSOR_CORE, - CPU_CORE_FLAGS, 0, 0 }, + CPU_CORE_FLAGS, 0 }, { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2, - CPU_CORE2_FLAGS, 1, 0 }, + CPU_CORE2_FLAGS, 1 }, { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2, - CPU_CORE2_FLAGS, 0, 0 }, + CPU_CORE2_FLAGS, 0 }, { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7, - CPU_COREI7_FLAGS, 0, 0 }, + CPU_COREI7_FLAGS, 0 }, { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM, - CPU_L1OM_FLAGS, 0, 0 }, + CPU_L1OM_FLAGS, 0 }, { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM, - CPU_K1OM_FLAGS, 0, 0 }, + CPU_K1OM_FLAGS, 0 }, + { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU, + CPU_IAMCU_FLAGS, 0 }, { STRING_COMMA_LEN ("k6"), PROCESSOR_K6, - CPU_K6_FLAGS, 0, 0 }, + CPU_K6_FLAGS, 0 }, { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6, - CPU_K6_2_FLAGS, 0, 0 }, + CPU_K6_2_FLAGS, 0 }, { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON, - CPU_ATHLON_FLAGS, 0, 0 }, + CPU_ATHLON_FLAGS, 0 }, { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8, - CPU_K8_FLAGS, 1, 0 }, + CPU_K8_FLAGS, 1 }, { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8, - CPU_K8_FLAGS, 0, 0 }, + CPU_K8_FLAGS, 0 }, { STRING_COMMA_LEN ("k8"), PROCESSOR_K8, - CPU_K8_FLAGS, 0, 0 }, + CPU_K8_FLAGS, 0 }, { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10, - CPU_AMDFAM10_FLAGS, 0, 0 }, + CPU_AMDFAM10_FLAGS, 0 }, { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD, - CPU_BDVER1_FLAGS, 0, 0 }, + CPU_BDVER1_FLAGS, 0 }, { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD, - CPU_BDVER2_FLAGS, 0, 0 }, + CPU_BDVER2_FLAGS, 0 }, { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD, - CPU_BDVER3_FLAGS, 0, 0 }, + CPU_BDVER3_FLAGS, 0 }, { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD, - CPU_BDVER4_FLAGS, 0, 0 }, + CPU_BDVER4_FLAGS, 0 }, { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER, - CPU_ZNVER1_FLAGS, 0, 0 }, + CPU_ZNVER1_FLAGS, 0 }, { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT, - CPU_BTVER1_FLAGS, 0, 0 }, + CPU_BTVER1_FLAGS, 0 }, { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT, - CPU_BTVER2_FLAGS, 0, 0 }, + CPU_BTVER2_FLAGS, 0 }, { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN, - CPU_8087_FLAGS, 0, 0 }, + CPU_8087_FLAGS, 0 }, { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN, - CPU_287_FLAGS, 0, 0 }, + CPU_287_FLAGS, 0 }, { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN, - CPU_387_FLAGS, 0, 0 }, - { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN, - CPU_ANY87_FLAGS, 0, 1 }, + CPU_387_FLAGS, 0 }, + { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN, + CPU_687_FLAGS, 0 }, { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN, - CPU_MMX_FLAGS, 0, 0 }, - { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN, - CPU_3DNOWA_FLAGS, 0, 1 }, + CPU_MMX_FLAGS, 0 }, { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN, - CPU_SSE_FLAGS, 0, 0 }, + CPU_SSE_FLAGS, 0 }, { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN, - CPU_SSE2_FLAGS, 0, 0 }, + CPU_SSE2_FLAGS, 0 }, { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN, - CPU_SSE3_FLAGS, 0, 0 }, + CPU_SSE3_FLAGS, 0 }, { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN, - CPU_SSSE3_FLAGS, 0, 0 }, + CPU_SSSE3_FLAGS, 0 }, { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN, - CPU_SSE4_1_FLAGS, 0, 0 }, + CPU_SSE4_1_FLAGS, 0 }, { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN, - CPU_SSE4_2_FLAGS, 0, 0 }, + CPU_SSE4_2_FLAGS, 0 }, { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN, - CPU_SSE4_2_FLAGS, 0, 0 }, - { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN, - CPU_ANY_SSE_FLAGS, 0, 1 }, + CPU_SSE4_2_FLAGS, 0 }, { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN, - CPU_AVX_FLAGS, 0, 0 }, + CPU_AVX_FLAGS, 0 }, { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN, - CPU_AVX2_FLAGS, 0, 0 }, + CPU_AVX2_FLAGS, 0 }, { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN, - CPU_AVX512F_FLAGS, 0, 0 }, + CPU_AVX512F_FLAGS, 0 }, { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN, - CPU_AVX512CD_FLAGS, 0, 0 }, + CPU_AVX512CD_FLAGS, 0 }, { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN, - CPU_AVX512ER_FLAGS, 0, 0 }, + CPU_AVX512ER_FLAGS, 0 }, { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN, - CPU_AVX512PF_FLAGS, 0, 0 }, + CPU_AVX512PF_FLAGS, 0 }, { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN, - CPU_AVX512DQ_FLAGS, 0, 0 }, + CPU_AVX512DQ_FLAGS, 0 }, { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN, - CPU_AVX512BW_FLAGS, 0, 0 }, + CPU_AVX512BW_FLAGS, 0 }, { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN, - CPU_AVX512VL_FLAGS, 0, 0 }, - { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN, - CPU_ANY_AVX_FLAGS, 0, 1 }, + CPU_AVX512VL_FLAGS, 0 }, { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN, - CPU_VMX_FLAGS, 0, 0 }, + CPU_VMX_FLAGS, 0 }, { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN, - CPU_VMFUNC_FLAGS, 0, 0 }, + CPU_VMFUNC_FLAGS, 0 }, { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN, - CPU_SMX_FLAGS, 0, 0 }, + CPU_SMX_FLAGS, 0 }, { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN, - CPU_XSAVE_FLAGS, 0, 0 }, + CPU_XSAVE_FLAGS, 0 }, { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN, - CPU_XSAVEOPT_FLAGS, 0, 0 }, + CPU_XSAVEOPT_FLAGS, 0 }, { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN, - CPU_XSAVEC_FLAGS, 0, 0 }, + CPU_XSAVEC_FLAGS, 0 }, { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN, - CPU_XSAVES_FLAGS, 0, 0 }, + CPU_XSAVES_FLAGS, 0 }, { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN, - CPU_AES_FLAGS, 0, 0 }, + CPU_AES_FLAGS, 0 }, { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN, - CPU_PCLMUL_FLAGS, 0, 0 }, + CPU_PCLMUL_FLAGS, 0 }, { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN, - CPU_PCLMUL_FLAGS, 1, 0 }, + CPU_PCLMUL_FLAGS, 1 }, { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN, - CPU_FSGSBASE_FLAGS, 0, 0 }, + CPU_FSGSBASE_FLAGS, 0 }, { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN, - CPU_RDRND_FLAGS, 0, 0 }, + CPU_RDRND_FLAGS, 0 }, { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN, - CPU_F16C_FLAGS, 0, 0 }, + CPU_F16C_FLAGS, 0 }, { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN, - CPU_BMI2_FLAGS, 0, 0 }, + CPU_BMI2_FLAGS, 0 }, { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN, - CPU_FMA_FLAGS, 0, 0 }, + CPU_FMA_FLAGS, 0 }, { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN, - CPU_FMA4_FLAGS, 0, 0 }, + CPU_FMA4_FLAGS, 0 }, { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN, - CPU_XOP_FLAGS, 0, 0 }, + CPU_XOP_FLAGS, 0 }, { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN, - CPU_LWP_FLAGS, 0, 0 }, + CPU_LWP_FLAGS, 0 }, { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN, - CPU_MOVBE_FLAGS, 0, 0 }, + CPU_MOVBE_FLAGS, 0 }, { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN, - CPU_CX16_FLAGS, 0, 0 }, + CPU_CX16_FLAGS, 0 }, { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN, - CPU_EPT_FLAGS, 0, 0 }, + CPU_EPT_FLAGS, 0 }, { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN, - CPU_LZCNT_FLAGS, 0, 0 }, + CPU_LZCNT_FLAGS, 0 }, { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN, - CPU_HLE_FLAGS, 0, 0 }, + CPU_HLE_FLAGS, 0 }, { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN, - CPU_RTM_FLAGS, 0, 0 }, + CPU_RTM_FLAGS, 0 }, { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN, - CPU_INVPCID_FLAGS, 0, 0 }, + CPU_INVPCID_FLAGS, 0 }, { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN, - CPU_CLFLUSH_FLAGS, 0, 0 }, + CPU_CLFLUSH_FLAGS, 0 }, { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN, - CPU_NOP_FLAGS, 0, 0 }, + CPU_NOP_FLAGS, 0 }, { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN, - CPU_SYSCALL_FLAGS, 0, 0 }, + CPU_SYSCALL_FLAGS, 0 }, { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN, - CPU_RDTSCP_FLAGS, 0, 0 }, + CPU_RDTSCP_FLAGS, 0 }, { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN, - CPU_3DNOW_FLAGS, 0, 0 }, + CPU_3DNOW_FLAGS, 0 }, { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN, - CPU_3DNOWA_FLAGS, 0, 0 }, + CPU_3DNOWA_FLAGS, 0 }, { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN, - CPU_PADLOCK_FLAGS, 0, 0 }, + CPU_PADLOCK_FLAGS, 0 }, { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN, - CPU_SVME_FLAGS, 1, 0 }, + CPU_SVME_FLAGS, 1 }, { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN, - CPU_SVME_FLAGS, 0, 0 }, + CPU_SVME_FLAGS, 0 }, { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN, - CPU_SSE4A_FLAGS, 0, 0 }, + CPU_SSE4A_FLAGS, 0 }, { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN, - CPU_ABM_FLAGS, 0, 0 }, + CPU_ABM_FLAGS, 0 }, { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN, - CPU_BMI_FLAGS, 0, 0 }, + CPU_BMI_FLAGS, 0 }, { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN, - CPU_TBM_FLAGS, 0, 0 }, + CPU_TBM_FLAGS, 0 }, { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN, - CPU_ADX_FLAGS, 0, 0 }, + CPU_ADX_FLAGS, 0 }, { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN, - CPU_RDSEED_FLAGS, 0, 0 }, + CPU_RDSEED_FLAGS, 0 }, { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN, - CPU_PRFCHW_FLAGS, 0, 0 }, + CPU_PRFCHW_FLAGS, 0 }, { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN, - CPU_SMAP_FLAGS, 0, 0 }, + CPU_SMAP_FLAGS, 0 }, { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN, - CPU_MPX_FLAGS, 0, 0 }, + CPU_MPX_FLAGS, 0 }, { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN, - CPU_SHA_FLAGS, 0, 0 }, + CPU_SHA_FLAGS, 0 }, { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN, - CPU_CLFLUSHOPT_FLAGS, 0, 0 }, + CPU_CLFLUSHOPT_FLAGS, 0 }, { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN, - CPU_PREFETCHWT1_FLAGS, 0, 0 }, + CPU_PREFETCHWT1_FLAGS, 0 }, { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN, - CPU_SE1_FLAGS, 0, 0 }, + CPU_SE1_FLAGS, 0 }, { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN, - CPU_CLWB_FLAGS, 0, 0 }, - { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN, - CPU_PCOMMIT_FLAGS, 0, 0 }, + CPU_CLWB_FLAGS, 0 }, { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN, - CPU_AVX512IFMA_FLAGS, 0, 0 }, + CPU_AVX512IFMA_FLAGS, 0 }, { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN, - CPU_AVX512VBMI_FLAGS, 0, 0 }, + CPU_AVX512VBMI_FLAGS, 0 }, + { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN, + CPU_AVX512_4FMAPS_FLAGS, 0 }, + { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN, + CPU_AVX512_4VNNIW_FLAGS, 0 }, + { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN, + CPU_AVX512_VPOPCNTDQ_FLAGS, 0 }, + { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN, + CPU_AVX512_VBMI2_FLAGS, 0 }, { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN, - CPU_CLZERO_FLAGS, 0, 0 }, + CPU_CLZERO_FLAGS, 0 }, + { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN, + CPU_MWAITX_FLAGS, 0 }, + { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN, + CPU_OSPKE_FLAGS, 0 }, + { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN, + CPU_RDPID_FLAGS, 0 }, + { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN, + CPU_PTWRITE_FLAGS, 0 }, + { STRING_COMMA_LEN (".cet"), PROCESSOR_UNKNOWN, + CPU_CET_FLAGS, 0 }, + { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN, + CPU_GFNI_FLAGS, 0 }, +}; + +static const noarch_entry cpu_noarch[] = +{ + { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS }, + { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS }, + { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS }, + { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS }, + { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS }, + { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS }, + { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS }, + { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS }, + { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS }, + { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS }, + { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS }, + { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS }, + { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS }, + { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS }, + { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS }, + { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS }, + { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS }, + { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS }, + { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS }, + { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS }, + { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS }, + { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS }, + { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS }, + { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS }, + { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS }, + { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS }, + { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS }, }; #ifdef I386COFF @@ -1050,95 +1133,95 @@ i386_align_code (fragS *fragP, int count) /* Various efficient no-op patterns for aligning code labels. Note: Don't try to assemble the instructions in the comments. 0L and 0w are not legal. */ - static const char f32_1[] = + static const unsigned char f32_1[] = {0x90}; /* nop */ - static const char f32_2[] = + static const unsigned char f32_2[] = {0x66,0x90}; /* xchg %ax,%ax */ - static const char f32_3[] = + static const unsigned char f32_3[] = {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ - static const char f32_4[] = + static const unsigned char f32_4[] = {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ - static const char f32_5[] = + static const unsigned char f32_5[] = {0x90, /* nop */ 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ - static const char f32_6[] = + static const unsigned char f32_6[] = {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ - static const char f32_7[] = + static const unsigned char f32_7[] = {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ - static const char f32_8[] = + static const unsigned char f32_8[] = {0x90, /* nop */ 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ - static const char f32_9[] = + static const unsigned char f32_9[] = {0x89,0xf6, /* movl %esi,%esi */ 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ - static const char f32_10[] = + static const unsigned char f32_10[] = {0x8d,0x76,0x00, /* leal 0(%esi),%esi */ 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ - static const char f32_11[] = + static const unsigned char f32_11[] = {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */ 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ - static const char f32_12[] = + static const unsigned char f32_12[] = {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */ - static const char f32_13[] = + static const unsigned char f32_13[] = {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ - static const char f32_14[] = + static const unsigned char f32_14[] = {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */ 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ - static const char f16_3[] = + static const unsigned char f16_3[] = {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */ - static const char f16_4[] = + static const unsigned char f16_4[] = {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ - static const char f16_5[] = + static const unsigned char f16_5[] = {0x90, /* nop */ 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ - static const char f16_6[] = + static const unsigned char f16_6[] = {0x89,0xf6, /* mov %si,%si */ 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ - static const char f16_7[] = + static const unsigned char f16_7[] = {0x8d,0x74,0x00, /* lea 0(%si),%si */ 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ - static const char f16_8[] = + static const unsigned char f16_8[] = {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */ 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ - static const char jump_31[] = + static const unsigned char jump_31[] = {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */ 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90, 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90, 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90}; - static const char *const f32_patt[] = { + static const unsigned char *const f32_patt[] = { f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8, f32_9, f32_10, f32_11, f32_12, f32_13, f32_14 }; - static const char *const f16_patt[] = { + static const unsigned char *const f16_patt[] = { f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8 }; /* nopl (%[re]ax) */ - static const char alt_3[] = + static const unsigned char alt_3[] = {0x0f,0x1f,0x00}; /* nopl 0(%[re]ax) */ - static const char alt_4[] = + static const unsigned char alt_4[] = {0x0f,0x1f,0x40,0x00}; /* nopl 0(%[re]ax,%[re]ax,1) */ - static const char alt_5[] = + static const unsigned char alt_5[] = {0x0f,0x1f,0x44,0x00,0x00}; /* nopw 0(%[re]ax,%[re]ax,1) */ - static const char alt_6[] = + static const unsigned char alt_6[] = {0x66,0x0f,0x1f,0x44,0x00,0x00}; /* nopl 0L(%[re]ax) */ - static const char alt_7[] = + static const unsigned char alt_7[] = {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; /* nopl 0L(%[re]ax,%[re]ax,1) */ - static const char alt_8[] = + static const unsigned char alt_8[] = {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; /* nopw 0L(%[re]ax,%[re]ax,1) */ - static const char alt_9[] = + static const unsigned char alt_9[] = {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; /* nopw %cs:0L(%[re]ax,%[re]ax,1) */ - static const char alt_10[] = + static const unsigned char alt_10[] = {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; - static const char *const alt_patt[] = { + static const unsigned char *const alt_patt[] = { f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, alt_9, alt_10 }; @@ -1176,7 +1259,7 @@ i386_align_code (fragS *fragP, int count) } else { - const char *const *patt = NULL; + const unsigned char *const *patt = NULL; if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN) { @@ -1212,6 +1295,7 @@ i386_align_code (fragS *fragP, int count) case PROCESSOR_I486: case PROCESSOR_PENTIUM: case PROCESSOR_PENTIUMPRO: + case PROCESSOR_IAMCU: case PROCESSOR_GENERIC32: patt = f32_patt; break; @@ -1230,6 +1314,7 @@ i386_align_code (fragS *fragP, int count) case PROCESSOR_I386: case PROCESSOR_I486: case PROCESSOR_PENTIUM: + case PROCESSOR_IAMCU: case PROCESSOR_K6: case PROCESSOR_ATHLON: case PROCESSOR_K8: @@ -1317,9 +1402,11 @@ operand_type_all_zero (const union i386_operand_type *x) case 3: if (x->array[2]) return 0; + /* Fall through. */ case 2: if (x->array[1]) return 0; + /* Fall through. */ case 1: return !x->array[0]; default: @@ -1334,10 +1421,13 @@ operand_type_set (union i386_operand_type *x, unsigned int v) { case 3: x->array[2] = v; + /* Fall through. */ case 2: x->array[1] = v; + /* Fall through. */ case 1: x->array[0] = v; + /* Fall through. */ break; default: abort (); @@ -1353,9 +1443,11 @@ operand_type_equal (const union i386_operand_type *x, case 3: if (x->array[2] != y->array[2]) return 0; + /* Fall through. */ case 2: if (x->array[1] != y->array[1]) return 0; + /* Fall through. */ case 1: return x->array[0] == y->array[0]; break; @@ -1369,12 +1461,18 @@ cpu_flags_all_zero (const union i386_cpu_flags *x) { switch (ARRAY_SIZE(x->array)) { + case 4: + if (x->array[3]) + return 0; + /* Fall through. */ case 3: if (x->array[2]) return 0; + /* Fall through. */ case 2: if (x->array[1]) return 0; + /* Fall through. */ case 1: return !x->array[0]; default: @@ -1382,35 +1480,24 @@ cpu_flags_all_zero (const union i386_cpu_flags *x) } } -static INLINE void -cpu_flags_set (union i386_cpu_flags *x, unsigned int v) -{ - switch (ARRAY_SIZE(x->array)) - { - case 3: - x->array[2] = v; - case 2: - x->array[1] = v; - case 1: - x->array[0] = v; - break; - default: - abort (); - } -} - static INLINE int cpu_flags_equal (const union i386_cpu_flags *x, const union i386_cpu_flags *y) { switch (ARRAY_SIZE(x->array)) { + case 4: + if (x->array[3] != y->array[3]) + return 0; + /* Fall through. */ case 3: if (x->array[2] != y->array[2]) return 0; + /* Fall through. */ case 2: if (x->array[1] != y->array[1]) return 0; + /* Fall through. */ case 1: return x->array[0] == y->array[0]; break; @@ -1431,10 +1518,15 @@ cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y) { switch (ARRAY_SIZE (x.array)) { + case 4: + x.array [3] &= y.array [3]; + /* Fall through. */ case 3: x.array [2] &= y.array [2]; + /* Fall through. */ case 2: x.array [1] &= y.array [1]; + /* Fall through. */ case 1: x.array [0] &= y.array [0]; break; @@ -1449,10 +1541,15 @@ cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y) { switch (ARRAY_SIZE (x.array)) { + case 4: + x.array [3] |= y.array [3]; + /* Fall through. */ case 3: x.array [2] |= y.array [2]; + /* Fall through. */ case 2: x.array [1] |= y.array [1]; + /* Fall through. */ case 1: x.array [0] |= y.array [0]; break; @@ -1467,10 +1564,15 @@ cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y) { switch (ARRAY_SIZE (x.array)) { + case 4: + x.array [3] &= ~y.array [3]; + /* Fall through. */ case 3: x.array [2] &= ~y.array [2]; + /* Fall through. */ case 2: x.array [1] &= ~y.array [1]; + /* Fall through. */ case 1: x.array [0] &= ~y.array [0]; break; @@ -1513,8 +1615,6 @@ cpu_flags_match (const insn_template *t) /* This instruction is available only on some archs. */ i386_cpu_flags cpu = cpu_arch_flags; - cpu.bitfield.cpu64 = 0; - cpu.bitfield.cpuno64 = 0; cpu = cpu_flags_and (x, cpu); if (!cpu_flags_all_zero (&cpu)) { @@ -1540,6 +1640,21 @@ cpu_flags_match (const insn_template *t) else match |= CPU_FLAGS_ARCH_MATCH; } + else if (x.bitfield.cpuavx512vl) + { + /* Match AVX512VL. */ + if (cpu.bitfield.cpuavx512vl) + { + /* Need another match. */ + cpu.bitfield.cpuavx512vl = 0; + if (!cpu_flags_all_zero (&cpu)) + match |= CPU_FLAGS_32BIT_MATCH; + else + match |= CPU_FLAGS_ARCH_MATCH; + } + else + match |= CPU_FLAGS_ARCH_MATCH; + } else match |= CPU_FLAGS_32BIT_MATCH; } @@ -1554,8 +1669,10 @@ operand_type_and (i386_operand_type x, i386_operand_type y) { case 3: x.array [2] &= y.array [2]; + /* Fall through. */ case 2: x.array [1] &= y.array [1]; + /* Fall through. */ case 1: x.array [0] &= y.array [0]; break; @@ -1572,8 +1689,10 @@ operand_type_or (i386_operand_type x, i386_operand_type y) { case 3: x.array [2] |= y.array [2]; + /* Fall through. */ case 2: x.array [1] |= y.array [1]; + /* Fall through. */ case 1: x.array [0] |= y.array [0]; break; @@ -1590,8 +1709,10 @@ operand_type_xor (i386_operand_type x, i386_operand_type y) { case 3: x.array [2] ^= y.array [2]; + /* Fall through. */ case 2: x.array [1] ^= y.array [1]; + /* Fall through. */ case 1: x.array [0] ^= y.array [0]; break; @@ -1702,6 +1823,7 @@ match_mem_size (const insn_template *t, unsigned int j) { return (match_reg_size (t, j) && !((i.types[j].bitfield.unspecified + && !i.broadcast && !t->operand_types[j].bitfield.unspecified) || (i.types[j].bitfield.fword && !t->operand_types[j].bitfield.fword) @@ -1865,6 +1987,9 @@ register_number (const reg_entry *r) if (r->reg_flags & RegRex) nr += 8; + if (r->reg_flags & RegVRex) + nr += 16; + return nr; } @@ -2044,6 +2169,7 @@ enum PREFIX_GROUP PREFIX_EXIST = 0, PREFIX_LOCK, PREFIX_REP, + PREFIX_DS, PREFIX_OTHER }; @@ -2052,7 +2178,8 @@ enum PREFIX_GROUP same class already exists. b. PREFIX_LOCK if lock prefix is added. c. PREFIX_REP if rep/repne prefix is added. - d. PREFIX_OTHER if other prefix is added. + d. PREFIX_DS if ds prefix is added. + e. PREFIX_OTHER if other prefix is added. */ static enum PREFIX_GROUP @@ -2077,8 +2204,10 @@ add_prefix (unsigned int prefix) default: abort (); - case CS_PREFIX_OPCODE: case DS_PREFIX_OPCODE: + ret = PREFIX_DS; + /* Fall through. */ + case CS_PREFIX_OPCODE: case ES_PREFIX_OPCODE: case FS_PREFIX_OPCODE: case GS_PREFIX_OPCODE: @@ -2188,8 +2317,8 @@ set_intel_syntax (int syntax_flag) SKIP_WHITESPACE (); if (!is_end_of_line[(unsigned char) *input_line_pointer]) { - char *string = input_line_pointer; - int e = get_symbol_end (); + char *string; + int e = get_symbol_name (&string); if (strcmp (string, "prefix") == 0) ask_naked_reg = 1; @@ -2197,7 +2326,7 @@ set_intel_syntax (int syntax_flag) ask_naked_reg = -1; else as_bad (_("bad argument to syntax directive.")); - *input_line_pointer = e; + (void) restore_line_pointer (e); } demand_empty_rest_of_line (); @@ -2249,8 +2378,8 @@ set_check (int what) if (!is_end_of_line[(unsigned char) *input_line_pointer]) { - char *string = input_line_pointer; - int e = get_symbol_end (); + char *string; + int e = get_symbol_name (&string); if (strcmp (string, "none") == 0) *kind = check_none; @@ -2260,7 +2389,7 @@ set_check (int what) *kind = check_error; else as_bad (_("bad argument to %s_check directive."), str); - *input_line_pointer = e; + (void) restore_line_pointer (e); } else as_bad (_("missing argument for %s_check directive"), str); @@ -2288,6 +2417,11 @@ check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED, arch = default_arch; } + /* If we are targeting Intel MCU, we must enable it. */ + if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU + || new_flag.bitfield.cpuiamcu) + return; + /* If we are targeting Intel L1OM, we must enable it. */ if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM || new_flag.bitfield.cpul1om) @@ -2309,8 +2443,8 @@ set_cpu_arch (int dummy ATTRIBUTE_UNUSED) if (!is_end_of_line[(unsigned char) *input_line_pointer]) { - char *string = input_line_pointer; - int e = get_symbol_end (); + char *string; + int e = get_symbol_name (&string); unsigned int j; i386_cpu_flags flags; @@ -2345,12 +2479,9 @@ set_cpu_arch (int dummy ATTRIBUTE_UNUSED) break; } - if (!cpu_arch[j].negated) - flags = cpu_flags_or (cpu_arch_flags, - cpu_arch[j].flags); - else - flags = cpu_flags_and_not (cpu_arch_flags, - cpu_arch[j].flags); + flags = cpu_flags_or (cpu_arch_flags, + cpu_arch[j].flags); + if (!cpu_flags_equal (&flags, &cpu_arch_flags)) { if (cpu_sub_arch_name) @@ -2366,11 +2497,42 @@ set_cpu_arch (int dummy ATTRIBUTE_UNUSED) cpu_arch_flags = flags; cpu_arch_isa_flags = flags; } - *input_line_pointer = e; + (void) restore_line_pointer (e); demand_empty_rest_of_line (); return; } } + + if (*string == '.' && j >= ARRAY_SIZE (cpu_arch)) + { + /* Disable an ISA extension. */ + for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) + if (strcmp (string + 1, cpu_noarch [j].name) == 0) + { + flags = cpu_flags_and_not (cpu_arch_flags, + cpu_noarch[j].flags); + if (!cpu_flags_equal (&flags, &cpu_arch_flags)) + { + if (cpu_sub_arch_name) + { + char *name = cpu_sub_arch_name; + cpu_sub_arch_name = concat (name, string, + (const char *) NULL); + free (name); + } + else + cpu_sub_arch_name = xstrdup (string); + cpu_arch_flags = flags; + cpu_arch_isa_flags = flags; + } + (void) restore_line_pointer (e); + demand_empty_rest_of_line (); + return; + } + + j = ARRAY_SIZE (cpu_arch); + } + if (j >= ARRAY_SIZE (cpu_arch)) as_bad (_("no such architecture: `%s'"), string); @@ -2383,8 +2545,11 @@ set_cpu_arch (int dummy ATTRIBUTE_UNUSED) if (*input_line_pointer == ',' && !is_end_of_line[(unsigned char) input_line_pointer[1]]) { - char *string = ++input_line_pointer; - int e = get_symbol_end (); + char *string; + char e; + + ++input_line_pointer; + e = get_symbol_name (&string); if (strcmp (string, "nojumps") == 0) no_cond_jump_promotion = 1; @@ -2393,7 +2558,7 @@ set_cpu_arch (int dummy ATTRIBUTE_UNUSED) else as_bad (_("no such architecture modifier: `%s'"), string); - *input_line_pointer = e; + (void) restore_line_pointer (e); } demand_empty_rest_of_line (); @@ -2416,6 +2581,13 @@ i386_arch (void) as_fatal (_("Intel K1OM is 64bit ELF only")); return bfd_arch_k1om; } + else if (cpu_arch_isa == PROCESSOR_IAMCU) + { + if (OUTPUT_FLAVOR != bfd_target_elf_flavour + || flag_code == CODE_64BIT) + as_fatal (_("Intel MCU is 32bit ELF only")); + return bfd_arch_iamcu; + } else return bfd_arch_i386; } @@ -2444,8 +2616,18 @@ i386_mach (void) else return bfd_mach_x64_32; } - else if (!strcmp (default_arch, "i386")) - return bfd_mach_i386_i386; + else if (!strcmp (default_arch, "i386") + || !strcmp (default_arch, "iamcu")) + { + if (cpu_arch_isa == PROCESSOR_IAMCU) + { + if (OUTPUT_FLAVOR != bfd_target_elf_flavour) + as_fatal (_("Intel MCU is 32bit ELF only")); + return bfd_mach_i386_iamcu; + } + else + return bfd_mach_i386_i386; + } else as_fatal (_("unknown architecture")); } @@ -2455,6 +2637,9 @@ md_begin (void) { const char *hash_err; + /* Support pseudo prefixes like {disp32}. */ + lex_type ['{'] = LEX_BEGIN_NAME; + /* Initialize op_hash hash table. */ op_hash = hash_new (); @@ -2464,7 +2649,7 @@ md_begin (void) /* Setup for loop. */ optab = i386_optab; - core_optab = (templates *) xmalloc (sizeof (templates)); + core_optab = XNEW (templates); core_optab->start = optab; while (1) @@ -2487,7 +2672,7 @@ md_begin (void) } if (optab->name == NULL) break; - core_optab = (templates *) xmalloc (sizeof (templates)); + core_optab = XNEW (templates); core_optab->start = optab; } } @@ -2536,7 +2721,10 @@ md_begin (void) operand_chars[c] = c; } else if (c == '{' || c == '}') - operand_chars[c] = c; + { + mnemonic_chars[c] = c; + operand_chars[c] = c; + } if (ISALPHA (c) || ISDIGIT (c)) identifier_chars[c] = c; @@ -2895,6 +3083,7 @@ tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED) || fixP->fx_r_type == BFD_RELOC_386_GOTOFF || fixP->fx_r_type == BFD_RELOC_386_PLT32 || fixP->fx_r_type == BFD_RELOC_386_GOT32 + || fixP->fx_r_type == BFD_RELOC_386_GOT32X || fixP->fx_r_type == BFD_RELOC_386_TLS_GD || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 @@ -2908,6 +3097,8 @@ tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED) || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL + || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX + || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 @@ -2997,12 +3188,13 @@ build_vex_prefix (const insn_template *t) else register_specifier = 0xf; - /* Use 2-byte VEX prefix by swappping destination and source + /* Use 2-byte VEX prefix by swapping destination and source operand. */ - if (!i.swap_operand + if (i.vec_encoding != vex_encoding_vex3 + && i.dir_encoding == dir_encoding_default && i.operands == i.reg_operands && i.tm.opcode_modifier.vexopcode == VEX0F - && i.tm.opcode_modifier.s + && i.tm.opcode_modifier.load && i.rex == REX_B) { unsigned int xchg = i.operands - 1; @@ -3051,7 +3243,8 @@ build_vex_prefix (const insn_template *t) } /* Use 2-byte VEX prefix if possible. */ - if (i.tm.opcode_modifier.vexopcode == VEX0F + if (i.vec_encoding != vex_encoding_vex3 + && i.tm.opcode_modifier.vexopcode == VEX0F && i.tm.opcode_modifier.vexw != VEXW1 && (i.rex & (REX_W | REX_X | REX_B)) == 0) { @@ -3313,6 +3506,34 @@ process_immext (void) i.operands = 0; } + if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0) + { + /* MONITORX/MWAITX instructions have fixed operands with an opcode + suffix which is coded in the same place as an 8-bit immediate + field would be. + Here we check those operands and remove them afterwards. */ + unsigned int x; + + if (i.operands != 3) + abort(); + + for (x = 0; x < 2; x++) + if (register_number (i.op[x].regs) != x) + goto bad_register_operand; + + /* Check for third operand for mwaitx/monitorx insn. */ + if (register_number (i.op[x].regs) + != (x + (i.tm.extension_opcode == 0xfb))) + { +bad_register_operand: + as_bad (_("can't use register '%s%s' as operand %d in '%s'."), + register_prefix, i.op[x].regs->reg_name, x+1, + i.tm.name); + } + + i.operands = 0; + } + /* These AMD 3DNow! and SSE2 instructions have an opcode suffix which is coded in the same place as an 8-bit immediate field would be. Here we fake an 8-bit immediate operand from the @@ -3381,7 +3602,7 @@ void md_assemble (char *line) { unsigned int j; - char mnemonic[MAX_MNEM_SIZE]; + char mnemonic[MAX_MNEM_SIZE], mnem_suffix; const insn_template *t; /* Initialize globals. */ @@ -3399,9 +3620,12 @@ md_assemble (char *line) line = parse_insn (line, mnemonic); if (line == NULL) return; + mnem_suffix = i.suffix; line = parse_operands (line, mnemonic); this_operand = -1; + xfree (i.memop1_string); + i.memop1_string = NULL; if (line == NULL) return; @@ -3442,7 +3666,7 @@ md_assemble (char *line) making sure the overlap of the given operands types is consistent with the template operand types. */ - if (!(t = match_template ())) + if (!(t = match_template (mnem_suffix))) return; if (sse_check != check_none @@ -3507,10 +3731,19 @@ md_assemble (char *line) if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok) as_bad (_("expecting valid branch instruction after `bnd'")); - if (i.tm.cpu_flags.bitfield.cpumpx - && flag_code == CODE_64BIT - && i.prefix[ADDR_PREFIX]) - as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions.")); + /* Check NOTRACK prefix. */ + if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok) + as_bad (_("expecting indirect branch instruction after `notrack'")); + + if (i.tm.cpu_flags.bitfield.cpumpx) + { + if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX]) + as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions.")); + else if (flag_code != CODE_16BIT + ? i.prefix[ADDR_PREFIX] + : i.mem_operands && !i.prefix[ADDR_PREFIX]) + as_bad (_("16-bit address isn't allowed in MPX instructions")); + } /* Insert BND prefix. */ if (add_bnd_prefix @@ -3724,21 +3957,65 @@ parse_insn (char *line, char *mnemonic) current_templates->start->name); return NULL; } - /* Add prefix, checking for repeated prefixes. */ - switch (add_prefix (current_templates->start->base_opcode)) + if (current_templates->start->opcode_length == 0) { - case PREFIX_EXIST: - return NULL; - case PREFIX_REP: - if (current_templates->start->cpu_flags.bitfield.cpuhle) - i.hle_prefix = current_templates->start->name; - else if (current_templates->start->cpu_flags.bitfield.cpumpx) - i.bnd_prefix = current_templates->start->name; - else - i.rep_prefix = current_templates->start->name; - break; - default: - break; + /* Handle pseudo prefixes. */ + switch (current_templates->start->base_opcode) + { + case 0x0: + /* {disp8} */ + i.disp_encoding = disp_encoding_8bit; + break; + case 0x1: + /* {disp32} */ + i.disp_encoding = disp_encoding_32bit; + break; + case 0x2: + /* {load} */ + i.dir_encoding = dir_encoding_load; + break; + case 0x3: + /* {store} */ + i.dir_encoding = dir_encoding_store; + break; + case 0x4: + /* {vex2} */ + i.vec_encoding = vex_encoding_vex2; + break; + case 0x5: + /* {vex3} */ + i.vec_encoding = vex_encoding_vex3; + break; + case 0x6: + /* {evex} */ + i.vec_encoding = vex_encoding_evex; + break; + default: + abort (); + } + } + else + { + /* Add prefix, checking for repeated prefixes. */ + switch (add_prefix (current_templates->start->base_opcode)) + { + case PREFIX_EXIST: + return NULL; + case PREFIX_DS: + if (current_templates->start->cpu_flags.bitfield.cpucet) + i.notrack_prefix = current_templates->start->name; + break; + case PREFIX_REP: + if (current_templates->start->cpu_flags.bitfield.cpuhle) + i.hle_prefix = current_templates->start->name; + else if (current_templates->start->cpu_flags.bitfield.cpumpx) + i.bnd_prefix = current_templates->start->name; + else + i.rep_prefix = current_templates->start->name; + break; + default: + break; + } } /* Skip past PREFIX_SEPARATOR and reset token_start. */ token_start = ++l; @@ -3752,7 +4029,7 @@ parse_insn (char *line, char *mnemonic) /* Check if we should swap operand or force 32bit displacement in encoding. */ if (mnem_p - 2 == dot_p && dot_p[1] == 's') - i.swap_operand = 1; + i.dir_encoding = dir_encoding_store; else if (mnem_p - 3 == dot_p && dot_p[1] == 'd' && dot_p[2] == '8') @@ -3779,6 +4056,7 @@ check_suffix: if (intel_syntax && (intel_float_operand (mnemonic) & 2)) i.suffix = SHORT_MNEM_SUFFIX; else + /* Fall through. */ case BYTE_MNEM_SUFFIX: case QWORD_MNEM_SUFFIX: i.suffix = mnem_p[-1]; @@ -3903,14 +4181,14 @@ parse_operands (char *l, const char *mnemonic) /* Skip optional white space before operand. */ if (is_space_char (*l)) ++l; - if (!is_operand_char (*l) && *l != END_OF_INSN) + if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"') { as_bad (_("invalid character %s before operand %d"), output_invalid (*l), i.operands + 1); return NULL; } - token_start = l; /* after white space */ + token_start = l; /* After white space. */ paren_not_balanced = 0; while (paren_not_balanced || *l != ',') { @@ -3929,7 +4207,7 @@ parse_operands (char *l, const char *mnemonic) else break; /* we are done */ } - else if (!is_operand_char (*l) && !is_space_char (*l)) + else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"') { as_bad (_("invalid character %s in operand %d"), output_invalid (*l), @@ -3956,13 +4234,13 @@ parse_operands (char *l, const char *mnemonic) { /* Yes, we've read in another operand. */ unsigned int operand_ok; this_operand = i.operands++; - i.types[this_operand].bitfield.unspecified = 1; if (i.operands > MAX_OPERANDS) { as_bad (_("spurious operands; (%d operands/instruction max)"), MAX_OPERANDS); return NULL; } + i.types[this_operand].bitfield.unspecified = 1; /* Now parse operand adding info to 'i' as we go along. */ END_STRING_AND_SAVE (l); @@ -4054,6 +4332,7 @@ swap_operands (void) case 5: case 4: swap_2_operands (1, i.operands - 2); + /* Fall through. */ case 3: case 2: swap_2_operands (0, i.operands - 1); @@ -4152,6 +4431,8 @@ optimize_imm (void) i.op[op].imms->X_add_number = (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); } +#ifdef BFD64 + /* Store 32-bit immediate in 64-bit for 64-bit BFD. */ if ((i.types[op].bitfield.imm32) && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) == 0)) @@ -4160,6 +4441,7 @@ optimize_imm (void) ^ ((offsetT) 1 << 31)) - ((offsetT) 1 << 31)); } +#endif i.types[op] = operand_type_or (i.types[op], smallest_imm_type (i.op[op].imms->X_add_number)); @@ -4240,6 +4522,8 @@ optimize_disp (void) op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000); i.types[op].bitfield.disp64 = 0; } +#ifdef BFD64 + /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */ if (i.types[op].bitfield.disp32 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0) { @@ -4250,6 +4534,7 @@ optimize_disp (void) op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); i.types[op].bitfield.disp64 = 0; } +#endif if (!op_disp && i.types[op].bitfield.baseindex) { i.types[op].bitfield.disp8 = 0; @@ -4491,7 +4776,9 @@ check_VecOperands (const insn_template *t) && i.op[op].disps->X_op == O_constant) { offsetT value = i.op[op].disps->X_add_number; - int vec_disp8_ok = fits_in_vec_disp8 (value); + int vec_disp8_ok + = (i.disp_encoding != disp_encoding_32bit + && fits_in_vec_disp8 (value)); if (t->operand_types [op].bitfield.vec_disp8) { if (vec_disp8_ok) @@ -4530,15 +4817,27 @@ check_VecOperands (const insn_template *t) static int VEX_check_operands (const insn_template *t) { - /* VREX is only valid with EVEX prefix. */ - if (i.need_vrex && !t->opcode_modifier.evex) + if (i.vec_encoding == vex_encoding_evex) { - i.error = invalid_register_operand; - return 1; + /* This instruction must be encoded with EVEX prefix. */ + if (!t->opcode_modifier.evex) + { + i.error = unsupported; + return 1; + } + return 0; } if (!t->opcode_modifier.vex) - return 0; + { + /* This instruction template doesn't have VEX prefix. */ + if (i.vec_encoding != vex_encoding_default) + { + i.error = unsupported; + return 1; + } + return 0; + } /* Only check VEX_Imm4, which must be the first operand. */ if (t->operand_types[0].bitfield.vec_imm4) @@ -4558,14 +4857,14 @@ VEX_check_operands (const insn_template *t) } static const insn_template * -match_template (void) +match_template (char mnem_suffix) { /* Points to template once we've found it. */ const insn_template *t; i386_operand_type overlap0, overlap1, overlap2, overlap3; i386_operand_type overlap4; unsigned int found_reverse_match; - i386_opcode_modifier suffix_check; + i386_opcode_modifier suffix_check, mnemsuf_check; i386_operand_type operand_types [MAX_OPERANDS]; int addr_prefix_disp; unsigned int j; @@ -4594,6 +4893,19 @@ match_template (void) else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX) suffix_check.no_ldsuf = 1; + memset (&mnemsuf_check, 0, sizeof (mnemsuf_check)); + if (intel_syntax) + { + switch (mnem_suffix) + { + case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break; + case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break; + case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break; + case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break; + case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break; + } + } + /* Must have right number of operands. */ i.error = number_of_operands_mismatch; @@ -4621,10 +4933,12 @@ match_template (void) if (intel_mnemonic && t->opcode_modifier.attmnemonic) continue; - /* Check AT&T/Intel syntax. */ + /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */ i.error = unsupported_syntax; if ((intel_syntax && t->opcode_modifier.attsyntax) - || (!intel_syntax && t->opcode_modifier.intelsyntax)) + || (!intel_syntax && t->opcode_modifier.intelsyntax) + || (intel64 && t->opcode_modifier.amd64) + || (!intel64 && t->opcode_modifier.intel64)) continue; /* Check the suffix, except for some instructions in intel mode. */ @@ -4637,6 +4951,14 @@ match_template (void) || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf) || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf))) continue; + /* In Intel mode all mnemonic suffixes must be explicitly allowed. */ + if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf) + || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf) + || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf) + || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf) + || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf) + || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf)) + continue; if (!operand_size_match (t)) continue; @@ -4730,6 +5052,10 @@ match_template (void) } } + /* Force 0x8b encoding for "mov foo@GOT, %eax". */ + if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0) + continue; + /* We check register size if needed. */ check_register = t->opcode_modifier.checkregsize; overlap0 = operand_type_and (i.types[0], operand_types[0]); @@ -4740,7 +5066,7 @@ match_template (void) continue; break; case 2: - /* xchg %eax, %eax is a special case. It is an aliase for nop + /* xchg %eax, %eax is a special case. It is an alias for nop only in 32bit mode and we can use opcode 0x90. In 64bit mode, we can't use 0x90 for xchg %eax, %eax since it should zero-extend %eax to %rax. */ @@ -4749,20 +5075,19 @@ match_template (void) && operand_type_equal (&i.types [0], &acc32) && operand_type_equal (&i.types [1], &acc32)) continue; - if (i.swap_operand) - { - /* If we swap operand in encoding, we either match - the next one or reverse direction of operands. */ - if (t->opcode_modifier.s) - continue; - else if (t->opcode_modifier.d) - goto check_reverse; - } + /* If we want store form, we reverse direction of operands. */ + if (i.dir_encoding == dir_encoding_store + && t->opcode_modifier.d) + goto check_reverse; + /* Fall through. */ case 3: - /* If we swap operand in encoding, we match the next one. */ - if (i.swap_operand && t->opcode_modifier.s) + /* If we want store form, we skip the current load. */ + if (i.dir_encoding == dir_encoding_store + && i.mem_operands == 0 + && t->opcode_modifier.load) continue; + /* Fall through. */ case 4: case 5: overlap1 = operand_type_and (i.types[1], operand_types[1]); @@ -4814,9 +5139,11 @@ check_reverse: case 5: overlap4 = operand_type_and (i.types[4], operand_types[4]); + /* Fall through. */ case 4: overlap3 = operand_type_and (i.types[3], operand_types[3]); + /* Fall through. */ case 3: overlap2 = operand_type_and (i.types[2], operand_types[2]); @@ -4834,6 +5161,7 @@ check_reverse: i.types[4], operand_types[4])) continue; + /* Fall through. */ case 4: if (!operand_type_match (overlap3, i.types[3]) || (check_register @@ -4844,6 +5172,7 @@ check_reverse: i.types[3], operand_types[3]))) continue; + /* Fall through. */ case 3: /* Here we make use of the fact that there are no reverse match 3 operand instructions, and all 3 @@ -5186,6 +5515,7 @@ process_suffix (void) i.suffix = QWORD_MNEM_SUFFIX; break; } + /* Fall through. */ case CODE_32BIT: if (!i.tm.opcode_modifier.no_lsuf) i.suffix = LONG_MNEM_SUFFIX; @@ -5471,7 +5801,7 @@ check_qword_reg (void) /* Warn if the r prefix on a general reg is missing. */ else if ((i.types[op].bitfield.reg16 || i.types[op].bitfield.reg32) - && (i.tm.operand_types[op].bitfield.reg32 + && (i.tm.operand_types[op].bitfield.reg64 || i.tm.operand_types[op].bitfield.acc)) { /* Prohibit these changes in the 64bit mode, since the @@ -5752,6 +6082,25 @@ duplicate: i.reg_operands--; i.tm.operands--; } + else if (i.tm.opcode_modifier.implicitquadgroup) + { + /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */ + gas_assert (i.operands >= 2 + && (operand_type_equal (&i.types[1], ®xmm) + || operand_type_equal (&i.types[1], ®ymm) + || operand_type_equal (&i.types[1], ®zmm))); + unsigned int regnum = register_number (i.op[1].regs); + unsigned int first_reg_in_group = regnum & ~3; + unsigned int last_reg_in_group = first_reg_in_group + 3; + if (regnum != first_reg_in_group) { + as_warn (_("the second source register `%s%s' implicitly denotes" + " `%s%.3s%d' to `%s%.3s%d' source group in `%s'"), + register_prefix, i.op[1].regs->reg_name, + register_prefix, i.op[1].regs->reg_name, first_reg_in_group, + register_prefix, i.op[1].regs->reg_name, last_reg_in_group, + i.tm.name); + } + } else if (i.tm.opcode_modifier.regkludge) { /* The imul $imm, %reg instruction is converted into @@ -5967,7 +6316,7 @@ build_modrm_byte (void) if (i.tm.opcode_modifier.immext) { - /* When ImmExt is set, the immdiate byte is the last + /* When ImmExt is set, the immediate byte is the last operand. */ imm_slot = i.operands - 1; source--; @@ -6769,6 +7118,7 @@ output_jump (void) { case 2: *p++ = i.tm.base_opcode >> 8; + /* Fall through. */ case 1: *p++ = i.tm.base_opcode; break; @@ -6880,6 +7230,22 @@ output_insn (void) unsigned int j; unsigned int prefix; + if (avoid_fence + && i.tm.base_opcode == 0xfae + && i.operands == 1 + && i.imm_operands == 1 + && (i.op[0].imms->X_add_number == 0xe8 + || i.op[0].imms->X_add_number == 0xf0 + || i.op[0].imms->X_add_number == 0xf8)) + { + /* Encode lfence, mfence, and sfence as + f0 83 04 24 00 lock addl $0x0, (%{re}sp). */ + offsetT val = 0x240483f0ULL; + p = frag_more (5); + md_number_to_chars (p, val, 5); + return; + } + /* Some processors fail on LOCK prefix. This options makes assembler ignore LOCK prefix and serves as a workaround. */ if (omit_lock_prefix) @@ -7096,6 +7462,7 @@ output_disp (fragS *insn_start_frag, offsetT insn_start_off) int size = disp_size (n); int sign = i.types[n].bitfield.disp32s; int pcrel = (i.flags[n] & Operand_PCrel) != 0; + fixS *fixP; /* We can't have 8 bit displacement here. */ gas_assert (!i.types[n].bitfield.disp8); @@ -7164,8 +7531,39 @@ output_disp (fragS *insn_start_frag, offsetT insn_start_off) insn, and that is taken care of in other code. */ reloc_type = BFD_RELOC_X86_64_GOTPC32; } - fix_new_exp (frag_now, p - frag_now->fr_literal, size, - i.op[n].disps, pcrel, reloc_type); + fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, + size, i.op[n].disps, pcrel, + reloc_type); + /* Check for "call/jmp *mem", "mov mem, %reg", + "test %reg, mem" and "binop mem, %reg" where binop + is one of adc, add, and, cmp, or, sbb, sub, xor + instructions. Always generate R_386_GOT32X for + "sym*GOT" operand in 32-bit mode. */ + if ((generate_relax_relocations + || (!object_64bit + && i.rm.mode == 0 + && i.rm.regmem == 5)) + && (i.rm.mode == 2 + || (i.rm.mode == 0 && i.rm.regmem == 5)) + && ((i.operands == 1 + && i.tm.base_opcode == 0xff + && (i.rm.reg == 2 || i.rm.reg == 4)) + || (i.operands == 2 + && (i.tm.base_opcode == 0x8b + || i.tm.base_opcode == 0x85 + || (i.tm.base_opcode & 0xc7) == 0x03)))) + { + if (object_64bit) + { + fixP->fx_tcbit = i.rex != 0; + if (i.base_reg + && (i.base_reg->reg_num == RegRip + || i.base_reg->reg_num == RegEip)) + fixP->fx_tcbit2 = 1; + } + else + fixP->fx_tcbit2 = 1; + } } } } @@ -7467,7 +7865,7 @@ lex_got (enum bfd_reloc_code_real *rel, /* Allocate and copy string. The trailing NUL shouldn't be necessary, but be safe. */ - tmpbuf = (char *) xmalloc (first + second + 2); + tmpbuf = XNEWVEC (char, first + second + 2); memcpy (tmpbuf, input_line_pointer, first); if (second != 0 && *past_reloc != ' ') /* Replace the relocation token with ' ', so that @@ -7575,7 +7973,7 @@ lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED, /* Allocate and copy string. The trailing NUL shouldn't be necessary, but be safe. */ - tmpbuf = (char *) xmalloc (first + second + 2); + tmpbuf = XNEWVEC (char, first + second + 2); memcpy (tmpbuf, input_line_pointer, first); if (second != 0 && *past_reloc != ' ') /* Replace the relocation token with ' ', so that @@ -8295,7 +8693,7 @@ i386_index_check (const char *operand_string) kind = "string address"; - if (current_templates->start->opcode_modifier.w) + if (current_templates->start->opcode_modifier.repprefixok) { i386_operand_type type = current_templates->end[-1].operand_types[0]; @@ -8365,6 +8763,23 @@ bad_address: || i.index_reg->reg_num == RegEiz)) || !i.index_reg->reg_type.bitfield.baseindex))) goto bad_address; + + /* bndmk, bndldx, and bndstx have special restrictions. */ + if (current_templates->start->base_opcode == 0xf30f1b + || (current_templates->start->base_opcode & ~1) == 0x0f1a) + { + /* They cannot use RIP-relative addressing. */ + if (i.base_reg && i.base_reg->reg_num == RegRip) + { + as_bad (_("`%s' cannot be used here"), operand_string); + return 0; + } + + /* bndldx and bndstx ignore their scale factor. */ + if (current_templates->start->base_opcode != 0xf30f1b + && i.log2_scale_factor) + as_warn (_("register scaling is being ignored here")); + } } else { @@ -8446,6 +8861,49 @@ RC_SAE_immediate (const char *imm_start) return 1; } +/* Only string instructions can have a second memory operand, so + reduce current_templates to just those if it contains any. */ +static int +maybe_adjust_templates (void) +{ + const insn_template *t; + + gas_assert (i.mem_operands == 1); + + for (t = current_templates->start; t < current_templates->end; ++t) + if (t->opcode_modifier.isstring) + break; + + if (t < current_templates->end) + { + static templates aux_templates; + bfd_boolean recheck; + + aux_templates.start = t; + for (; t < current_templates->end; ++t) + if (!t->opcode_modifier.isstring) + break; + aux_templates.end = t; + + /* Determine whether to re-check the first memory operand. */ + recheck = (aux_templates.start != current_templates->start + || t != current_templates->end); + + current_templates = &aux_templates; + + if (recheck) + { + i.mem_operands = 0; + if (i.memop1_string != NULL + && i386_index_check (i.memop1_string) == 0) + return 0; + i.mem_operands = 1; + } + } + + return 1; +} + /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero on error. */ @@ -8573,6 +9031,7 @@ i386_att_operand (char *operand_string) } else if (is_digit_char (*op_string) || is_identifier_char (*op_string) + || *op_string == '"' || *op_string == '(') { /* This is a memory reference of some sort. */ @@ -8584,6 +9043,8 @@ i386_att_operand (char *operand_string) char *vop_start; do_memory_reference: + if (i.mem_operands == 1 && !maybe_adjust_templates ()) + return 0; if ((i.mem_operands == 1 && !current_templates->start->opcode_modifier.isstring) || i.mem_operands == 2) @@ -8761,6 +9222,8 @@ i386_att_operand (char *operand_string) if (i386_index_check (operand_string) == 0) return 0; i.types[this_operand].bitfield.mem = 1; + if (i.mem_operands == 0) + i.memop1_string = xstrdup (operand_string); i.mem_operands++; } else @@ -8787,6 +9250,40 @@ i386_frag_max_var (fragS *frag) return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5; } +#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) +static int +elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var) +{ + /* STT_GNU_IFUNC symbol must go through PLT. */ + if ((symbol_get_bfdsym (fr_symbol)->flags + & BSF_GNU_INDIRECT_FUNCTION) != 0) + return 0; + + if (!S_IS_EXTERNAL (fr_symbol)) + /* Symbol may be weak or local. */ + return !S_IS_WEAK (fr_symbol); + + /* Global symbols with non-default visibility can't be preempted. */ + if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT) + return 1; + + if (fr_var != NO_RELOC) + switch ((enum bfd_reloc_code_real) fr_var) + { + case BFD_RELOC_386_PLT32: + case BFD_RELOC_X86_64_PLT32: + /* Symbol with PLT relocation may be preempted. */ + return 0; + default: + abort (); + } + + /* Global symbols with default visibility in a shared library may be + preempted by another definition. */ + return !shared; +} +#endif + /* md_estimate_size_before_relax() Called just before relax() for rs_machine_dependent frags. The x86 @@ -8810,10 +9307,8 @@ md_estimate_size_before_relax (fragS *fragP, segT segment) if (S_GET_SEGMENT (fragP->fr_symbol) != segment #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || (IS_ELF - && (S_IS_EXTERNAL (fragP->fr_symbol) - || S_IS_WEAK (fragP->fr_symbol) - || ((symbol_get_bfdsym (fragP->fr_symbol)->flags - & BSF_GNU_INDIRECT_FUNCTION)))) + && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol, + fragP->fr_var)) #endif #if defined (OBJ_COFF) && defined (TE_PE) || (OUTPUT_FLAVOR == bfd_target_coff_flavour @@ -9168,11 +9663,6 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) fixP->fx_done = 0; return; - case BFD_RELOC_386_GOT32: - case BFD_RELOC_X86_64_GOT32: - value = 0; /* Fully resolved at runtime. No addend. */ - break; - case BFD_RELOC_VTABLE_INHERIT: case BFD_RELOC_VTABLE_ENTRY: fixP->fx_done = 0; @@ -9209,7 +9699,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) md_number_to_chars (p, value, fixP->fx_size); } -char * +const char * md_atof (int type, char *litP, int *sizeP) { /* This outputs the LITTLENUMs in REVERSE order; @@ -9315,17 +9805,20 @@ parse_real_register (char *reg_string, char **end_op) && !cpu_arch_flags.bitfield.cpu387) return (const reg_entry *) NULL; - if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx) + if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx) + return (const reg_entry *) NULL; + + if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpuregxmm) return (const reg_entry *) NULL; - if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse) + if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuregymm) return (const reg_entry *) NULL; - if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx) + if (r->reg_type.bitfield.regzmm && !cpu_arch_flags.bitfield.cpuregzmm) return (const reg_entry *) NULL; - if ((r->reg_type.bitfield.regzmm || r->reg_type.bitfield.regmask) - && !cpu_arch_flags.bitfield.cpuavx512f) + if (r->reg_type.bitfield.regmask + && !cpu_arch_flags.bitfield.cpuregmask) return (const reg_entry *) NULL; /* Don't allow fake index register unless allow_index_reg isn't 0. */ @@ -9337,11 +9830,13 @@ parse_real_register (char *reg_string, char **end_op) mode. */ if ((r->reg_flags & RegVRex)) { + if (i.vec_encoding == vex_encoding_default) + i.vec_encoding = vex_encoding_evex; + if (!cpu_arch_flags.bitfield.cpuvrex + || i.vec_encoding != vex_encoding_evex || flag_code != CODE_64BIT) return (const reg_entry *) NULL; - - i.need_vrex = 1; } if (((r->reg_flags & (RegRex64 | RegRex)) @@ -9375,7 +9870,7 @@ parse_register (char *reg_string, char **end_op) symbolS *symbolP; input_line_pointer = reg_string; - c = get_symbol_end (); + c = get_symbol_name (®_string); symbolP = symbol_find (reg_string); if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) { @@ -9386,7 +9881,7 @@ parse_register (char *reg_string, char **end_op) && (valueT) e->X_add_number < i386_regtab_size); r = i386_regtab + e->X_add_number; if ((r->reg_flags & RegVRex)) - i.need_vrex = 1; + i.vec_encoding = vex_encoding_evex; *end_op = input_line_pointer; } *input_line_pointer = c; @@ -9481,8 +9976,13 @@ const char *md_shortopts = "qn"; #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16) #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17) #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18) -#define OPTION_OMIT_LOCK_PREFIX (OPTION_MD_BASE + 19) +#define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19) #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20) +#define OPTION_MSHARED (OPTION_MD_BASE + 21) +#define OPTION_MAMD64 (OPTION_MD_BASE + 22) +#define OPTION_MINTEL64 (OPTION_MD_BASE + 23) +#define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24) +#define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25) struct option md_longopts[] = { @@ -9493,6 +9993,7 @@ struct option md_longopts[] = #endif #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) {"x32", no_argument, NULL, OPTION_X32}, + {"mshared", no_argument, NULL, OPTION_MSHARED}, #endif {"divide", no_argument, NULL, OPTION_DIVIDE}, {"march", required_argument, NULL, OPTION_MARCH}, @@ -9512,17 +10013,21 @@ struct option md_longopts[] = # if defined (TE_PE) || defined (TE_PEP) {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ}, #endif - {"momit-lock-prefix", required_argument, NULL, OPTION_OMIT_LOCK_PREFIX}, + {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX}, + {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD}, + {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS}, {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG}, + {"mamd64", no_argument, NULL, OPTION_MAMD64}, + {"mintel64", no_argument, NULL, OPTION_MINTEL64}, {NULL, no_argument, NULL, 0} }; size_t md_longopts_size = sizeof (md_longopts); int -md_parse_option (int c, char *arg) +md_parse_option (int c, const char *arg) { unsigned int j; - char *arch, *next; + char *arch, *next, *saved; switch (c) { @@ -9553,6 +10058,10 @@ md_parse_option (int c, char *arg) /* -s: On i386 Solaris, this tells the native assembler to use .stab instead of .stab.excl. We always use .stab anyhow. */ break; + + case OPTION_MSHARED: + shared = 1; + break; #endif #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) @@ -9610,7 +10119,7 @@ md_parse_option (int c, char *arg) char *n, *t; const char *s; - n = (char *) xmalloc (strlen (i386_comment_chars) + 1); + n = XNEWVEC (char, strlen (i386_comment_chars) + 1); t = n; for (s = i386_comment_chars; *s != '\0'; s++) if (*s != '/') @@ -9622,7 +10131,11 @@ md_parse_option (int c, char *arg) break; case OPTION_MARCH: - arch = xstrdup (arg); + saved = xstrdup (arg); + arch = saved; + /* Allow -march=+nosse. */ + if (*arch == '+') + arch++; do { if (*arch == '.') @@ -9653,15 +10166,12 @@ md_parse_option (int c, char *arg) else if (*cpu_arch [j].name == '.' && strcmp (arch, cpu_arch [j].name + 1) == 0) { - /* ISA entension. */ + /* ISA extension. */ i386_cpu_flags flags; - if (!cpu_arch[j].negated) - flags = cpu_flags_or (cpu_arch_flags, - cpu_arch[j].flags); - else - flags = cpu_flags_and_not (cpu_arch_flags, - cpu_arch[j].flags); + flags = cpu_flags_or (cpu_arch_flags, + cpu_arch[j].flags); + if (!cpu_flags_equal (&flags, &cpu_arch_flags)) { if (cpu_sub_arch_name) @@ -9681,12 +10191,44 @@ md_parse_option (int c, char *arg) } } + if (j >= ARRAY_SIZE (cpu_arch)) + { + /* Disable an ISA extension. */ + for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) + if (strcmp (arch, cpu_noarch [j].name) == 0) + { + i386_cpu_flags flags; + + flags = cpu_flags_and_not (cpu_arch_flags, + cpu_noarch[j].flags); + if (!cpu_flags_equal (&flags, &cpu_arch_flags)) + { + if (cpu_sub_arch_name) + { + char *name = cpu_sub_arch_name; + cpu_sub_arch_name = concat (arch, + (const char *) NULL); + free (name); + } + else + cpu_sub_arch_name = xstrdup (arch); + cpu_arch_flags = flags; + cpu_arch_isa_flags = flags; + } + break; + } + + if (j >= ARRAY_SIZE (cpu_noarch)) + j = ARRAY_SIZE (cpu_arch); + } + if (j >= ARRAY_SIZE (cpu_arch)) as_fatal (_("invalid -march= option: `%s'"), arg); arch = next; } - while (next != NULL ); + while (next != NULL); + free (saved); break; case OPTION_MTUNE: @@ -9814,7 +10356,7 @@ md_parse_option (int c, char *arg) break; #endif - case OPTION_OMIT_LOCK_PREFIX: + case OPTION_MOMIT_LOCK_PREFIX: if (strcasecmp (arg, "yes") == 0) omit_lock_prefix = 1; else if (strcasecmp (arg, "no") == 0) @@ -9823,6 +10365,32 @@ md_parse_option (int c, char *arg) as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg); break; + case OPTION_MFENCE_AS_LOCK_ADD: + if (strcasecmp (arg, "yes") == 0) + avoid_fence = 1; + else if (strcasecmp (arg, "no") == 0) + avoid_fence = 0; + else + as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg); + break; + + case OPTION_MRELAX_RELOCATIONS: + if (strcasecmp (arg, "yes") == 0) + generate_relax_relocations = 1; + else if (strcasecmp (arg, "no") == 0) + generate_relax_relocations = 0; + else + as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg); + break; + + case OPTION_MAMD64: + intel64 = 0; + break; + + case OPTION_MINTEL64: + intel64 = 1; + break; + default: return 0; } @@ -9832,6 +10400,44 @@ md_parse_option (int c, char *arg) #define MESSAGE_TEMPLATE \ " " +static char * +output_message (FILE *stream, char *p, char *message, char *start, + int *left_p, const char *name, int len) +{ + int size = sizeof (MESSAGE_TEMPLATE); + int left = *left_p; + + /* Reserve 2 spaces for ", " or ",\0" */ + left -= len + 2; + + /* Check if there is any room. */ + if (left >= 0) + { + if (p != start) + { + *p++ = ','; + *p++ = ' '; + } + p = mempcpy (p, name, len); + } + else + { + /* Output the current message now and start a new one. */ + *p++ = ','; + *p = '\0'; + fprintf (stream, "%s\n", message); + p = start; + left = size - (start - message) - len - 2; + + gas_assert (left >= 0); + + p = mempcpy (p, name, len); + } + + *left_p = left; + return p; +} + static void show_arch (FILE *stream, int ext, int check) { @@ -9876,34 +10482,19 @@ show_arch (FILE *stream, int ext, int check) continue; } - /* Reserve 2 spaces for ", " or ",\0" */ - left -= len + 2; - - /* Check if there is any room. */ - if (left >= 0) - { - if (p != start) - { - *p++ = ','; - *p++ = ' '; - } - p = mempcpy (p, name, len); - } - else - { - /* Output the current message now and start a new one. */ - *p++ = ','; - *p = '\0'; - fprintf (stream, "%s\n", message); - p = start; - left = size - (start - message) - len - 2; - - gas_assert (left >= 0); - - p = mempcpy (p, name, len); - } + p = output_message (stream, p, message, start, &left, name, len); } + /* Display disabled extensions. */ + if (ext) + for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) + { + name = cpu_noarch [j].name; + len = cpu_noarch [j].len; + p = output_message (stream, p, message, start, &left, name, + len); + } + *p = '\0'; fprintf (stream, "%s\n", message); } @@ -9979,6 +10570,8 @@ md_show_usage (FILE *stream) -mold-gcc support old (<= 2.8.1) versions of gcc\n")); fprintf (stream, _("\ -madd-bnd-prefix add BND prefix for all valid branches\n")); + fprintf (stream, _("\ + -mshared disable branch optimization for shared code\n")); # if defined (TE_PE) || defined (TE_PEP) fprintf (stream, _("\ -mbig-obj generate big object files\n")); @@ -9986,6 +10579,17 @@ md_show_usage (FILE *stream) fprintf (stream, _("\ -momit-lock-prefix=[no|yes]\n\ strip all lock prefixes\n")); + fprintf (stream, _("\ + -mfence-as-lock-add=[no|yes]\n\ + encode lfence, mfence and sfence as\n\ + lock addl $0x0, (%%{re}sp)\n")); + fprintf (stream, _("\ + -mrelax-relocations=[no|yes]\n\ + generate relax relocations\n")); + fprintf (stream, _("\ + -mamd64 accept only AMD64 ISA\n")); + fprintf (stream, _("\ + -mintel64 accept only Intel64 ISA\n")); } #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ @@ -10007,6 +10611,27 @@ i386_target_format (void) } else if (!strcmp (default_arch, "i386")) update_code_flag (CODE_32BIT, 1); + else if (!strcmp (default_arch, "iamcu")) + { + update_code_flag (CODE_32BIT, 1); + if (cpu_arch_isa == PROCESSOR_UNKNOWN) + { + static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS; + cpu_arch_name = "iamcu"; + cpu_sub_arch_name = NULL; + cpu_arch_flags = iamcu_flags; + cpu_arch_isa = PROCESSOR_IAMCU; + cpu_arch_isa_flags = iamcu_flags; + if (!cpu_arch_tune_set) + { + cpu_arch_tune = cpu_arch_isa; + cpu_arch_tune_flags = cpu_arch_isa_flags; + } + } + else if (cpu_arch_isa != PROCESSOR_IAMCU) + as_fatal (_("Intel MCU doesn't support `%s' architecture"), + cpu_arch_name); + } else as_fatal (_("unknown architecture")); @@ -10064,12 +10689,18 @@ i386_target_format (void) as_fatal (_("Intel L1OM is 64bit only")); return ELF_TARGET_L1OM_FORMAT; } - if (cpu_arch_isa == PROCESSOR_K1OM) + else if (cpu_arch_isa == PROCESSOR_K1OM) { if (x86_elf_abi != X86_64_ABI) as_fatal (_("Intel K1OM is 64bit only")); return ELF_TARGET_K1OM_FORMAT; } + else if (cpu_arch_isa == PROCESSOR_IAMCU) + { + if (x86_elf_abi != I386_ABI) + as_fatal (_("Intel MCU is 32bit only")); + return ELF_TARGET_IAMCU_FORMAT; + } else return format; } @@ -10092,48 +10723,6 @@ i386_target_format (void) } #endif /* OBJ_MAYBE_ more than one */ - -#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) -void -i386_elf_emit_arch_note (void) -{ - if (IS_ELF && cpu_arch_name != NULL) - { - char *p; - asection *seg = now_seg; - subsegT subseg = now_subseg; - Elf_Internal_Note i_note; - Elf_External_Note e_note; - asection *note_secp; - int len; - - /* Create the .note section. */ - note_secp = subseg_new (".note", 0); - bfd_set_section_flags (stdoutput, - note_secp, - SEC_HAS_CONTENTS | SEC_READONLY); - - /* Process the arch string. */ - len = strlen (cpu_arch_name); - - i_note.namesz = len + 1; - i_note.descsz = 0; - i_note.type = NT_ARCH; - p = frag_more (sizeof (e_note.namesz)); - md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz)); - p = frag_more (sizeof (e_note.descsz)); - md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz)); - p = frag_more (sizeof (e_note.type)); - md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type)); - p = frag_more (len + 1); - strcpy (p, cpu_arch_name); - - frag_align (2, 0, 0); - - subseg_set (seg, subseg); - } -} -#endif symbolS * md_undefined_symbol (char *name) @@ -10171,7 +10760,7 @@ md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) int align; align = bfd_get_section_alignment (stdoutput, segment); - size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); + size = ((size + (1 << align) - 1) & (-((valueT) 1 << align))); } #endif @@ -10209,23 +10798,41 @@ s_bss (int ignore ATTRIBUTE_UNUSED) void i386_validate_fix (fixS *fixp) { - if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol) + if (fixp->fx_subsy) { - if (fixp->fx_r_type == BFD_RELOC_32_PCREL) + if (fixp->fx_subsy == GOT_symbol) { - if (!object_64bit) - abort (); - fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; - } - else - { - if (!object_64bit) - fixp->fx_r_type = BFD_RELOC_386_GOTOFF; + if (fixp->fx_r_type == BFD_RELOC_32_PCREL) + { + if (!object_64bit) + abort (); +#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) + if (fixp->fx_tcbit2) + fixp->fx_r_type = (fixp->fx_tcbit + ? BFD_RELOC_X86_64_REX_GOTPCRELX + : BFD_RELOC_X86_64_GOTPCRELX); + else +#endif + fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; + } else - fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; + { + if (!object_64bit) + fixp->fx_r_type = BFD_RELOC_386_GOTOFF; + else + fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; + } + fixp->fx_subsy = 0; } - fixp->fx_subsy = 0; } +#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) + else if (!object_64bit) + { + if (fixp->fx_r_type == BFD_RELOC_386_GOT32 + && fixp->fx_tcbit2) + fixp->fx_r_type = BFD_RELOC_386_GOT32X; + } +#endif } arelent * @@ -10255,12 +10862,16 @@ tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) return NULL; } #endif + /* Fall through. */ case BFD_RELOC_X86_64_PLT32: case BFD_RELOC_X86_64_GOT32: case BFD_RELOC_X86_64_GOTPCREL: + case BFD_RELOC_X86_64_GOTPCRELX: + case BFD_RELOC_X86_64_REX_GOTPCRELX: case BFD_RELOC_386_PLT32: case BFD_RELOC_386_GOT32: + case BFD_RELOC_386_GOT32X: case BFD_RELOC_386_GOTOFF: case BFD_RELOC_386_GOTPC: case BFD_RELOC_386_TLS_GD: @@ -10304,6 +10915,7 @@ tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) code = fixp->fx_r_type; break; } + /* Fall through. */ default: if (fixp->fx_pcrel) { @@ -10362,8 +10974,8 @@ tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) code = BFD_RELOC_X86_64_GOTPC64; } - rel = (arelent *) xmalloc (sizeof (arelent)); - rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); + rel = XNEW (arelent); + rel->sym_ptr_ptr = XNEW (asymbol *); *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); rel->address = fixp->fx_frag->fr_address + fixp->fx_where; @@ -10412,6 +11024,8 @@ tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) case BFD_RELOC_X86_64_PLT32: case BFD_RELOC_X86_64_GOT32: case BFD_RELOC_X86_64_GOTPCREL: + case BFD_RELOC_X86_64_GOTPCRELX: + case BFD_RELOC_X86_64_REX_GOTPCRELX: case BFD_RELOC_X86_64_TLSGD: case BFD_RELOC_X86_64_TLSLD: case BFD_RELOC_X86_64_GOTTPOFF: @@ -10542,7 +11156,7 @@ tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */ bfd_vma -x86_64_section_letter (int letter, char **ptr_msg) +x86_64_section_letter (int letter, const char **ptr_msg) { if (flag_code == CODE_64BIT) {