X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=gas%2Fdoc%2Fc-i386.texi;h=74296e61f698966e92cb22a1807f576623eafad3;hb=e379e5f385f874adb0b414f917adb1fc50e20de9;hp=7ca70c91dbbedc03a78bd7ffe993828437e84f2e;hpb=9aff4b7ac12edba0c170c2a55763c3973b708749;p=deliverable%2Fbinutils-gdb.git diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index 7ca70c91db..74296e61f6 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -1,4 +1,4 @@ -@c Copyright 1991-2013 Free Software Foundation, Inc. +@c Copyright (C) 1991-2019 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @c man end @@ -74,7 +74,8 @@ usage and use x86-64 as target platform). @item -n By default, x86 GAS replaces multiple nop instructions used for alignment within code sections with multi-byte nop instructions such -as leal 0(%esi,1),%esi. This switch disables the optimization. +as leal 0(%esi,1),%esi. This switch disables the optimization if a single +byte nop (0x90) is explicitly specified as the fill byte for alignment. @cindex @samp{--divide} option, i386 @item --divide @@ -110,6 +111,7 @@ processor names are recognized: @code{corei7}, @code{l1om}, @code{k1om}, +@code{iamcu}, @code{k6}, @code{k6_2}, @code{athlon}, @@ -119,6 +121,9 @@ processor names are recognized: @code{bdver1}, @code{bdver2}, @code{bdver3}, +@code{bdver4}, +@code{znver1}, +@code{znver2}, @code{btver1}, @code{btver2}, @code{generic32} and @@ -131,7 +136,15 @@ accept various extension mnemonics. For example, @code{8087}, @code{287}, @code{387}, +@code{687}, @code{no87}, +@code{no287}, +@code{no387}, +@code{no687}, +@code{cmov}, +@code{nocmov}, +@code{fxsr}, +@code{nofxsr}, @code{mmx}, @code{nommx}, @code{sse}, @@ -142,24 +155,76 @@ accept various extension mnemonics. For example, @code{sse4.2}, @code{sse4}, @code{nosse}, +@code{nosse2}, +@code{nosse3}, +@code{nossse3}, +@code{nosse4.1}, +@code{nosse4.2}, +@code{nosse4}, @code{avx}, @code{avx2}, +@code{noavx}, +@code{noavx2}, @code{adx}, @code{rdseed}, @code{prfchw}, @code{smap}, @code{mpx}, @code{sha}, +@code{rdpid}, +@code{ptwrite}, +@code{cet}, +@code{gfni}, +@code{vaes}, +@code{vpclmulqdq}, +@code{prefetchwt1}, +@code{clflushopt}, +@code{se1}, +@code{clwb}, +@code{movdiri}, +@code{movdir64b}, +@code{enqcmd}, @code{avx512f}, @code{avx512cd}, @code{avx512er}, @code{avx512pf}, -@code{noavx}, +@code{avx512vl}, +@code{avx512bw}, +@code{avx512dq}, +@code{avx512ifma}, +@code{avx512vbmi}, +@code{avx512_4fmaps}, +@code{avx512_4vnniw}, +@code{avx512_vpopcntdq}, +@code{avx512_vbmi2}, +@code{avx512_vnni}, +@code{avx512_bitalg}, +@code{avx512_bf16}, +@code{noavx512f}, +@code{noavx512cd}, +@code{noavx512er}, +@code{noavx512pf}, +@code{noavx512vl}, +@code{noavx512bw}, +@code{noavx512dq}, +@code{noavx512ifma}, +@code{noavx512vbmi}, +@code{noavx512_4fmaps}, +@code{noavx512_4vnniw}, +@code{noavx512_vpopcntdq}, +@code{noavx512_vbmi2}, +@code{noavx512_vnni}, +@code{noavx512_bitalg}, +@code{noavx512_vp2intersect}, +@code{noavx512_bf16}, +@code{noenqcmd}, @code{vmx}, @code{vmfunc}, @code{smx}, @code{xsave}, @code{xsaveopt}, +@code{xsavec}, +@code{xsaves}, @code{aes}, @code{pclmul}, @code{fsgsbase}, @@ -174,6 +239,14 @@ accept various extension mnemonics. For example, @code{rtm}, @code{invpcid}, @code{clflush}, +@code{mwaitx}, +@code{clzero}, +@code{wbnoinvd}, +@code{pconfig}, +@code{waitpkg}, +@code{cldemote}, +@code{rdpru}, +@code{mcommit}, @code{lwp}, @code{fma4}, @code{xop}, @@ -232,6 +305,22 @@ AVX instructions with 128bit vector length, which is the default. @option{-mavxscalar=@var{256}} will encode scalar AVX instructions with 256bit vector length. +WARNING: Don't use this for production code - due to CPU errata the +resulting code may not work on certain models. + +@cindex @samp{-mvexwig=} option, i386 +@cindex @samp{-mvexwig=} option, x86-64 +@item -mvexwig=@var{0} +@itemx -mvexwig=@var{1} +These options control how the assembler should encode VEX.W-ignored (WIG) +VEX instructions. @option{-mvexwig=@var{0}} will encode WIG VEX +instructions with vex.w = 0, which is the default. +@option{-mvexwig=@var{1}} will encode WIG EVEX instructions with +vex.w = 1. + +WARNING: Don't use this for production code - due to CPU errata the +resulting code may not work on certain models. + @cindex @samp{-mevexlig=} option, i386 @cindex @samp{-mevexlig=} option, x86-64 @item -mevexlig=@var{128} @@ -273,7 +362,7 @@ take precedent. @cindex @samp{-mnaked-reg} option, i386 @cindex @samp{-mnaked-reg} option, x86-64 @item -mnaked-reg -This opetion specifies that registers don't require a @samp{%} prefix. +This option specifies that registers don't require a @samp{%} prefix. The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent. @cindex @samp{-madd-bnd-prefix} option, i386 @@ -282,6 +371,147 @@ The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent. This option forces the assembler to add BND prefix to all branches, even if such prefix was not explicitly specified in the source code. +@cindex @samp{-mshared} option, i386 +@cindex @samp{-mshared} option, x86-64 +@item -mno-shared +On ELF target, the assembler normally optimizes out non-PLT relocations +against defined non-weak global branch targets with default visibility. +The @samp{-mshared} option tells the assembler to generate code which +may go into a shared library where all non-weak global branch targets +with default visibility can be preempted. The resulting code is +slightly bigger. This option only affects the handling of branch +instructions. + +@cindex @samp{-mbig-obj} option, x86-64 +@item -mbig-obj +On x86-64 PE/COFF target this option forces the use of big object file +format, which allows more than 32768 sections. + +@cindex @samp{-momit-lock-prefix=} option, i386 +@cindex @samp{-momit-lock-prefix=} option, x86-64 +@item -momit-lock-prefix=@var{no} +@itemx -momit-lock-prefix=@var{yes} +These options control how the assembler should encode lock prefix. +This option is intended as a workaround for processors, that fail on +lock prefix. This option can only be safely used with single-core, +single-thread computers +@option{-momit-lock-prefix=@var{yes}} will omit all lock prefixes. +@option{-momit-lock-prefix=@var{no}} will encode lock prefix as usual, +which is the default. + +@cindex @samp{-mfence-as-lock-add=} option, i386 +@cindex @samp{-mfence-as-lock-add=} option, x86-64 +@item -mfence-as-lock-add=@var{no} +@itemx -mfence-as-lock-add=@var{yes} +These options control how the assembler should encode lfence, mfence and +sfence. +@option{-mfence-as-lock-add=@var{yes}} will encode lfence, mfence and +sfence as @samp{lock addl $0x0, (%rsp)} in 64-bit mode and +@samp{lock addl $0x0, (%esp)} in 32-bit mode. +@option{-mfence-as-lock-add=@var{no}} will encode lfence, mfence and +sfence as usual, which is the default. + +@cindex @samp{-mrelax-relocations=} option, i386 +@cindex @samp{-mrelax-relocations=} option, x86-64 +@item -mrelax-relocations=@var{no} +@itemx -mrelax-relocations=@var{yes} +These options control whether the assembler should generate relax +relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX and +R_X86_64_REX_GOTPCRELX, in 64-bit mode. +@option{-mrelax-relocations=@var{yes}} will generate relax relocations. +@option{-mrelax-relocations=@var{no}} will not generate relax +relocations. The default can be controlled by a configure option +@option{--enable-x86-relax-relocations}. + +@cindex @samp{-malign-branch-boundary=} option, i386 +@cindex @samp{-malign-branch-boundary=} option, x86-64 +@item -malign-branch-boundary=@var{NUM} +This option controls how the assembler should align branches with segment +prefixes or NOP. @var{NUM} must be a power of 2. It should be 0 or +no less than 16. Branches will be aligned within @var{NUM} byte +boundary. @option{-malign-branch-boundary=0}, which is the default, +doesn't align branches. + +@cindex @samp{-malign-branch=} option, i386 +@cindex @samp{-malign-branch=} option, x86-64 +@item -malign-branch=@var{TYPE}[+@var{TYPE}...] +This option specifies types of branches to align. @var{TYPE} is +combination of @samp{jcc}, which aligns conditional jumps, +@samp{fused}, which aligns fused conditional jumps, @samp{jmp}, +which aligns unconditional jumps, @samp{call} which aligns calls, +@samp{ret}, which aligns rets, @samp{indirect}, which aligns indirect +jumps and calls. The default is @option{-malign-branch=jcc+fused+jmp}. + +@cindex @samp{-malign-branch-prefix-size=} option, i386 +@cindex @samp{-malign-branch-prefix-size=} option, x86-64 +@item -malign-branch-prefix-size=@var{NUM} +This option specifies the maximum number of prefixes on an instruction +to align branches. @var{NUM} should be between 0 and 5. The default +@var{NUM} is 5. + +@cindex @samp{-mx86-used-note=} option, i386 +@cindex @samp{-mx86-used-note=} option, x86-64 +@item -mx86-used-note=@var{no} +@itemx -mx86-used-note=@var{yes} +These options control whether the assembler should generate +GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_FEATURE_2_USED +GNU property notes. The default can be controlled by the +@option{--enable-x86-used-note} configure option. + +@cindex @samp{-mevexrcig=} option, i386 +@cindex @samp{-mevexrcig=} option, x86-64 +@item -mevexrcig=@var{rne} +@itemx -mevexrcig=@var{rd} +@itemx -mevexrcig=@var{ru} +@itemx -mevexrcig=@var{rz} +These options control how the assembler should encode SAE-only +EVEX instructions. @option{-mevexrcig=@var{rne}} will encode RC bits +of EVEX instruction with 00, which is the default. +@option{-mevexrcig=@var{rd}}, @option{-mevexrcig=@var{ru}} +and @option{-mevexrcig=@var{rz}} will encode SAE-only EVEX instructions +with 01, 10 and 11 RC bits, respectively. + +@cindex @samp{-mamd64} option, x86-64 +@cindex @samp{-mintel64} option, x86-64 +@item -mamd64 +@itemx -mintel64 +This option specifies that the assembler should accept only AMD64 or +Intel64 ISA in 64-bit mode. The default is to accept both. + +@cindex @samp{-O0} option, i386 +@cindex @samp{-O0} option, x86-64 +@cindex @samp{-O} option, i386 +@cindex @samp{-O} option, x86-64 +@cindex @samp{-O1} option, i386 +@cindex @samp{-O1} option, x86-64 +@cindex @samp{-O2} option, i386 +@cindex @samp{-O2} option, x86-64 +@cindex @samp{-Os} option, i386 +@cindex @samp{-Os} option, x86-64 +@item -O0 | -O | -O1 | -O2 | -Os +Optimize instruction encoding with smaller instruction size. @samp{-O} +and @samp{-O1} encode 64-bit register load instructions with 64-bit +immediate as 32-bit register load instructions with 31-bit or 32-bits +immediates, encode 64-bit register clearing instructions with 32-bit +register clearing instructions, encode 256-bit/512-bit VEX/EVEX vector +register clearing instructions with 128-bit VEX vector register +clearing instructions, encode 128-bit/256-bit EVEX vector +register load/store instructions with VEX vector register load/store +instructions, and encode 128-bit/256-bit EVEX packed integer logical +instructions with 128-bit/256-bit VEX packed integer logical. + +@samp{-O2} includes @samp{-O1} optimization plus encodes +256-bit/512-bit EVEX vector register clearing instructions with 128-bit +EVEX vector register clearing instructions. In 64-bit mode VEX encoded +instructions with commutative source operands will also have their +source operands swapped if this allows using the 2-byte VEX prefix form +instead of the 3-byte one. Certain forms of AND as well as OR with the +same (register) operand specified twice will also be changed to TEST. + +@samp{-Os} includes @samp{-O2} optimization plus encodes 16-bit, 32-bit +and 64-bit register tests with immediate as 8-bit register test with +immediate. @samp{-O0} turns off this optimization. + @end table @c man end @@ -304,8 +534,23 @@ specifies the desired alignment of the symbol in the bss section. This directive is only available for COFF based x86 targets. +@cindex @code{largecomm} directive, ELF +@item .largecomm @var{symbol} , @var{length}[, @var{alignment}] +This directive behaves in the same way as the @code{comm} directive +except that the data is placed into the @var{.lbss} section instead of +the @var{.bss} section @ref{Comm}. + +The directive is intended to be used for data which requires a large +amount of space, and it is only available for ELF based x86_64 +targets. + +@cindex @code{value} directive +@item .value @var{expression} [, @var{expression}] +This directive behaves in the same way as the @code{.short} directive, +taking a series of comma separated expressions and storing them as +two-byte wide values into the current section. + @c FIXME: Document other x86 specific directives ? Eg: .code16gcc, -@c .largecomm @end table @@ -387,11 +632,16 @@ instruction, do @emph{not} have reversed order. @ref{i386-Bugs}. In AT&T syntax the size of memory operands is determined from the last character of the instruction mnemonic. Mnemonic suffixes of @samp{b}, @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long -(32-bit) and quadruple word (64-bit) memory references. Intel syntax accomplishes -this by prefixing memory operands (@emph{not} the instruction mnemonics) with -@samp{byte ptr}, @samp{word ptr}, @samp{dword ptr} and @samp{qword ptr}. Thus, -Intel @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T -syntax. +(32-bit) and quadruple word (64-bit) memory references. Mnemonic suffixes +of @samp{x}, @samp{y} and @samp{z} specify xmm (128-bit vector), ymm +(256-bit vector) and zmm (512-bit vector) memory references, only when there's +no other way to disambiguate an instruction. Intel syntax accomplishes this by +prefixing memory operands (@emph{not} the instruction mnemonics) with +@samp{byte ptr}, @samp{word ptr}, @samp{dword ptr}, @samp{qword ptr}, +@samp{xmmword ptr}, @samp{ymmword ptr} and @samp{zmmword ptr}. Thus, Intel +syntax @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T +syntax. In Intel syntax, @samp{fword ptr}, @samp{tbyte ptr} and +@samp{oword ptr} specify 48-bit, 80-bit and 128-bit memory references. In 64-bit code, @samp{movabs} can be used to encode the @samp{mov} instruction with the 64-bit displacement or immediate operand. @@ -431,7 +681,7 @@ line is treated as a comment, but in this case the line can also be a logical line number directive (@pxref{Comments}) or a preprocessor control command (@pxref{Preprocessing}). -If the @option{--divide} command line option has not been specified +If the @option{--divide} command-line option has not been specified then the @samp{/} character appearing anywhere on a line also introduces a line comment. @@ -442,7 +692,8 @@ The @samp{;} character can be used to separate statements on the same line. @node i386-Mnemonics -@section Instruction Naming +@section i386-Mnemonics +@subsection Instruction Naming @cindex i386 instruction naming @cindex instruction naming, i386 @@ -480,10 +731,38 @@ quadruple word). @cindex encoding options, i386 @cindex encoding options, x86-64 -Different encoding options can be specified via optional mnemonic -suffix. @samp{.s} suffix swaps 2 register operands in encoding when -moving from one register to another. @samp{.d8} or @samp{.d32} suffix -prefers 8bit or 32bit displacement in encoding. +Different encoding options can be specified via pseudo prefixes: + +@itemize @bullet +@item +@samp{@{disp8@}} -- prefer 8-bit displacement. + +@item +@samp{@{disp32@}} -- prefer 32-bit displacement. + +@item +@samp{@{load@}} -- prefer load-form instruction. + +@item +@samp{@{store@}} -- prefer store-form instruction. + +@item +@samp{@{vex2@}} -- prefer 2-byte VEX prefix for VEX instruction. + +@item +@samp{@{vex3@}} -- prefer 3-byte VEX prefix for VEX instruction. + +@item +@samp{@{evex@}} -- encode with EVEX prefix. + +@item +@samp{@{rex@}} -- prefer REX prefix for integer and legacy vector +instructions (x86-64 only). Note that this differs from the @samp{rex} +prefix which generates REX prefix unconditionally. + +@item +@samp{@{nooptimize@}} -- disable instruction size optimization. +@end itemize @cindex conversion instructions, i386 @cindex i386 conversion instructions @@ -526,7 +805,7 @@ Far call/jump instructions are @samp{lcall} and @samp{ljmp} in AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel convention. -@section AT&T Mnemonic versus Intel Mnemonic +@subsection AT&T Mnemonic versus Intel Mnemonic @cindex i386 mnemonic compatibility @cindex mnemonic compatibility, i386 @@ -573,8 +852,8 @@ the 6 section registers @samp{%cs} (code section), @samp{%ds} and @samp{%gs}. @item -the 3 processor control registers @samp{%cr0}, @samp{%cr2}, and -@samp{%cr3}. +the 5 processor control registers @samp{%cr0}, @samp{%cr2}, +@samp{%cr3}, @samp{%cr4}, and @samp{%cr8}. @item the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2}, @@ -592,7 +871,7 @@ These registers are overloaded by 8 MMX registers @samp{%mm0}, @samp{%mm6} and @samp{%mm7}. @item -the 8 SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2}, +the 8 128-bit SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2}, @samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}. @end itemize @@ -609,13 +888,13 @@ pointer) the 8 extended registers @samp{%r8}--@samp{%r15}. @item -the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d} +the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}. @item -the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w} +the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}. @item -the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b} +the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}. @item the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}. @@ -624,7 +903,43 @@ the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}. the 8 debug registers: @samp{%db8}--@samp{%db15}. @item -the 8 SSE registers: @samp{%xmm8}--@samp{%xmm15}. +the 8 128-bit SSE registers: @samp{%xmm8}--@samp{%xmm15}. +@end itemize + +With the AVX extensions more registers were made available: + +@itemize @bullet + +@item +the 16 256-bit SSE @samp{%ymm0}--@samp{%ymm15} (only the first 8 +available in 32-bit mode). The bottom 128 bits are overlaid with the +@samp{xmm0}--@samp{xmm15} registers. + +@end itemize + +The AVX2 extensions made in 64-bit mode more registers available: + +@itemize @bullet + +@item +the 16 128-bit registers @samp{%xmm16}--@samp{%xmm31} and the 16 256-bit +registers @samp{%ymm16}--@samp{%ymm31}. + +@end itemize + +The AVX512 extensions added the following registers: + +@itemize @bullet + +@item +the 32 512-bit registers @samp{%zmm0}--@samp{%zmm31} (only the first 8 +available in 32-bit mode). The bottom 128 bits are overlaid with the +@samp{%xmm0}--@samp{%xmm31} registers and the first 256 bits are +overlaid with the @samp{%ymm0}--@samp{%ymm31} registers. + +@item +the 8 mask registers @samp{%k0}--@samp{%k7}. + @end itemize @node i386-Prefixes @@ -1008,27 +1323,6 @@ opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which is correct since the processor default operand size is assumed to be 16 bits in a 16-bit code section. -@node i386-Bugs -@section AT&T Syntax bugs - -The UnixWare assembler, and probably other AT&T derived ix86 Unix -assemblers, generate floating point instructions with reversed source -and destination registers in certain cases. Unfortunately, gcc and -possibly many other programs use this reversed syntax, so we're stuck -with it. - -For example - -@smallexample - fsub %st,%st(3) -@end smallexample -@noindent -results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather -than the expected @samp{%st(3) - %st}. This happens with all the -non-commutative arithmetic floating point operations with two register -operands where the source register is @samp{%st} and the destination -register is @samp{%st(i)}. - @node i386-Arch @section Specifying CPU Architecture @@ -1047,12 +1341,13 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium} @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4} @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2} -@item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om} +@item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om} @tab @samp{iamcu} @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8} @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3} -@item @samp{btver1} @tab @samp{btver2} -@item @samp{generic32} @tab @samp{generic64} -@item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3} +@item @samp{bdver4} @tab @samp{znver1} @tab @samp{znver2} @tab @samp{btver1} +@item @samp{btver2} @tab @samp{generic32} @tab @samp{generic64} +@item @samp{.cmov} @tab @samp{.fxsr} @tab @samp{.mmx} +@item @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3} @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4} @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept} @item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt} @@ -1060,17 +1355,22 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2} @item @samp{.lzcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} @tab @samp{.hle} @item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw} -@item @samp{.smap} @tab @samp{.mpx} -@item @samp{.smap} @tab @samp{.sha} +@item @samp{.smap} @tab @samp{.mpx} @tab @samp{.sha} @tab @samp{.prefetchwt1} +@item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1} +@item @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} @tab @samp{.avx512pf} +@item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab @samp{.avx512ifma} +@item @samp{.avx512vbmi} @tab @samp{.avx512_4fmaps} @tab @samp{.avx512_4vnniw} +@item @samp{.avx512_vpopcntdq} @tab @samp{.avx512_vbmi2} @tab @samp{.avx512_vnni} +@item @samp{.avx512_bitalg} @tab @samp{.avx512_bf16} @tab @samp{.avx512_vp2intersect} +@item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @item @samp{.ibt} +@item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote} +@item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq} +@item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5} @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm} @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16} -@item @samp{.padlock} -@item @samp{.smap} @tab @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} -@item @samp{.avx512pf} @tab @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} -@item @samp{.sse5} @tab @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} -@item @samp{.abm} @tab @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} -@item @samp{.cx16} @tab @samp{.padlock} +@item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx} @tab @samp{.rdpru} +@item @samp{.mcommit} @end multitable Apart from the warning, there are only two other effects on @@ -1102,6 +1402,27 @@ For example .arch i8086,nojumps @end smallexample +@node i386-Bugs +@section AT&T Syntax bugs + +The UnixWare assembler, and probably other AT&T derived ix86 Unix +assemblers, generate floating point instructions with reversed source +and destination registers in certain cases. Unfortunately, gcc and +possibly many other programs use this reversed syntax, so we're stuck +with it. + +For example + +@smallexample + fsub %st,%st(3) +@end smallexample +@noindent +results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather +than the expected @samp{%st(3) - %st}. This happens with all the +non-commutative arithmetic floating point operations with two register +operands where the source register is @samp{%st} and the destination +register is @samp{%st(i)}. + @node i386-Notes @section Notes