X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=gas%2Fdoc%2Fc-mips.texi;h=8d61d04cf7d865ed45d09459a018fe72efeafdb4;hb=8bd978587880bff236f2b3c20df703c88899be5f;hp=f377ef3c1388ed696e79adaeb6935a45c36ee101;hpb=e335d9cbd89a0a80bd2b0cbdcf60061d3ec75902;p=deliverable%2Fbinutils-gdb.git diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi index f377ef3c13..8d61d04cf7 100644 --- a/gas/doc/c-mips.texi +++ b/gas/doc/c-mips.texi @@ -1,6 +1,4 @@ -@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2000, 2001, -@c 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2013 -@c Free Software Foundation, Inc. +@c Copyright (C) 1991-2014 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @ifset GENERIC @@ -30,6 +28,8 @@ Assembly Language Programming'' in the same work. * MIPS assembly options:: Directives to control code generation * MIPS autoextend:: Directives for extending MIPS 16 bit instructions * MIPS insn:: Directive to mark data as an instruction +* MIPS FP ABIs:: Marking which FP ABI is in use +* MIPS NaN Encodings:: Directives to record which NaN encoding is being used * MIPS Option Stack:: Directives to save and restore options * MIPS ASE Instruction Generation Overrides:: Directives to control generation of MIPS ASE instructions @@ -82,20 +82,26 @@ VxWorks-style position-independent macro expansions. @itemx -mips5 @itemx -mips32 @itemx -mips32r2 +@itemx -mips32r3 +@itemx -mips32r5 +@itemx -mips32r6 @itemx -mips64 @itemx -mips64r2 +@itemx -mips64r3 +@itemx -mips64r5 +@itemx -mips64r6 Generate code for a particular MIPS Instruction Set Architecture level. @samp{-mips1} corresponds to the R2000 and R3000 processors, @samp{-mips2} to the R6000 processor, @samp{-mips3} to the -R4000 processor, and @samp{-mips4} to the R8000 and -R10000 processors. @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, -@samp{-mips64}, and @samp{-mips64r2} -correspond to generic -@sc{MIPS V}, @sc{MIPS32}, @sc{MIPS32 Release 2}, @sc{MIPS64}, -and @sc{MIPS64 Release 2} -ISA processors, respectively. You can also switch -instruction sets during the assembly; see @ref{MIPS ISA, Directives to -override the ISA level}. +R4000 processor, and @samp{-mips4} to the R8000 and R10000 processors. +@samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, @samp{-mips32r3}, +@samp{-mips32r5}, @samp{-mips32r6}, @samp{-mips64}, @samp{-mips64r2}, +@samp{-mips64r3}, @samp{-mips64r5}, and @samp{-mips64r6} correspond to +generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3, MIPS32 +Release 5, MIPS32 Release 6, MIPS64, and MIPS64 Release 2, MIPS64 +Release 3, MIPS64 Release 5, and MIPS64 Release 6 ISA processors, +respectively. You can also switch instruction sets during the assembly; +see @ref{MIPS ISA, Directives to override the ISA level}. @item -mgp32 @itemx -mfp32 @@ -123,6 +129,22 @@ The @code{.set gp=64} and @code{.set fp=64} directives allow the size of registers to be changed for parts of an object. The default value is restored by @code{.set gp=default} and @code{.set fp=default}. +@item -mfpxx +Make no assumptions about whether 32-bit or 64-bit floating-point +registers are available. This is provided to support having modules +compatible with either @samp{-mfp32} or @samp{-mfp64}. This option can +only be used with MIPS II and above. + +The @code{.set fp=xx} directive allows a part of an object to be marked +as not making assumptions about 32-bit or 64-bit FP registers. The +default value is restored by @code{.set fp=default}. + +@item -modd-spreg +@itemx -mno-odd-spreg +Enable use of floating-point operations on odd-numbered single-precision +registers when supported by the ISA. @samp{-mfpxx} implies +@samp{-mno-odd-spreg}, otherwise the default is @samp{-modd-spreg} + @item -mips16 @itemx -no-mips16 Generate code for the MIPS 16 processor. This is equivalent to putting @@ -181,6 +203,18 @@ Generate code for the MCU Application Specific Extension. This tells the assembler to accept MCU instructions. @samp{-mno-mcu} turns off this option. +@item -mmsa +@itemx -mno-msa +Generate code for the MIPS SIMD Architecture Extension. +This tells the assembler to accept MSA instructions. +@samp{-mno-msa} turns off this option. + +@item -mxpa +@itemx -mno-xpa +Generate code for the MIPS eXtended Physical Address (XPA) Extension. +This tells the assembler to accept XPA instructions. +@samp{-mno-xpa} turns off this option. + @item -mvirt @itemx -mno-virt Generate code for the Virtualization Application Specific Extension. @@ -202,6 +236,11 @@ selected, allowing all instructions to be used. Cause nops to be inserted if the read of the destination register of an mfhi or mflo instruction occurs in the following two instructions. +@item -mfix-rm7000 +@itemx -mno-fix-rm7000 +Cause nops to be inserted if a dmult or dmultu instruction is +followed by a load instruction. + @item -mfix-loongson2f-jump @itemx -mno-fix-loongson2f-jump Eliminate instruction fetch from outside 256M region to work around the @@ -330,6 +369,7 @@ m14kec, 1004kf2_1, 1004kf, 1004kf1_1, +p5600, 5kc, 5kf, 20kc, @@ -414,11 +454,21 @@ be relaxed with the use of a longer sequence involving another branch, however this has not been implemented and if their target turns out of reach, they produce an error even if branch relaxation is enabled. -Also no @sc{mips16} branches are ever relaxed. +Also no MIPS16 branches are ever relaxed. By default @samp{--no-relax-branch} is selected, causing any out-of-range branches to produce an error. +@cindex @option{-mnan=} command line option, MIPS +@item -mnan=@var{encoding} +This option indicates whether the source code uses the IEEE 2008 +NaN encoding (@option{-mnan=2008}) or the original MIPS encoding +(@option{-mnan=legacy}). It is equivalent to adding a @code{.nan} +directive to the beginning of the source file. @xref{MIPS NaN Encodings}. + +@option{-mnan=legacy} is the default if no @option{-mnan} option or +@code{.nan} directive is used. + @item --trap @itemx --no-break @c FIXME! (1) reflect these options (next item too) in option summaries; @@ -628,15 +678,15 @@ Small data is not supported for SVR4-style PIC. @kindex @code{.set mips@var{n}} @sc{gnu} @code{@value{AS}} supports an additional directive to change the MIPS Instruction Set Architecture level on the fly: @code{.set -mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 64 -or 64r2. +mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 32r3, +32r5, 32r6, 64, 64r2, 64r3, 64r5 or 64r6. The values other than 0 make the assembler accept instructions for the corresponding ISA level, from that point on in the assembly. @code{.set mips@var{n}} affects not only which instructions are permitted, but also how certain macros are expanded. @code{.set mips0} restores the ISA level to its original level: either the level you selected with command line options, or the default for your -configuration. You can use this feature to permit specific @sc{mips3} +configuration. You can use this feature to permit specific MIPS III instructions while assembling in 32 bit mode. Use this directive with care! @@ -663,6 +713,20 @@ Traditional MIPS assemblers do not support this directive. @node MIPS assembly options @section Directives to control code generation +@cindex MIPS directives to override command line options +@kindex @code{.module} +The @code{.module} directive allows command line options to be set directly +from assembly. The format of the directive matches the @code{.set} +directive but only those options which are relevant to a whole module are +supported. The effect of a @code{.module} directive is the same as the +corresponding command line option. Where @code{.set} directives support +returning to a default then the @code{.module} directives do not as they +define the defaults. + +These module-level directives must appear first in assembly. + +Traditional MIPS assemblers do not support this directive. + @cindex MIPS 32-bit microMIPS instruction generation override @kindex @code{.set insn32} @kindex @code{.set noinsn32} @@ -725,6 +789,156 @@ baz: @end example +@node MIPS FP ABIs +@section Directives to control the FP ABI +@menu +* MIPS FP ABI History:: History of FP ABIs +* MIPS FP ABI Variants:: Supported FP ABIs +* MIPS FP ABI Selection:: Automatic selection of FP ABI +* MIPS FP ABI Compatibility:: Linking different FP ABI variants +@end menu + +@node MIPS FP ABI History +@subsection History of FP ABIs +@cindex @code{.gnu_attribute 4, @var{n}} directive, MIPS +@cindex @code{.gnu_attribute Tag_GNU_MIPS_ABI_FP, @var{n}} directive, MIPS +The MIPS ABIs support a variety of different floating-point extensions +where calling-convention and register sizes vary for floating-point data. +The extensions exist to support a wide variety of optional architecture +features. The resulting ABI variants are generally incompatible with each +other and must be tracked carefully. + +Traditionally the use of an explicit @code{.gnu_attribute 4, @var{n}} +directive is used to indicate which ABI is in use by a specific module. +It was then left to the user to ensure that command line options and the +selected ABI were compatible with some potential for inconsistencies. + +@node MIPS FP ABI Variants +@subsection Supported FP ABIs +The supported floating-point ABI variants are: + +@table @code +@item 0 - No floating-point +This variant is used to indicate that floating-point is not used within +the module at all and therefore has no impact on the ABI. This is the +default. + +@item 1 - Double-precision +This variant indicates that double-precision support is used. For 64-bit +ABIs this means that 64-bit wide floating-point registers are required. +For 32-bit ABIs this means that 32-bit wide floating-point registers are +required and double-precision operations use pairs of registers. + +@item 2 - Single-precision +This variant indicates that single-precision support is used. Double +precision operations will be supported via soft-float routines. + +@item 3 - Soft-float +This variant indicates that although floating-point support is used all +operations are emulated in software. This means the ABI is modified to +pass all floating-point data in general-purpose registers. + +@item 4 - Deprecated +This variant existed as an initial attempt at supporting 64-bit wide +floating-point registers for O32 ABI on a MIPS32r2 cpu. This has been +superceded by 5, 6 and 7. + +@item 5 - Double-precision 32-bit CPU, 32-bit or 64-bit FPU +This variant is used by 32-bit ABIs to indicate that the floating-point +code in the module has been designed to operate correctly with either +32-bit wide or 64-bit wide floating-point registers. Double-precision +support is used. Only O32 currently supports this variant and requires +a minimum architecture of MIPS II. + +@item 6 - Double-precision 32-bit FPU, 64-bit FPU +This variant is used by 32-bit ABIs to indicate that the floating-point +code in the module requires 64-bit wide floating-point registers. +Double-precision support is used. Only O32 currently supports this +variant and requires a minimum architecture of MIPS32r2. + +@item 7 - Double-precision compat 32-bit FPU, 64-bit FPU +This variant is used by 32-bit ABIs to indicate that the floating-point +code in the module requires 64-bit wide floating-point registers. +Double-precision support is used. This differs from the previous ABI +as it restricts use of odd-numbered single-precision registers. Only +O32 currently supports this variant and requires a minimum architecture +of MIPS32r2. +@end table + +@node MIPS FP ABI Selection +@subsection Automatic selection of FP ABI +@cindex @code{.module fp=@var{nn}} directive, MIPS +In order to simplify and add safety to the process of selecting the +correct floating-point ABI, the assembler will automatically infer the +correct @code{.gnu_attribute 4, @var{n}} directive based on command line +options and @code{.module} overrides. Where an explicit +@code{.gnu_attribute 4, @var{n}} directive has been seen then a warning +will be raised if it does not match an inferred setting. + +The floating-point ABI is inferred as follows. If @samp{-msoft-float} +has been used the module will be marked as soft-float. If +@samp{-msingle-float} has been used then the module will be marked as +single-precision. The remaining ABIs are then selected based +on the FP register width. Double-precision is selected if the width +of GP and FP registers match and the special double-precision variants +for 32-bit ABIs are then selected depending on @samp{-mfpxx}, +@samp{-mfp64} and @samp{-mno-odd-spreg}. + +@node MIPS FP ABI Compatibility +@subsection Linking different FP ABI variants +Modules using the default FP ABI (no floating-point) can be linked with +any other (singular) FP ABI variant. + +Special compatibility support exists for O32 with the four +double-precision FP ABI variants. The @samp{-mfpxx} FP ABI is specifically +designed to be compatible with the standard double-precision ABI and the +@samp{-mfp64} FP ABIs. This makes it desirable for O32 modules to be +built as @samp{-mfpxx} to ensure the maximum compatibility with other +modules produced for more specific needs. The only FP ABIs which cannot +be linked together are the standard double-precision ABI and the full +@samp{-mfp64} ABI with @samp{-modd-spreg}. + +@node MIPS NaN Encodings +@section Directives to record which NaN encoding is being used + +@cindex MIPS IEEE 754 NaN data encoding selection +@cindex @code{.nan} directive, MIPS +The IEEE 754 floating-point standard defines two types of not-a-number +(NaN) data: ``signalling'' NaNs and ``quiet'' NaNs. The original version +of the standard did not specify how these two types should be +distinguished. Most implementations followed the i387 model, in which +the first bit of the significand is set for quiet NaNs and clear for +signalling NaNs. However, the original MIPS implementation assigned the +opposite meaning to the bit, so that it was set for signalling NaNs and +clear for quiet NaNs. + +The 2008 revision of the standard formally suggested the i387 choice +and as from Sep 2012 the current release of the MIPS architecture +therefore optionally supports that form. Code that uses one NaN encoding +would usually be incompatible with code that uses the other NaN encoding, +so MIPS ELF objects have a flag (@code{EF_MIPS_NAN2008}) to record which +encoding is being used. + +Assembly files can use the @code{.nan} directive to select between the +two encodings. @samp{.nan 2008} says that the assembly file uses the +IEEE 754-2008 encoding while @samp{.nan legacy} says that the file uses +the original MIPS encoding. If several @code{.nan} directives are given, +the final setting is the one that is used. + +The command-line options @option{-mnan=legacy} and @option{-mnan=2008} +can be used instead of @samp{.nan legacy} and @samp{.nan 2008} +respectively. However, any @code{.nan} directive overrides the +command-line setting. + +@samp{.nan legacy} is the default if no @code{.nan} directive or +@option{-mnan} option is given. + +Note that @sc{gnu} @code{@value{AS}} does not produce NaNs itself and +therefore these directives do not affect code generation. They simply +control the setting of the @code{EF_MIPS_NAN2008} flag. + +Traditional MIPS assemblers do not support these directives. + @node MIPS Option Stack @section Directives to save and restore options @@ -804,6 +1018,14 @@ from the MCU Application Specific Extension from that point on in the assembly. The @code{.set nomcu} directive prevents MCU instructions from being accepted. +@cindex MIPS SIMD Architecture instruction generation override +@kindex @code{.set msa} +@kindex @code{.set nomsa} +The directive @code{.set msa} makes the assembler accept instructions +from the MIPS SIMD Architecture Extension from that point on +in the assembly. The @code{.set nomsa} directive prevents MSA +instructions from being accepted. + @cindex Virtualization instruction generation override @kindex @code{.set virt} @kindex @code{.set novirt} @@ -812,6 +1034,13 @@ from the Virtualization Application Specific Extension from that point on in the assembly. The @code{.set novirt} directive prevents Virtualization instructions from being accepted. +@cindex MIPS eXtended Physical Address (XPA) instruction generation override +@kindex @code{.set xpa} +@kindex @code{.set noxpa} +The directive @code{.set xpa} makes the assembler accept instructions +from the XPA Extension from that point on in the assembly. The +@code{.set noxpa} directive prevents XPA instructions from being accepted. + Traditional MIPS assemblers do not support these directives. @node MIPS Floating-Point