X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=gdb%2Faarch64-linux-nat.c;h=77d5863a56aa2bd78779827fe58a1d4ba28fb577;hb=refs%2Fheads%2Fconcurrent-displaced-stepping-2020-04-01;hp=628ffe893d2cba65e9c90c133a5f6e20d18ecd10;hpb=e53b69389a7d743fe888926475d46167e91b1157;p=deliverable%2Fbinutils-gdb.git diff --git a/gdb/aarch64-linux-nat.c b/gdb/aarch64-linux-nat.c index 628ffe893d..77d5863a56 100644 --- a/gdb/aarch64-linux-nat.c +++ b/gdb/aarch64-linux-nat.c @@ -1,6 +1,6 @@ /* Native-dependent code for GNU/Linux AArch64. - Copyright (C) 2011-2015 Free Software Foundation, Inc. + Copyright (C) 2011-2020 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GDB. @@ -30,163 +30,80 @@ #include "aarch64-tdep.h" #include "aarch64-linux-tdep.h" #include "aarch32-linux-nat.h" +#include "aarch32-tdep.h" +#include "arch/arm.h" +#include "nat/aarch64-linux.h" +#include "nat/aarch64-linux-hw-point.h" +#include "nat/aarch64-sve-linux-ptrace.h" #include "elf/external.h" #include "elf/common.h" -#include +#include "nat/gdb_ptrace.h" #include #include #include "gregset.h" +#include "linux-tdep.h" /* Defines ps_err_e, struct ps_prochandle. */ #include "gdb_proc_service.h" +#include "arch-utils.h" #ifndef TRAP_HWBKPT #define TRAP_HWBKPT 0x0004 #endif -/* On GNU/Linux, threads are implemented as pseudo-processes, in which - case we may be tracing more than one process at a time. In that - case, inferior_ptid will contain the main process ID and the - individual thread (process) ID. get_thread_id () is used to get - the thread id if it's available, and the process id otherwise. */ - -static int -get_thread_id (ptid_t ptid) +class aarch64_linux_nat_target final : public linux_nat_target { - int tid = ptid_get_lwp (ptid); - - if (0 == tid) - tid = ptid_get_pid (ptid); - return tid; -} - -/* Macro definitions, data structures, and code for the hardware - breakpoint and hardware watchpoint support follow. We use the - following abbreviations throughout the code: - - hw - hardware - bp - breakpoint - wp - watchpoint */ - -/* Maximum number of hardware breakpoint and watchpoint registers. - Neither of these values may exceed the width of dr_changed_t - measured in bits. */ - -#define AARCH64_HBP_MAX_NUM 16 -#define AARCH64_HWP_MAX_NUM 16 - -/* Alignment requirement in bytes for addresses written to - hardware breakpoint and watchpoint value registers. - - A ptrace call attempting to set an address that does not meet the - alignment criteria will fail. Limited support has been provided in - this port for unaligned watchpoints, such that from a GDB user - perspective, an unaligned watchpoint may be requested. - - This is achieved by minimally enlarging the watched area to meet the - alignment requirement, and if necessary, splitting the watchpoint - over several hardware watchpoint registers. */ - -#define AARCH64_HBP_ALIGNMENT 4 -#define AARCH64_HWP_ALIGNMENT 8 - -/* The maximum length of a memory region that can be watched by one - hardware watchpoint register. */ - -#define AARCH64_HWP_MAX_LEN_PER_REG 8 - -/* ptrace hardware breakpoint resource info is formatted as follows: - - 31 24 16 8 0 - +---------------+--------------+---------------+---------------+ - | RESERVED | RESERVED | DEBUG_ARCH | NUM_SLOTS | - +---------------+--------------+---------------+---------------+ */ - - -/* Macros to extract fields from the hardware debug information word. */ -#define AARCH64_DEBUG_NUM_SLOTS(x) ((x) & 0xff) -#define AARCH64_DEBUG_ARCH(x) (((x) >> 8) & 0xff) - -/* Macro for the expected version of the ARMv8-A debug architecture. */ -#define AARCH64_DEBUG_ARCH_V8 0x6 - -/* Number of hardware breakpoints/watchpoints the target supports. - They are initialized with values obtained via the ptrace calls - with NT_ARM_HW_BREAK and NT_ARM_HW_WATCH respectively. */ - -static int aarch64_num_bp_regs; -static int aarch64_num_wp_regs; - -/* Each bit of a variable of this type is used to indicate whether a - hardware breakpoint or watchpoint setting has been changed since - the last update. - - Bit N corresponds to the Nth hardware breakpoint or watchpoint - setting which is managed in aarch64_debug_reg_state, where N is - valid between 0 and the total number of the hardware breakpoint or - watchpoint debug registers minus 1. - - When bit N is 1, the corresponding breakpoint or watchpoint setting - has changed, and therefore the corresponding hardware debug - register needs to be updated via the ptrace interface. - - In the per-thread arch-specific data area, we define two such - variables for per-thread hardware breakpoint and watchpoint - settings respectively. - - This type is part of the mechanism which helps reduce the number of - ptrace calls to the kernel, i.e. avoid asking the kernel to write - to the debug registers with unchanged values. */ - -typedef ULONGEST dr_changed_t; - -/* Set each of the lower M bits of X to 1; assert X is wide enough. */ +public: + /* Add our register access methods. */ + void fetch_registers (struct regcache *, int) override; + void store_registers (struct regcache *, int) override; + + const struct target_desc *read_description () override; + + /* Add our hardware breakpoint and watchpoint implementation. */ + int can_use_hw_breakpoint (enum bptype, int, int) override; + int insert_hw_breakpoint (struct gdbarch *, struct bp_target_info *) override; + int remove_hw_breakpoint (struct gdbarch *, struct bp_target_info *) override; + int region_ok_for_hw_watchpoint (CORE_ADDR, int) override; + int insert_watchpoint (CORE_ADDR, int, enum target_hw_bp_type, + struct expression *) override; + int remove_watchpoint (CORE_ADDR, int, enum target_hw_bp_type, + struct expression *) override; + bool stopped_by_watchpoint () override; + bool stopped_data_address (CORE_ADDR *) override; + bool watchpoint_addr_within_range (CORE_ADDR, CORE_ADDR, int) override; + + int can_do_single_step () override; -#define DR_MARK_ALL_CHANGED(x, m) \ - do \ - { \ - gdb_assert (sizeof ((x)) * 8 >= (m)); \ - (x) = (((dr_changed_t)1 << (m)) - 1); \ - } while (0) + /* Override the GNU/Linux inferior startup hook. */ + void post_startup_inferior (ptid_t) override; -#define DR_MARK_N_CHANGED(x, n) \ - do \ - { \ - (x) |= ((dr_changed_t)1 << (n)); \ - } while (0) + /* Override the GNU/Linux post attach hook. */ + void post_attach (int pid) override; -#define DR_CLEAR_CHANGED(x) \ - do \ - { \ - (x) = 0; \ - } while (0) + /* These three defer to common nat/ code. */ + void low_new_thread (struct lwp_info *lp) override + { aarch64_linux_new_thread (lp); } + void low_delete_thread (struct arch_lwp_info *lp) override + { aarch64_linux_delete_thread (lp); } + void low_prepare_to_resume (struct lwp_info *lp) override + { aarch64_linux_prepare_to_resume (lp); } -#define DR_HAS_CHANGED(x) ((x) != 0) -#define DR_N_HAS_CHANGED(x, n) ((x) & ((dr_changed_t)1 << (n))) + void low_new_fork (struct lwp_info *parent, pid_t child_pid) override; + void low_forget_process (pid_t pid) override; -/* Structure for managing the hardware breakpoint/watchpoint resources. - DR_ADDR_* stores the address, DR_CTRL_* stores the control register - content, and DR_REF_COUNT_* counts the numbers of references to the - corresponding bp/wp, by which way the limited hardware resources - are not wasted on duplicated bp/wp settings (though so far gdb has - done a good job by not sending duplicated bp/wp requests). */ + /* Add our siginfo layout converter. */ + bool low_siginfo_fixup (siginfo_t *ptrace, gdb_byte *inf, int direction) + override; -struct aarch64_debug_reg_state -{ - /* hardware breakpoint */ - CORE_ADDR dr_addr_bp[AARCH64_HBP_MAX_NUM]; - unsigned int dr_ctrl_bp[AARCH64_HBP_MAX_NUM]; - unsigned int dr_ref_count_bp[AARCH64_HBP_MAX_NUM]; - - /* hardware watchpoint */ - CORE_ADDR dr_addr_wp[AARCH64_HWP_MAX_NUM]; - unsigned int dr_ctrl_wp[AARCH64_HWP_MAX_NUM]; - unsigned int dr_ref_count_wp[AARCH64_HWP_MAX_NUM]; + struct gdbarch *thread_architecture (ptid_t) override; }; +static aarch64_linux_nat_target the_aarch64_linux_nat_target; + /* Per-process data. We don't bind this to a per-inferior registry because of targets like x86 GNU/Linux that need to keep track of processes that aren't bound to any inferior (e.g., fork children, @@ -228,7 +145,7 @@ aarch64_add_process (pid_t pid) { struct aarch64_process_info *proc; - proc = xcalloc (1, sizeof (*proc)); + proc = XCNEW (struct aarch64_process_info); proc->pid = pid; proc->next = aarch64_process_list; @@ -255,8 +172,8 @@ aarch64_process_info_get (pid_t pid) /* Called whenever GDB is no longer debugging process PID. It deletes data structures that keep track of debug register state. */ -static void -aarch64_forget_process (pid_t pid) +void +aarch64_linux_nat_target::low_forget_process (pid_t pid) { struct aarch64_process_info *proc, **proc_link; @@ -280,181 +197,12 @@ aarch64_forget_process (pid_t pid) /* Get debug registers state for process PID. */ -static struct aarch64_debug_reg_state * +struct aarch64_debug_reg_state * aarch64_get_debug_reg_state (pid_t pid) { return &aarch64_process_info_get (pid)->state; } -/* Per-thread arch-specific data we want to keep. */ - -struct arch_lwp_info -{ - /* When bit N is 1, it indicates the Nth hardware breakpoint or - watchpoint register pair needs to be updated when the thread is - resumed; see aarch64_linux_prepare_to_resume. */ - dr_changed_t dr_changed_bp; - dr_changed_t dr_changed_wp; -}; - -/* Call ptrace to set the thread TID's hardware breakpoint/watchpoint - registers with data from *STATE. */ - -static void -aarch64_linux_set_debug_regs (const struct aarch64_debug_reg_state *state, - int tid, int watchpoint) -{ - int i, count; - struct iovec iov; - struct user_hwdebug_state regs; - const CORE_ADDR *addr; - const unsigned int *ctrl; - - memset (®s, 0, sizeof (regs)); - iov.iov_base = ®s; - count = watchpoint ? aarch64_num_wp_regs : aarch64_num_bp_regs; - addr = watchpoint ? state->dr_addr_wp : state->dr_addr_bp; - ctrl = watchpoint ? state->dr_ctrl_wp : state->dr_ctrl_bp; - if (count == 0) - return; - iov.iov_len = (offsetof (struct user_hwdebug_state, dbg_regs[count - 1]) - + sizeof (regs.dbg_regs [count - 1])); - - for (i = 0; i < count; i++) - { - regs.dbg_regs[i].addr = addr[i]; - regs.dbg_regs[i].ctrl = ctrl[i]; - } - - if (ptrace (PTRACE_SETREGSET, tid, - watchpoint ? NT_ARM_HW_WATCH : NT_ARM_HW_BREAK, - (void *) &iov)) - error (_("Unexpected error setting hardware debug registers")); -} - -struct aarch64_dr_update_callback_param -{ - int is_watchpoint; - unsigned int idx; -}; - -/* Callback for iterate_over_lwps. Records the - information about the change of one hardware breakpoint/watchpoint - setting for the thread LWP. - The information is passed in via PTR. - N.B. The actual updating of hardware debug registers is not - carried out until the moment the thread is resumed. */ - -static int -debug_reg_change_callback (struct lwp_info *lwp, void *ptr) -{ - struct aarch64_dr_update_callback_param *param_p - = (struct aarch64_dr_update_callback_param *) ptr; - int pid = get_thread_id (lwp->ptid); - int idx = param_p->idx; - int is_watchpoint = param_p->is_watchpoint; - struct arch_lwp_info *info = lwp->arch_private; - dr_changed_t *dr_changed_ptr; - dr_changed_t dr_changed; - - if (info == NULL) - info = lwp->arch_private = XCNEW (struct arch_lwp_info); - - if (show_debug_regs) - { - fprintf_unfiltered (gdb_stdlog, - "debug_reg_change_callback: \n\tOn entry:\n"); - fprintf_unfiltered (gdb_stdlog, - "\tpid%d, dr_changed_bp=0x%s, " - "dr_changed_wp=0x%s\n", - pid, phex (info->dr_changed_bp, 8), - phex (info->dr_changed_wp, 8)); - } - - dr_changed_ptr = is_watchpoint ? &info->dr_changed_wp - : &info->dr_changed_bp; - dr_changed = *dr_changed_ptr; - - gdb_assert (idx >= 0 - && (idx <= (is_watchpoint ? aarch64_num_wp_regs - : aarch64_num_bp_regs))); - - /* The actual update is done later just before resuming the lwp, - we just mark that one register pair needs updating. */ - DR_MARK_N_CHANGED (dr_changed, idx); - *dr_changed_ptr = dr_changed; - - /* If the lwp isn't stopped, force it to momentarily pause, so - we can update its debug registers. */ - if (!lwp->stopped) - linux_stop_lwp (lwp); - - if (show_debug_regs) - { - fprintf_unfiltered (gdb_stdlog, - "\tOn exit:\n\tpid%d, dr_changed_bp=0x%s, " - "dr_changed_wp=0x%s\n", - pid, phex (info->dr_changed_bp, 8), - phex (info->dr_changed_wp, 8)); - } - - /* Continue the iteration. */ - return 0; -} - -/* Notify each thread that their IDXth breakpoint/watchpoint register - pair needs to be updated. The message will be recorded in each - thread's arch-specific data area, the actual updating will be done - when the thread is resumed. */ - -static void -aarch64_notify_debug_reg_change (const struct aarch64_debug_reg_state *state, - int is_watchpoint, unsigned int idx) -{ - struct aarch64_dr_update_callback_param param; - ptid_t pid_ptid = pid_to_ptid (ptid_get_pid (inferior_ptid)); - - param.is_watchpoint = is_watchpoint; - param.idx = idx; - - iterate_over_lwps (pid_ptid, debug_reg_change_callback, (void *) ¶m); -} - -/* Print the values of the cached breakpoint/watchpoint registers. */ - -static void -aarch64_show_debug_reg_state (struct aarch64_debug_reg_state *state, - const char *func, CORE_ADDR addr, - int len, int type) -{ - int i; - - fprintf_unfiltered (gdb_stdlog, "%s", func); - if (addr || len) - fprintf_unfiltered (gdb_stdlog, " (addr=0x%08lx, len=%d, type=%s)", - (unsigned long) addr, len, - type == hw_write ? "hw-write-watchpoint" - : (type == hw_read ? "hw-read-watchpoint" - : (type == hw_access ? "hw-access-watchpoint" - : (type == hw_execute ? "hw-breakpoint" - : "??unknown??")))); - fprintf_unfiltered (gdb_stdlog, ":\n"); - - fprintf_unfiltered (gdb_stdlog, "\tBREAKPOINTs:\n"); - for (i = 0; i < aarch64_num_bp_regs; i++) - fprintf_unfiltered (gdb_stdlog, - "\tBP%d: addr=0x%08lx, ctrl=0x%08x, ref.count=%d\n", - i, state->dr_addr_bp[i], - state->dr_ctrl_bp[i], state->dr_ref_count_bp[i]); - - fprintf_unfiltered (gdb_stdlog, "\tWATCHPOINTs:\n"); - for (i = 0; i < aarch64_num_wp_regs; i++) - fprintf_unfiltered (gdb_stdlog, - "\tWP%d: addr=0x%08lx, ctrl=0x%08x, ref.count=%d\n", - i, state->dr_addr_wp[i], - state->dr_ctrl_wp[i], state->dr_ref_count_wp[i]); -} - /* Fill GDB's register array with the general-purpose register values from the current thread. */ @@ -462,7 +210,7 @@ static void fetch_gregs_from_thread (struct regcache *regcache) { int ret, tid; - struct gdbarch *gdbarch = get_regcache_arch (regcache); + struct gdbarch *gdbarch = regcache->arch (); elf_gregset_t regs; struct iovec iovec; @@ -470,7 +218,7 @@ fetch_gregs_from_thread (struct regcache *regcache) and arm. */ gdb_static_assert (sizeof (regs) >= 18 * 4); - tid = get_thread_id (inferior_ptid); + tid = regcache->ptid ().lwp (); iovec.iov_base = ®s; if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) @@ -489,7 +237,7 @@ fetch_gregs_from_thread (struct regcache *regcache) int regno; for (regno = AARCH64_X0_REGNUM; regno <= AARCH64_CPSR_REGNUM; regno++) - regcache_raw_supply (regcache, regno, ®s[regno - AARCH64_X0_REGNUM]); + regcache->raw_supply (regno, ®s[regno - AARCH64_X0_REGNUM]); } } @@ -502,12 +250,12 @@ store_gregs_to_thread (const struct regcache *regcache) int ret, tid; elf_gregset_t regs; struct iovec iovec; - struct gdbarch *gdbarch = get_regcache_arch (regcache); + struct gdbarch *gdbarch = regcache->arch (); /* Make sure REGS can hold all registers contents on both aarch64 and arm. */ gdb_static_assert (sizeof (regs) >= 18 * 4); - tid = get_thread_id (inferior_ptid); + tid = regcache->ptid ().lwp (); iovec.iov_base = ®s; if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) @@ -526,9 +274,8 @@ store_gregs_to_thread (const struct regcache *regcache) int regno; for (regno = AARCH64_X0_REGNUM; regno <= AARCH64_CPSR_REGNUM; regno++) - if (REG_VALID == regcache_register_status (regcache, regno)) - regcache_raw_collect (regcache, regno, - ®s[regno - AARCH64_X0_REGNUM]); + if (REG_VALID == regcache->get_register_status (regno)) + regcache->raw_collect (regno, ®s[regno - AARCH64_X0_REGNUM]); } ret = ptrace (PTRACE_SETREGSET, tid, NT_PRSTATUS, &iovec); @@ -545,19 +292,19 @@ fetch_fpregs_from_thread (struct regcache *regcache) int ret, tid; elf_fpregset_t regs; struct iovec iovec; - struct gdbarch *gdbarch = get_regcache_arch (regcache); + struct gdbarch *gdbarch = regcache->arch (); /* Make sure REGS can hold all VFP registers contents on both aarch64 and arm. */ - gdb_static_assert (sizeof regs >= VFP_REGS_SIZE); + gdb_static_assert (sizeof regs >= ARM_VFP3_REGS_SIZE); - tid = get_thread_id (inferior_ptid); + tid = regcache->ptid ().lwp (); iovec.iov_base = ®s; if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) { - iovec.iov_len = VFP_REGS_SIZE; + iovec.iov_len = ARM_VFP3_REGS_SIZE; ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec); if (ret < 0) @@ -576,11 +323,10 @@ fetch_fpregs_from_thread (struct regcache *regcache) perror_with_name (_("Unable to fetch vFP/SIMD registers.")); for (regno = AARCH64_V0_REGNUM; regno <= AARCH64_V31_REGNUM; regno++) - regcache_raw_supply (regcache, regno, - ®s.vregs[regno - AARCH64_V0_REGNUM]); + regcache->raw_supply (regno, ®s.vregs[regno - AARCH64_V0_REGNUM]); - regcache_raw_supply (regcache, AARCH64_FPSR_REGNUM, ®s.fpsr); - regcache_raw_supply (regcache, AARCH64_FPCR_REGNUM, ®s.fpcr); + regcache->raw_supply (AARCH64_FPSR_REGNUM, ®s.fpsr); + regcache->raw_supply (AARCH64_FPCR_REGNUM, ®s.fpcr); } } @@ -593,18 +339,18 @@ store_fpregs_to_thread (const struct regcache *regcache) int ret, tid; elf_fpregset_t regs; struct iovec iovec; - struct gdbarch *gdbarch = get_regcache_arch (regcache); + struct gdbarch *gdbarch = regcache->arch (); /* Make sure REGS can hold all VFP registers contents on both aarch64 and arm. */ - gdb_static_assert (sizeof regs >= VFP_REGS_SIZE); - tid = get_thread_id (inferior_ptid); + gdb_static_assert (sizeof regs >= ARM_VFP3_REGS_SIZE); + tid = regcache->ptid ().lwp (); iovec.iov_base = ®s; if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) { - iovec.iov_len = VFP_REGS_SIZE; + iovec.iov_len = ARM_VFP3_REGS_SIZE; ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec); if (ret < 0) @@ -623,16 +369,14 @@ store_fpregs_to_thread (const struct regcache *regcache) perror_with_name (_("Unable to fetch FP/SIMD registers.")); for (regno = AARCH64_V0_REGNUM; regno <= AARCH64_V31_REGNUM; regno++) - if (REG_VALID == regcache_register_status (regcache, regno)) - regcache_raw_collect (regcache, regno, - (char *) ®s.vregs[regno - AARCH64_V0_REGNUM]); - - if (REG_VALID == regcache_register_status (regcache, AARCH64_FPSR_REGNUM)) - regcache_raw_collect (regcache, AARCH64_FPSR_REGNUM, - (char *) ®s.fpsr); - if (REG_VALID == regcache_register_status (regcache, AARCH64_FPCR_REGNUM)) - regcache_raw_collect (regcache, AARCH64_FPCR_REGNUM, - (char *) ®s.fpcr); + if (REG_VALID == regcache->get_register_status (regno)) + regcache->raw_collect + (regno, (char *) ®s.vregs[regno - AARCH64_V0_REGNUM]); + + if (REG_VALID == regcache->get_register_status (AARCH64_FPSR_REGNUM)) + regcache->raw_collect (AARCH64_FPSR_REGNUM, (char *) ®s.fpsr); + if (REG_VALID == regcache->get_register_status (AARCH64_FPCR_REGNUM)) + regcache->raw_collect (AARCH64_FPCR_REGNUM, (char *) ®s.fpcr); } if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) @@ -649,38 +393,126 @@ store_fpregs_to_thread (const struct regcache *regcache) } } -/* Implement the "to_fetch_register" target_ops method. */ +/* Fill GDB's register array with the sve register values + from the current thread. */ + +static void +fetch_sveregs_from_thread (struct regcache *regcache) +{ + std::unique_ptr base + = aarch64_sve_get_sveregs (regcache->ptid ().lwp ()); + aarch64_sve_regs_copy_to_reg_buf (regcache, base.get ()); +} + +/* Store to the current thread the valid sve register + values in the GDB's register array. */ + +static void +store_sveregs_to_thread (struct regcache *regcache) +{ + int ret; + struct iovec iovec; + int tid = regcache->ptid ().lwp (); + + /* First store vector length to the thread. This is done first to ensure the + ptrace buffers read from the kernel are the correct size. */ + if (!aarch64_sve_set_vq (tid, regcache)) + perror_with_name (_("Unable to set VG register.")); + + /* Obtain a dump of SVE registers from ptrace. */ + std::unique_ptr base = aarch64_sve_get_sveregs (tid); + + /* Overwrite with regcache state. */ + aarch64_sve_regs_copy_from_reg_buf (regcache, base.get ()); + + /* Write back to the kernel. */ + iovec.iov_base = base.get (); + iovec.iov_len = ((struct user_sve_header *) base.get ())->size; + ret = ptrace (PTRACE_SETREGSET, tid, NT_ARM_SVE, &iovec); + + if (ret < 0) + perror_with_name (_("Unable to store sve registers")); +} + +/* Fill GDB's register array with the pointer authentication mask values from + the current thread. */ static void -aarch64_linux_fetch_inferior_registers (struct target_ops *ops, - struct regcache *regcache, - int regno) +fetch_pauth_masks_from_thread (struct regcache *regcache) +{ + struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ()); + int ret; + struct iovec iovec; + uint64_t pauth_regset[2] = {0, 0}; + int tid = regcache->ptid ().lwp (); + + iovec.iov_base = &pauth_regset; + iovec.iov_len = sizeof (pauth_regset); + + ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_PAC_MASK, &iovec); + if (ret != 0) + perror_with_name (_("unable to fetch pauth registers.")); + + regcache->raw_supply (AARCH64_PAUTH_DMASK_REGNUM (tdep->pauth_reg_base), + &pauth_regset[0]); + regcache->raw_supply (AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base), + &pauth_regset[1]); +} + +/* Implement the "fetch_registers" target_ops method. */ + +void +aarch64_linux_nat_target::fetch_registers (struct regcache *regcache, + int regno) { + struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ()); + if (regno == -1) { fetch_gregs_from_thread (regcache); - fetch_fpregs_from_thread (regcache); + if (tdep->has_sve ()) + fetch_sveregs_from_thread (regcache); + else + fetch_fpregs_from_thread (regcache); + + if (tdep->has_pauth ()) + fetch_pauth_masks_from_thread (regcache); } else if (regno < AARCH64_V0_REGNUM) fetch_gregs_from_thread (regcache); + else if (tdep->has_sve ()) + fetch_sveregs_from_thread (regcache); else fetch_fpregs_from_thread (regcache); + + if (tdep->has_pauth ()) + { + if (regno == AARCH64_PAUTH_DMASK_REGNUM (tdep->pauth_reg_base) + || regno == AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base)) + fetch_pauth_masks_from_thread (regcache); + } } -/* Implement the "to_store_register" target_ops method. */ +/* Implement the "store_registers" target_ops method. */ -static void -aarch64_linux_store_inferior_registers (struct target_ops *ops, - struct regcache *regcache, - int regno) +void +aarch64_linux_nat_target::store_registers (struct regcache *regcache, + int regno) { + struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ()); + if (regno == -1) { store_gregs_to_thread (regcache); - store_fpregs_to_thread (regcache); + if (tdep->has_sve ()) + store_sveregs_to_thread (regcache); + else + store_fpregs_to_thread (regcache); } else if (regno < AARCH64_V0_REGNUM) store_gregs_to_thread (regcache); + else if (tdep->has_sve ()) + store_sveregs_to_thread (regcache); else store_fpregs_to_thread (regcache); } @@ -733,63 +565,11 @@ supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp) AARCH64_LINUX_SIZEOF_FPREGSET); } -/* Called when resuming a thread. - The hardware debug registers are updated when there is any change. */ - -static void -aarch64_linux_prepare_to_resume (struct lwp_info *lwp) -{ - struct arch_lwp_info *info = lwp->arch_private; - - /* NULL means this is the main thread still going through the shell, - or, no watchpoint has been set yet. In that case, there's - nothing to do. */ - if (info == NULL) - return; - - if (DR_HAS_CHANGED (info->dr_changed_bp) - || DR_HAS_CHANGED (info->dr_changed_wp)) - { - int tid = ptid_get_lwp (lwp->ptid); - struct aarch64_debug_reg_state *state - = aarch64_get_debug_reg_state (ptid_get_pid (lwp->ptid)); - - if (show_debug_regs) - fprintf_unfiltered (gdb_stdlog, "prepare_to_resume thread %d\n", tid); - - /* Watchpoints. */ - if (DR_HAS_CHANGED (info->dr_changed_wp)) - { - aarch64_linux_set_debug_regs (state, tid, 1); - DR_CLEAR_CHANGED (info->dr_changed_wp); - } - - /* Breakpoints. */ - if (DR_HAS_CHANGED (info->dr_changed_bp)) - { - aarch64_linux_set_debug_regs (state, tid, 0); - DR_CLEAR_CHANGED (info->dr_changed_bp); - } - } -} - -static void -aarch64_linux_new_thread (struct lwp_info *lp) -{ - struct arch_lwp_info *info = XCNEW (struct arch_lwp_info); - - /* Mark that all the hardware breakpoint/watchpoint register pairs - for this thread need to be initialized. */ - DR_MARK_ALL_CHANGED (info->dr_changed_bp, aarch64_num_bp_regs); - DR_MARK_ALL_CHANGED (info->dr_changed_wp, aarch64_num_wp_regs); - - lp->arch_private = info; -} - /* linux_nat_new_fork hook. */ -static void -aarch64_linux_new_fork (struct lwp_info *parent, pid_t child_pid) +void +aarch64_linux_nat_target::low_new_fork (struct lwp_info *parent, + pid_t child_pid) { pid_t parent_pid; struct aarch64_debug_reg_state *parent_state; @@ -806,7 +586,7 @@ aarch64_linux_new_fork (struct lwp_info *parent, pid_t child_pid) new process so that all breakpoints and watchpoints can be removed together. */ - parent_pid = ptid_get_pid (parent->ptid); + parent_pid = parent->ptid.pid (); parent_state = aarch64_get_debug_reg_state (parent_pid); child_state = aarch64_get_debug_reg_state (child_pid); *child_state = *parent_state; @@ -817,219 +597,92 @@ aarch64_linux_new_fork (struct lwp_info *parent, pid_t child_pid) storage (or its descriptor). */ ps_err_e -ps_get_thread_area (const struct ps_prochandle *ph, +ps_get_thread_area (struct ps_prochandle *ph, lwpid_t lwpid, int idx, void **base) { - struct iovec iovec; - uint64_t reg; + int is_64bit_p + = (gdbarch_bfd_arch_info (target_gdbarch ())->bits_per_word == 64); - iovec.iov_base = ® - iovec.iov_len = sizeof (reg); - - if (ptrace (PTRACE_GETREGSET, lwpid, NT_ARM_TLS, &iovec) != 0) - return PS_ERR; - - /* IDX is the bias from the thread pointer to the beginning of the - thread descriptor. It has to be subtracted due to implementation - quirks in libthread_db. */ - *base = (void *) (reg - idx); - - return PS_OK; + return aarch64_ps_get_thread_area (ph, lwpid, idx, base, is_64bit_p); } -/* Get the hardware debug register capacity information from the - inferior represented by PTID. */ +/* Implement the "post_startup_inferior" target_ops method. */ -static void -aarch64_linux_get_debug_reg_capacity (ptid_t ptid) +void +aarch64_linux_nat_target::post_startup_inferior (ptid_t ptid) { - int tid; - struct iovec iov; - struct user_hwdebug_state dreg_state; - - tid = ptid_get_pid (ptid); - iov.iov_base = &dreg_state; - iov.iov_len = sizeof (dreg_state); - - /* Get hardware watchpoint register info. */ - if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_HW_WATCH, &iov) == 0 - && AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8) - { - aarch64_num_wp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info); - if (aarch64_num_wp_regs > AARCH64_HWP_MAX_NUM) - { - warning (_("Unexpected number of hardware watchpoint registers" - " reported by ptrace, got %d, expected %d."), - aarch64_num_wp_regs, AARCH64_HWP_MAX_NUM); - aarch64_num_wp_regs = AARCH64_HWP_MAX_NUM; - } - } - else - { - warning (_("Unable to determine the number of hardware watchpoints" - " available.")); - aarch64_num_wp_regs = 0; - } - - /* Get hardware breakpoint register info. */ - if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_HW_BREAK, &iov) == 0 - && AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8) - { - aarch64_num_bp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info); - if (aarch64_num_bp_regs > AARCH64_HBP_MAX_NUM) - { - warning (_("Unexpected number of hardware breakpoint registers" - " reported by ptrace, got %d, expected %d."), - aarch64_num_bp_regs, AARCH64_HBP_MAX_NUM); - aarch64_num_bp_regs = AARCH64_HBP_MAX_NUM; - } - } - else - { - warning (_("Unable to determine the number of hardware breakpoints" - " available.")); - aarch64_num_bp_regs = 0; - } + low_forget_process (ptid.pid ()); + aarch64_linux_get_debug_reg_capacity (ptid.pid ()); + linux_nat_target::post_startup_inferior (ptid); } -static void (*super_post_startup_inferior) (struct target_ops *self, - ptid_t ptid); - -/* Implement the "to_post_startup_inferior" target_ops method. */ +/* Implement the "post_attach" target_ops method. */ -static void -aarch64_linux_child_post_startup_inferior (struct target_ops *self, - ptid_t ptid) +void +aarch64_linux_nat_target::post_attach (int pid) { - aarch64_forget_process (ptid_get_pid (ptid)); - aarch64_linux_get_debug_reg_capacity (ptid); - super_post_startup_inferior (self, ptid); + low_forget_process (pid); + /* Set the hardware debug register capacity. If + aarch64_linux_get_debug_reg_capacity is not called + (as it is in aarch64_linux_child_post_startup_inferior) then + software watchpoints will be used instead of hardware + watchpoints when attaching to a target. */ + aarch64_linux_get_debug_reg_capacity (pid); + linux_nat_target::post_attach (pid); } -extern struct target_desc *tdesc_arm_with_vfpv3; -extern struct target_desc *tdesc_arm_with_neon; - -/* Implement the "to_read_description" target_ops method. */ +/* Implement the "read_description" target_ops method. */ -static const struct target_desc * -aarch64_linux_read_description (struct target_ops *ops) +const struct target_desc * +aarch64_linux_nat_target::read_description () { - CORE_ADDR at_phent; - - if (target_auxv_search (ops, AT_PHENT, &at_phent) == 1) - { - if (at_phent == sizeof (Elf64_External_Phdr)) - return tdesc_aarch64; - else - { - CORE_ADDR arm_hwcap = 0; - - if (target_auxv_search (ops, AT_HWCAP, &arm_hwcap) != 1) - return ops->beneath->to_read_description (ops->beneath); - -#ifndef COMPAT_HWCAP_VFP -#define COMPAT_HWCAP_VFP (1 << 6) -#endif -#ifndef COMPAT_HWCAP_NEON -#define COMPAT_HWCAP_NEON (1 << 12) -#endif -#ifndef COMPAT_HWCAP_VFPv3 -#define COMPAT_HWCAP_VFPv3 (1 << 13) -#endif + int ret, tid; + gdb_byte regbuf[ARM_VFP3_REGS_SIZE]; + struct iovec iovec; - if (arm_hwcap & COMPAT_HWCAP_VFP) - { - char *buf; - const struct target_desc *result = NULL; + tid = inferior_ptid.lwp (); - if (arm_hwcap & COMPAT_HWCAP_NEON) - result = tdesc_arm_with_neon; - else if (arm_hwcap & COMPAT_HWCAP_VFPv3) - result = tdesc_arm_with_vfpv3; + iovec.iov_base = regbuf; + iovec.iov_len = ARM_VFP3_REGS_SIZE; - return result; - } + ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec); + if (ret == 0) + return aarch32_read_description (); - return NULL; - } - } + CORE_ADDR hwcap = linux_get_hwcap (this); - return tdesc_aarch64; + return aarch64_read_description (aarch64_sve_get_vq (tid), + hwcap & AARCH64_HWCAP_PACA); } -/* Given the (potentially unaligned) watchpoint address in ADDR and - length in LEN, return the aligned address and aligned length in - *ALIGNED_ADDR_P and *ALIGNED_LEN_P, respectively. The returned - aligned address and length will be valid values to write to the - hardware watchpoint value and control registers. +/* Convert a native/host siginfo object, into/from the siginfo in the + layout of the inferiors' architecture. Returns true if any + conversion was done; false otherwise. If DIRECTION is 1, then copy + from INF to NATIVE. If DIRECTION is 0, copy from NATIVE to + INF. */ - The given watchpoint may get truncated if more than one hardware - register is needed to cover the watched region. *NEXT_ADDR_P - and *NEXT_LEN_P, if non-NULL, will return the address and length - of the remaining part of the watchpoint (which can be processed - by calling this routine again to generate another aligned address - and length pair. - - See the comment above the function of the same name in - gdbserver/linux-aarch64-low.c for more information. */ - -static void -aarch64_align_watchpoint (CORE_ADDR addr, int len, CORE_ADDR *aligned_addr_p, - int *aligned_len_p, CORE_ADDR *next_addr_p, - int *next_len_p) +bool +aarch64_linux_nat_target::low_siginfo_fixup (siginfo_t *native, gdb_byte *inf, + int direction) { - int aligned_len; - unsigned int offset; - CORE_ADDR aligned_addr; - const unsigned int alignment = AARCH64_HWP_ALIGNMENT; - const unsigned int max_wp_len = AARCH64_HWP_MAX_LEN_PER_REG; - - /* As assumed by the algorithm. */ - gdb_assert (alignment == max_wp_len); - - if (len <= 0) - return; - - /* Address to be put into the hardware watchpoint value register - must be aligned. */ - offset = addr & (alignment - 1); - aligned_addr = addr - offset; - - gdb_assert (offset >= 0 && offset < alignment); - gdb_assert (aligned_addr >= 0 && aligned_addr <= addr); - gdb_assert (offset + len > 0); + struct gdbarch *gdbarch = get_frame_arch (get_current_frame ()); - if (offset + len >= max_wp_len) - { - /* Need more than one watchpoint registers; truncate it at the - alignment boundary. */ - aligned_len = max_wp_len; - len -= (max_wp_len - offset); - addr += (max_wp_len - offset); - gdb_assert ((addr & (alignment - 1)) == 0); - } - else + /* Is the inferior 32-bit? If so, then do fixup the siginfo + object. */ + if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) { - /* Find the smallest valid length that is large enough to - accommodate this watchpoint. */ - static const unsigned char - aligned_len_array[AARCH64_HWP_MAX_LEN_PER_REG] = - { 1, 2, 4, 4, 8, 8, 8, 8 }; - - aligned_len = aligned_len_array[offset + len - 1]; - addr += len; - len = 0; + if (direction == 0) + aarch64_compat_siginfo_from_siginfo ((struct compat_siginfo *) inf, + native); + else + aarch64_siginfo_from_compat_siginfo (native, + (struct compat_siginfo *) inf); + + return true; } - if (aligned_addr_p) - *aligned_addr_p = aligned_addr; - if (aligned_len_p) - *aligned_len_p = aligned_len; - if (next_addr_p) - *next_addr_p = addr; - if (next_len_p) - *next_len_p = len; + return false; } /* Returns the number of hardware watchpoints of type TYPE that we can @@ -1040,285 +693,50 @@ aarch64_align_watchpoint (CORE_ADDR addr, int len, CORE_ADDR *aligned_addr_p, bp_read_watchpoint, bp_write_watchpoint, or bp_hardware_breakpoint. CNT is the number of such watchpoints used so far (including this one). OTHERTYPE is non-zero if other types of watchpoints are - currently enabled. - - We always return 1 here because we don't have enough information - about possible overlap of addresses that they want to watch. As an - extreme example, consider the case where all the watchpoints watch - the same address and the same region length: then we can handle a - virtually unlimited number of watchpoints, due to debug register - sharing implemented via reference counts. */ - -static int -aarch64_linux_can_use_hw_breakpoint (struct target_ops *self, - int type, int cnt, int othertype) -{ - return 1; -} - -/* ptrace expects control registers to be formatted as follows: + currently enabled. */ - 31 13 5 3 1 0 - +--------------------------------+----------+------+------+----+ - | RESERVED (SBZ) | LENGTH | TYPE | PRIV | EN | - +--------------------------------+----------+------+------+----+ - - The TYPE field is ignored for breakpoints. */ - -#define DR_CONTROL_ENABLED(ctrl) (((ctrl) & 0x1) == 1) -#define DR_CONTROL_LENGTH(ctrl) (((ctrl) >> 5) & 0xff) - -/* Utility function that returns the length in bytes of a watchpoint - according to the content of a hardware debug control register CTRL. - Note that the kernel currently only supports the following Byte - Address Select (BAS) values: 0x1, 0x3, 0xf and 0xff, which means - that for a hardware watchpoint, its valid length can only be 1 - byte, 2 bytes, 4 bytes or 8 bytes. */ - -static inline unsigned int -aarch64_watchpoint_length (unsigned int ctrl) +int +aarch64_linux_nat_target::can_use_hw_breakpoint (enum bptype type, + int cnt, int othertype) { - switch (DR_CONTROL_LENGTH (ctrl)) + if (type == bp_hardware_watchpoint || type == bp_read_watchpoint + || type == bp_access_watchpoint || type == bp_watchpoint) { - case 0x01: - return 1; - case 0x03: - return 2; - case 0x0f: - return 4; - case 0xff: - return 8; - default: - return 0; + if (aarch64_num_wp_regs == 0) + return 0; } -} - -/* Given the hardware breakpoint or watchpoint type TYPE and its - length LEN, return the expected encoding for a hardware - breakpoint/watchpoint control register. */ - -static unsigned int -aarch64_point_encode_ctrl_reg (int type, int len) -{ - unsigned int ctrl, ttype; - - /* type */ - switch (type) + else if (type == bp_hardware_breakpoint) { - case hw_write: - ttype = 2; - break; - case hw_read: - ttype = 1; - break; - case hw_access: - ttype = 3; - break; - case hw_execute: - ttype = 0; - break; - default: - perror_with_name (_("Unrecognized breakpoint/watchpoint type")); - } - ctrl = ttype << 3; - - /* length bitmask */ - ctrl |= ((1 << len) - 1) << 5; - /* enabled at el0 */ - ctrl |= (2 << 1) | 1; - - return ctrl; -} - -/* Addresses to be written to the hardware breakpoint and watchpoint - value registers need to be aligned; the alignment is 4-byte and - 8-type respectively. Linux kernel rejects any non-aligned address - it receives from the related ptrace call. Furthermore, the kernel - currently only supports the following Byte Address Select (BAS) - values: 0x1, 0x3, 0xf and 0xff, which means that for a hardware - watchpoint to be accepted by the kernel (via ptrace call), its - valid length can only be 1 byte, 2 bytes, 4 bytes or 8 bytes. - Despite these limitations, the unaligned watchpoint is supported in - this port. - - Return 0 for any non-compliant ADDR and/or LEN; return 1 otherwise. */ - -static int -aarch64_point_is_aligned (int is_watchpoint, CORE_ADDR addr, int len) -{ - unsigned int alignment = is_watchpoint ? AARCH64_HWP_ALIGNMENT - : AARCH64_HBP_ALIGNMENT; - - if (addr & (alignment - 1)) - return 0; - - if (len != 8 && len != 4 && len != 2 && len != 1) - return 0; - - return 1; -} - -/* Record the insertion of one breakpoint/watchpoint, as represented - by ADDR and CTRL, in the cached debug register state area *STATE. */ - -static int -aarch64_dr_state_insert_one_point (struct aarch64_debug_reg_state *state, - int type, CORE_ADDR addr, int len) -{ - int i, idx, num_regs, is_watchpoint; - unsigned int ctrl, *dr_ctrl_p, *dr_ref_count; - CORE_ADDR *dr_addr_p; - - /* Set up state pointers. */ - is_watchpoint = (type != hw_execute); - gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len)); - if (is_watchpoint) - { - num_regs = aarch64_num_wp_regs; - dr_addr_p = state->dr_addr_wp; - dr_ctrl_p = state->dr_ctrl_wp; - dr_ref_count = state->dr_ref_count_wp; - } - else - { - num_regs = aarch64_num_bp_regs; - dr_addr_p = state->dr_addr_bp; - dr_ctrl_p = state->dr_ctrl_bp; - dr_ref_count = state->dr_ref_count_bp; - } - - ctrl = aarch64_point_encode_ctrl_reg (type, len); - - /* Find an existing or free register in our cache. */ - idx = -1; - for (i = 0; i < num_regs; ++i) - { - if ((dr_ctrl_p[i] & 1) == 0) - { - gdb_assert (dr_ref_count[i] == 0); - idx = i; - /* no break; continue hunting for an existing one. */ - } - else if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl) - { - gdb_assert (dr_ref_count[i] != 0); - idx = i; - break; - } - } - - /* No space. */ - if (idx == -1) - return -1; - - /* Update our cache. */ - if ((dr_ctrl_p[idx] & 1) == 0) - { - /* new entry */ - dr_addr_p[idx] = addr; - dr_ctrl_p[idx] = ctrl; - dr_ref_count[idx] = 1; - /* Notify the change. */ - aarch64_notify_debug_reg_change (state, is_watchpoint, idx); + if (aarch64_num_bp_regs == 0) + return 0; } else - { - /* existing entry */ - dr_ref_count[idx]++; - } - - return 0; -} - -/* Record the removal of one breakpoint/watchpoint, as represented by - ADDR and CTRL, in the cached debug register state area *STATE. */ - -static int -aarch64_dr_state_remove_one_point (struct aarch64_debug_reg_state *state, - int type, CORE_ADDR addr, int len) -{ - int i, num_regs, is_watchpoint; - unsigned int ctrl, *dr_ctrl_p, *dr_ref_count; - CORE_ADDR *dr_addr_p; - - /* Set up state pointers. */ - is_watchpoint = (type != hw_execute); - gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len)); - if (is_watchpoint) - { - num_regs = aarch64_num_wp_regs; - dr_addr_p = state->dr_addr_wp; - dr_ctrl_p = state->dr_ctrl_wp; - dr_ref_count = state->dr_ref_count_wp; - } - else - { - num_regs = aarch64_num_bp_regs; - dr_addr_p = state->dr_addr_bp; - dr_ctrl_p = state->dr_ctrl_bp; - dr_ref_count = state->dr_ref_count_bp; - } - - ctrl = aarch64_point_encode_ctrl_reg (type, len); - - /* Find the entry that matches the ADDR and CTRL. */ - for (i = 0; i < num_regs; ++i) - if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl) - { - gdb_assert (dr_ref_count[i] != 0); - break; - } - - /* Not found. */ - if (i == num_regs) - return -1; - - /* Clear our cache. */ - if (--dr_ref_count[i] == 0) - { - /* Clear the enable bit. */ - ctrl &= ~1; - dr_addr_p[i] = 0; - dr_ctrl_p[i] = ctrl; - /* Notify the change. */ - aarch64_notify_debug_reg_change (state, is_watchpoint, i); - } - - return 0; -} - -/* Implement insertion and removal of a single breakpoint. */ - -static int -aarch64_handle_breakpoint (int type, CORE_ADDR addr, int len, int is_insert) -{ - struct aarch64_debug_reg_state *state; - - /* The hardware breakpoint on AArch64 should always be 4-byte - aligned. */ - if (!aarch64_point_is_aligned (0 /* is_watchpoint */ , addr, len)) - return -1; - - state = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid)); - - if (is_insert) - return aarch64_dr_state_insert_one_point (state, type, addr, len); - else - return aarch64_dr_state_remove_one_point (state, type, addr, len); + gdb_assert_not_reached ("unexpected breakpoint type"); + + /* We always return 1 here because we don't have enough information + about possible overlap of addresses that they want to watch. As an + extreme example, consider the case where all the watchpoints watch + the same address and the same region length: then we can handle a + virtually unlimited number of watchpoints, due to debug register + sharing implemented via reference counts. */ + return 1; } /* Insert a hardware-assisted breakpoint at BP_TGT->reqstd_address. Return 0 on success, -1 on failure. */ -static int -aarch64_linux_insert_hw_breakpoint (struct target_ops *self, - struct gdbarch *gdbarch, - struct bp_target_info *bp_tgt) +int +aarch64_linux_nat_target::insert_hw_breakpoint (struct gdbarch *gdbarch, + struct bp_target_info *bp_tgt) { int ret; CORE_ADDR addr = bp_tgt->placed_address = bp_tgt->reqstd_address; - const int len = 4; - const int type = hw_execute; + int len; + const enum target_hw_bp_type type = hw_execute; + struct aarch64_debug_reg_state *state + = aarch64_get_debug_reg_state (inferior_ptid.pid ()); + + gdbarch_breakpoint_from_pc (gdbarch, &addr, &len); if (show_debug_regs) fprintf_unfiltered @@ -1326,13 +744,10 @@ aarch64_linux_insert_hw_breakpoint (struct target_ops *self, "insert_hw_breakpoint on entry (addr=0x%08lx, len=%d))\n", (unsigned long) addr, len); - ret = aarch64_handle_breakpoint (type, addr, len, 1 /* is_insert */); + ret = aarch64_handle_breakpoint (type, addr, len, 1 /* is_insert */, state); if (show_debug_regs) { - struct aarch64_debug_reg_state *state - = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid)); - aarch64_show_debug_reg_state (state, "insert_hw_breakpoint", addr, len, type); } @@ -1343,28 +758,28 @@ aarch64_linux_insert_hw_breakpoint (struct target_ops *self, /* Remove a hardware-assisted breakpoint at BP_TGT->placed_address. Return 0 on success, -1 on failure. */ -static int -aarch64_linux_remove_hw_breakpoint (struct target_ops *self, - struct gdbarch *gdbarch, - struct bp_target_info *bp_tgt) +int +aarch64_linux_nat_target::remove_hw_breakpoint (struct gdbarch *gdbarch, + struct bp_target_info *bp_tgt) { int ret; CORE_ADDR addr = bp_tgt->placed_address; - const int len = 4; - const int type = hw_execute; + int len = 4; + const enum target_hw_bp_type type = hw_execute; + struct aarch64_debug_reg_state *state + = aarch64_get_debug_reg_state (inferior_ptid.pid ()); + + gdbarch_breakpoint_from_pc (gdbarch, &addr, &len); if (show_debug_regs) fprintf_unfiltered (gdb_stdlog, "remove_hw_breakpoint on entry (addr=0x%08lx, len=%d))\n", (unsigned long) addr, len); - ret = aarch64_handle_breakpoint (type, addr, len, 0 /* is_insert */); + ret = aarch64_handle_breakpoint (type, addr, len, 0 /* is_insert */, state); if (show_debug_regs) { - struct aarch64_debug_reg_state *state - = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid)); - aarch64_show_debug_reg_state (state, "remove_hw_watchpoint", addr, len, type); } @@ -1372,88 +787,20 @@ aarch64_linux_remove_hw_breakpoint (struct target_ops *self, return ret; } -/* This is essentially the same as aarch64_handle_breakpoint, apart - from that it is an aligned watchpoint to be handled. */ - -static int -aarch64_handle_aligned_watchpoint (int type, CORE_ADDR addr, int len, - int is_insert) -{ - struct aarch64_debug_reg_state *state - = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid)); - - if (is_insert) - return aarch64_dr_state_insert_one_point (state, type, addr, len); - else - return aarch64_dr_state_remove_one_point (state, type, addr, len); -} - -/* Insert/remove unaligned watchpoint by calling - aarch64_align_watchpoint repeatedly until the whole watched region, - as represented by ADDR and LEN, has been properly aligned and ready - to be written to one or more hardware watchpoint registers. - IS_INSERT indicates whether this is an insertion or a deletion. - Return 0 if succeed. */ - -static int -aarch64_handle_unaligned_watchpoint (int type, CORE_ADDR addr, int len, - int is_insert) -{ - struct aarch64_debug_reg_state *state - = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid)); - - while (len > 0) - { - CORE_ADDR aligned_addr; - int aligned_len, ret; - - aarch64_align_watchpoint (addr, len, &aligned_addr, &aligned_len, - &addr, &len); - - if (is_insert) - ret = aarch64_dr_state_insert_one_point (state, type, aligned_addr, - aligned_len); - else - ret = aarch64_dr_state_remove_one_point (state, type, aligned_addr, - aligned_len); - - if (show_debug_regs) - fprintf_unfiltered (gdb_stdlog, -"handle_unaligned_watchpoint: is_insert: %d\n" -" aligned_addr: 0x%08lx, aligned_len: %d\n" -" next_addr: 0x%08lx, next_len: %d\n", - is_insert, aligned_addr, aligned_len, addr, len); - - if (ret != 0) - return ret; - } - - return 0; -} - -/* Implements insertion and removal of a single watchpoint. */ - -static int -aarch64_handle_watchpoint (int type, CORE_ADDR addr, int len, int is_insert) -{ - if (aarch64_point_is_aligned (1 /* is_watchpoint */ , addr, len)) - return aarch64_handle_aligned_watchpoint (type, addr, len, is_insert); - else - return aarch64_handle_unaligned_watchpoint (type, addr, len, is_insert); -} - -/* Implement the "to_insert_watchpoint" target_ops method. +/* Implement the "insert_watchpoint" target_ops method. Insert a watchpoint to watch a memory region which starts at address ADDR and whose length is LEN bytes. Watch memory accesses of the type TYPE. Return 0 on success, -1 on failure. */ -static int -aarch64_linux_insert_watchpoint (struct target_ops *self, - CORE_ADDR addr, int len, int type, - struct expression *cond) +int +aarch64_linux_nat_target::insert_watchpoint (CORE_ADDR addr, int len, + enum target_hw_bp_type type, + struct expression *cond) { int ret; + struct aarch64_debug_reg_state *state + = aarch64_get_debug_reg_state (inferior_ptid.pid ()); if (show_debug_regs) fprintf_unfiltered (gdb_stdlog, @@ -1462,13 +809,10 @@ aarch64_linux_insert_watchpoint (struct target_ops *self, gdb_assert (type != hw_execute); - ret = aarch64_handle_watchpoint (type, addr, len, 1 /* is_insert */); + ret = aarch64_handle_watchpoint (type, addr, len, 1 /* is_insert */, state); if (show_debug_regs) { - struct aarch64_debug_reg_state *state - = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid)); - aarch64_show_debug_reg_state (state, "insert_watchpoint", addr, len, type); } @@ -1476,17 +820,19 @@ aarch64_linux_insert_watchpoint (struct target_ops *self, return ret; } -/* Implement the "to_remove_watchpoint" target_ops method. +/* Implement the "remove_watchpoint" target_ops method. Remove a watchpoint that watched the memory region which starts at address ADDR, whose length is LEN bytes, and for accesses of the type TYPE. Return 0 on success, -1 on failure. */ -static int -aarch64_linux_remove_watchpoint (struct target_ops *self, - CORE_ADDR addr, int len, int type, - struct expression *cond) +int +aarch64_linux_nat_target::remove_watchpoint (CORE_ADDR addr, int len, + enum target_hw_bp_type type, + struct expression *cond) { int ret; + struct aarch64_debug_reg_state *state + = aarch64_get_debug_reg_state (inferior_ptid.pid ()); if (show_debug_regs) fprintf_unfiltered (gdb_stdlog, @@ -1495,13 +841,10 @@ aarch64_linux_remove_watchpoint (struct target_ops *self, gdb_assert (type != hw_execute); - ret = aarch64_handle_watchpoint (type, addr, len, 0 /* is_insert */); + ret = aarch64_handle_watchpoint (type, addr, len, 0 /* is_insert */, state); if (show_debug_regs) { - struct aarch64_debug_reg_state *state - = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid)); - aarch64_show_debug_reg_state (state, "remove_watchpoint", addr, len, type); } @@ -1509,105 +852,129 @@ aarch64_linux_remove_watchpoint (struct target_ops *self, return ret; } -/* Implement the "to_region_ok_for_hw_watchpoint" target_ops method. */ +/* Implement the "region_ok_for_hw_watchpoint" target_ops method. */ -static int -aarch64_linux_region_ok_for_hw_watchpoint (struct target_ops *self, - CORE_ADDR addr, int len) +int +aarch64_linux_nat_target::region_ok_for_hw_watchpoint (CORE_ADDR addr, int len) { - CORE_ADDR aligned_addr; - - /* Can not set watchpoints for zero or negative lengths. */ - if (len <= 0) - return 0; - - /* Must have hardware watchpoint debug register(s). */ - if (aarch64_num_wp_regs == 0) - return 0; - - /* We support unaligned watchpoint address and arbitrary length, - as long as the size of the whole watched area after alignment - doesn't exceed size of the total area that all watchpoint debug - registers can watch cooperatively. - - This is a very relaxed rule, but unfortunately there are - limitations, e.g. false-positive hits, due to limited support of - hardware debug registers in the kernel. See comment above - aarch64_align_watchpoint for more information. */ - - aligned_addr = addr & ~(AARCH64_HWP_MAX_LEN_PER_REG - 1); - if (aligned_addr + aarch64_num_wp_regs * AARCH64_HWP_MAX_LEN_PER_REG - < addr + len) - return 0; - - /* All tests passed so we are likely to be able to set the watchpoint. - The reason that it is 'likely' rather than 'must' is because - we don't check the current usage of the watchpoint registers, and - there may not be enough registers available for this watchpoint. - Ideally we should check the cached debug register state, however - the checking is costly. */ - return 1; + return aarch64_linux_region_ok_for_watchpoint (addr, len); } -/* Implement the "to_stopped_data_address" target_ops method. */ +/* Implement the "stopped_data_address" target_ops method. */ -static int -aarch64_linux_stopped_data_address (struct target_ops *target, - CORE_ADDR *addr_p) +bool +aarch64_linux_nat_target::stopped_data_address (CORE_ADDR *addr_p) { siginfo_t siginfo; - int i, tid; + int i; struct aarch64_debug_reg_state *state; if (!linux_nat_get_siginfo (inferior_ptid, &siginfo)) - return 0; + return false; /* This must be a hardware breakpoint. */ if (siginfo.si_signo != SIGTRAP || (siginfo.si_code & 0xffff) != TRAP_HWBKPT) - return 0; + return false; /* Check if the address matches any watched address. */ - state = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid)); + state = aarch64_get_debug_reg_state (inferior_ptid.pid ()); for (i = aarch64_num_wp_regs - 1; i >= 0; --i) { + const unsigned int offset + = aarch64_watchpoint_offset (state->dr_ctrl_wp[i]); const unsigned int len = aarch64_watchpoint_length (state->dr_ctrl_wp[i]); const CORE_ADDR addr_trap = (CORE_ADDR) siginfo.si_addr; - const CORE_ADDR addr_watch = state->dr_addr_wp[i]; + const CORE_ADDR addr_watch = state->dr_addr_wp[i] + offset; + const CORE_ADDR addr_watch_aligned = align_down (state->dr_addr_wp[i], 8); + const CORE_ADDR addr_orig = state->dr_addr_orig_wp[i]; if (state->dr_ref_count_wp[i] && DR_CONTROL_ENABLED (state->dr_ctrl_wp[i]) - && addr_trap >= addr_watch + && addr_trap >= addr_watch_aligned && addr_trap < addr_watch + len) { - *addr_p = addr_trap; - return 1; + /* ADDR_TRAP reports the first address of the memory range + accessed by the CPU, regardless of what was the memory + range watched. Thus, a large CPU access that straddles + the ADDR_WATCH..ADDR_WATCH+LEN range may result in an + ADDR_TRAP that is lower than the + ADDR_WATCH..ADDR_WATCH+LEN range. E.g.: + + addr: | 4 | 5 | 6 | 7 | 8 | + |---- range watched ----| + |----------- range accessed ------------| + + In this case, ADDR_TRAP will be 4. + + To match a watchpoint known to GDB core, we must never + report *ADDR_P outside of any ADDR_WATCH..ADDR_WATCH+LEN + range. ADDR_WATCH <= ADDR_TRAP < ADDR_ORIG is a false + positive on kernels older than 4.10. See PR + external/20207. */ + *addr_p = addr_orig; + return true; } } - return 0; + return false; } -/* Implement the "to_stopped_by_watchpoint" target_ops method. */ +/* Implement the "stopped_by_watchpoint" target_ops method. */ -static int -aarch64_linux_stopped_by_watchpoint (struct target_ops *ops) +bool +aarch64_linux_nat_target::stopped_by_watchpoint () { CORE_ADDR addr; - return aarch64_linux_stopped_data_address (ops, &addr); + return stopped_data_address (&addr); } -/* Implement the "to_watchpoint_addr_within_range" target_ops method. */ +/* Implement the "watchpoint_addr_within_range" target_ops method. */ -static int -aarch64_linux_watchpoint_addr_within_range (struct target_ops *target, - CORE_ADDR addr, - CORE_ADDR start, int length) +bool +aarch64_linux_nat_target::watchpoint_addr_within_range (CORE_ADDR addr, + CORE_ADDR start, int length) { return start <= addr && start + length - 1 >= addr; } +/* Implement the "can_do_single_step" target_ops method. */ + +int +aarch64_linux_nat_target::can_do_single_step () +{ + return 1; +} + +/* Implement the "thread_architecture" target_ops method. */ + +struct gdbarch * +aarch64_linux_nat_target::thread_architecture (ptid_t ptid) +{ + /* Return the gdbarch for the current thread. If the vector length has + changed since the last time this was called, then do a further lookup. */ + + uint64_t vq = aarch64_sve_get_vq (ptid.lwp ()); + + /* Find the current gdbarch the same way as process_stratum_target. Only + return it if the current vector length matches the one in the tdep. */ + inferior *inf = find_inferior_ptid (this, ptid); + gdb_assert (inf != NULL); + if (vq == gdbarch_tdep (inf->gdbarch)->vq) + return inf->gdbarch; + + /* We reach here if the vector length for the thread is different from its + value at process start. Lookup gdbarch via info (potentially creating a + new one), stashing the vector length inside id. Use -1 for when SVE + unavailable, to distinguish from an unset value of 0. */ + struct gdbarch_info info; + gdbarch_info_init (&info); + info.bfd_arch_info = bfd_lookup_arch (bfd_arch_aarch64, bfd_mach_aarch64); + info.id = (int *) (vq == 0 ? -1 : vq); + return gdbarch_find_by_info (info); +} + /* Define AArch64 maintenance commands. */ static void @@ -1629,45 +996,13 @@ triggers a breakpoint or watchpoint."), &maintenance_show_cmdlist); } -/* -Wmissing-prototypes. */ -void _initialize_aarch64_linux_nat (void); - +void _initialize_aarch64_linux_nat (); void -_initialize_aarch64_linux_nat (void) +_initialize_aarch64_linux_nat () { - struct target_ops *t; - - /* Fill in the generic GNU/Linux methods. */ - t = linux_target (); - add_show_debug_regs_command (); - /* Add our register access methods. */ - t->to_fetch_registers = aarch64_linux_fetch_inferior_registers; - t->to_store_registers = aarch64_linux_store_inferior_registers; - - t->to_read_description = aarch64_linux_read_description; - - t->to_can_use_hw_breakpoint = aarch64_linux_can_use_hw_breakpoint; - t->to_insert_hw_breakpoint = aarch64_linux_insert_hw_breakpoint; - t->to_remove_hw_breakpoint = aarch64_linux_remove_hw_breakpoint; - t->to_region_ok_for_hw_watchpoint = - aarch64_linux_region_ok_for_hw_watchpoint; - t->to_insert_watchpoint = aarch64_linux_insert_watchpoint; - t->to_remove_watchpoint = aarch64_linux_remove_watchpoint; - t->to_stopped_by_watchpoint = aarch64_linux_stopped_by_watchpoint; - t->to_stopped_data_address = aarch64_linux_stopped_data_address; - t->to_watchpoint_addr_within_range = - aarch64_linux_watchpoint_addr_within_range; - - /* Override the GNU/Linux inferior startup hook. */ - super_post_startup_inferior = t->to_post_startup_inferior; - t->to_post_startup_inferior = aarch64_linux_child_post_startup_inferior; - /* Register the target. */ - linux_nat_add_target (t); - linux_nat_set_new_thread (t, aarch64_linux_new_thread); - linux_nat_set_new_fork (t, aarch64_linux_new_fork); - linux_nat_set_forget_process (t, aarch64_forget_process); - linux_nat_set_prepare_to_resume (t, aarch64_linux_prepare_to_resume); + linux_target = &the_aarch64_linux_nat_target; + add_inf_child_target (&the_aarch64_linux_nat_target); }