X-Git-Url: http://git.efficios.com/?a=blobdiff_plain;f=gdb%2Famd64-tdep.c;h=67a4d3f11a959bf8c488f5f1f9340cbc3a1617ea;hb=deeafabb678e59d8585be6d765c7fbd0e7060b6c;hp=10bd31b269009bce09f473aee095871133c3ce5b;hpb=ecc37a5acc8ff504d62487149f61955343d35fcf;p=deliverable%2Fbinutils-gdb.git diff --git a/gdb/amd64-tdep.c b/gdb/amd64-tdep.c index 10bd31b269..67a4d3f11a 100644 --- a/gdb/amd64-tdep.c +++ b/gdb/amd64-tdep.c @@ -1,6 +1,6 @@ /* Target-dependent code for AMD64. - Copyright (C) 2001-2014 Free Software Foundation, Inc. + Copyright (C) 2001-2019 Free Software Foundation, Inc. Contributed by Jiri Smid, SuSE Labs. @@ -29,6 +29,7 @@ #include "frame-base.h" #include "frame-unwind.h" #include "inferior.h" +#include "infrun.h" #include "gdbcmd.h" #include "gdbcore.h" #include "objfiles.h" @@ -36,22 +37,18 @@ #include "regset.h" #include "symfile.h" #include "disasm.h" -#include "gdb_assert.h" -#include "exceptions.h" #include "amd64-tdep.h" #include "i387-tdep.h" - -#include "features/i386/amd64.c" -#include "features/i386/amd64-avx.c" -#include "features/i386/amd64-mpx.c" -#include "features/i386/amd64-avx512.c" - -#include "features/i386/x32.c" -#include "features/i386/x32-avx.c" -#include "features/i386/x32-avx512.c" - +#include "gdbsupport/x86-xstate.h" +#include +#include "target-descriptions.h" +#include "arch/amd64.h" +#include "producer.h" #include "ax.h" #include "ax-gdb.h" +#include "gdbsupport/byte-vector.h" +#include "osabi.h" +#include "x86-tdep.h" /* Note that the AMD64 architecture was previously known as x86-64. The latter is (forever) engraved into the canonical system name as @@ -154,6 +151,10 @@ static const char *amd64_xmm_avx512_names[] = { "xmm28", "xmm29", "xmm30", "xmm31" }; +static const char *amd64_pkeys_names[] = { + "pkru" +}; + /* DWARF Register Number Mapping as defined in the System V psABI, section 3.6. */ @@ -200,7 +201,13 @@ static int amd64_dwarf_regmap[] = AMD64_ST0_REGNUM + 2, AMD64_ST0_REGNUM + 3, AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5, AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7, - + + /* MMX Registers 0 - 7. + We have to handle those registers specifically, as their register + number within GDB depends on the target (or they may even not be + available at all). */ + -1, -1, -1, -1, -1, -1, -1, -1, + /* Control and Status Flags Register. */ AMD64_EFLAGS_REGNUM, @@ -246,9 +253,7 @@ amd64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) if (reg >= 0 && reg < amd64_dwarf_regmap_len) regnum = amd64_dwarf_regmap[reg]; - if (regnum == -1) - warning (_("Unmapped DWARF Register #%d encountered."), reg); - else if (ymm0_regnum >= 0 + if (ymm0_regnum >= 0 && i386_xmm_regnum_p (gdbarch, regnum)) regnum += ymm0_regnum - I387_XMM0_REGNUM (tdep); @@ -344,19 +349,15 @@ amd64_pseudo_register_name (struct gdbarch *gdbarch, int regnum) static struct value * amd64_pseudo_register_read_value (struct gdbarch *gdbarch, - struct regcache *regcache, + readable_regcache *regcache, int regnum) { - gdb_byte raw_buf[MAX_REGISTER_SIZE]; struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); - enum register_status status; - struct value *result_value; - gdb_byte *buf; - result_value = allocate_value (register_type (gdbarch, regnum)); + value *result_value = allocate_value (register_type (gdbarch, regnum)); VALUE_LVAL (result_value) = lval_register; VALUE_REGNUM (result_value) = regnum; - buf = value_contents_raw (result_value); + gdb_byte *buf = value_contents_raw (result_value); if (i386_byte_regnum_p (gdbarch, regnum)) { @@ -365,10 +366,11 @@ amd64_pseudo_register_read_value (struct gdbarch *gdbarch, /* Extract (always little endian). */ if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS) { + gpnum -= AMD64_NUM_LOWER_BYTE_REGS; + gdb_byte raw_buf[register_size (gdbarch, gpnum)]; + /* Special handling for AH, BH, CH, DH. */ - status = regcache_raw_read (regcache, - gpnum - AMD64_NUM_LOWER_BYTE_REGS, - raw_buf); + register_status status = regcache->raw_read (gpnum, raw_buf); if (status == REG_VALID) memcpy (buf, raw_buf + 1, 1); else @@ -377,7 +379,8 @@ amd64_pseudo_register_read_value (struct gdbarch *gdbarch, } else { - status = regcache_raw_read (regcache, gpnum, raw_buf); + gdb_byte raw_buf[register_size (gdbarch, gpnum)]; + register_status status = regcache->raw_read (gpnum, raw_buf); if (status == REG_VALID) memcpy (buf, raw_buf, 1); else @@ -388,8 +391,9 @@ amd64_pseudo_register_read_value (struct gdbarch *gdbarch, else if (i386_dword_regnum_p (gdbarch, regnum)) { int gpnum = regnum - tdep->eax_regnum; + gdb_byte raw_buf[register_size (gdbarch, gpnum)]; /* Extract (always little endian). */ - status = regcache_raw_read (regcache, gpnum, raw_buf); + register_status status = regcache->raw_read (gpnum, raw_buf); if (status == REG_VALID) memcpy (buf, raw_buf, 4); else @@ -408,7 +412,6 @@ amd64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, int regnum, const gdb_byte *buf) { - gdb_byte raw_buf[MAX_REGISTER_SIZE]; struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); if (i386_byte_regnum_p (gdbarch, regnum)) @@ -417,40 +420,73 @@ amd64_pseudo_register_write (struct gdbarch *gdbarch, if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS) { + gpnum -= AMD64_NUM_LOWER_BYTE_REGS; + gdb_byte raw_buf[register_size (gdbarch, gpnum)]; + /* Read ... AH, BH, CH, DH. */ - regcache_raw_read (regcache, - gpnum - AMD64_NUM_LOWER_BYTE_REGS, raw_buf); + regcache->raw_read (gpnum, raw_buf); /* ... Modify ... (always little endian). */ memcpy (raw_buf + 1, buf, 1); /* ... Write. */ - regcache_raw_write (regcache, - gpnum - AMD64_NUM_LOWER_BYTE_REGS, raw_buf); + regcache->raw_write (gpnum, raw_buf); } else { + gdb_byte raw_buf[register_size (gdbarch, gpnum)]; + /* Read ... */ - regcache_raw_read (regcache, gpnum, raw_buf); + regcache->raw_read (gpnum, raw_buf); /* ... Modify ... (always little endian). */ memcpy (raw_buf, buf, 1); /* ... Write. */ - regcache_raw_write (regcache, gpnum, raw_buf); + regcache->raw_write (gpnum, raw_buf); } } else if (i386_dword_regnum_p (gdbarch, regnum)) { int gpnum = regnum - tdep->eax_regnum; + gdb_byte raw_buf[register_size (gdbarch, gpnum)]; /* Read ... */ - regcache_raw_read (regcache, gpnum, raw_buf); + regcache->raw_read (gpnum, raw_buf); /* ... Modify ... (always little endian). */ memcpy (raw_buf, buf, 4); /* ... Write. */ - regcache_raw_write (regcache, gpnum, raw_buf); + regcache->raw_write (gpnum, raw_buf); } else i386_pseudo_register_write (gdbarch, regcache, regnum, buf); } +/* Implement the 'ax_pseudo_register_collect' gdbarch method. */ + +static int +amd64_ax_pseudo_register_collect (struct gdbarch *gdbarch, + struct agent_expr *ax, int regnum) +{ + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + + if (i386_byte_regnum_p (gdbarch, regnum)) + { + int gpnum = regnum - tdep->al_regnum; + + if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS) + ax_reg_mask (ax, gpnum - AMD64_NUM_LOWER_BYTE_REGS); + else + ax_reg_mask (ax, gpnum); + return 0; + } + else if (i386_dword_regnum_p (gdbarch, regnum)) + { + int gpnum = regnum - tdep->eax_regnum; + + ax_reg_mask (ax, gpnum); + return 0; + } + else + return i386_ax_pseudo_register_collect (gdbarch, ax, regnum); +} + /* Register classes as defined in the psABI. */ @@ -503,38 +539,128 @@ amd64_merge_classes (enum amd64_reg_class class1, enum amd64_reg_class class2) return AMD64_SSE; } -static void amd64_classify (struct type *type, enum amd64_reg_class class[2]); +static void amd64_classify (struct type *type, enum amd64_reg_class theclass[2]); -/* Return non-zero if TYPE is a non-POD structure or union type. */ +/* Return true if TYPE is a structure or union with unaligned fields. */ -static int -amd64_non_pod_p (struct type *type) +static bool +amd64_has_unaligned_fields (struct type *type) { - /* ??? A class with a base class certainly isn't POD, but does this - catch all non-POD structure types? */ - if (TYPE_CODE (type) == TYPE_CODE_STRUCT && TYPE_N_BASECLASSES (type) > 0) - return 1; + if (TYPE_CODE (type) == TYPE_CODE_STRUCT + || TYPE_CODE (type) == TYPE_CODE_UNION) + { + for (int i = 0; i < TYPE_NFIELDS (type); i++) + { + struct type *subtype = check_typedef (TYPE_FIELD_TYPE (type, i)); + int bitpos = TYPE_FIELD_BITPOS (type, i); + int align = type_align(subtype); + + /* Ignore static fields, empty fields (for example nested + empty structures), and bitfields (these are handled by + the caller). */ + if (field_is_static (&TYPE_FIELD (type, i)) + || (TYPE_FIELD_BITSIZE (type, i) == 0 + && TYPE_LENGTH (subtype) == 0) + || TYPE_FIELD_PACKED (type, i)) + continue; - return 0; + if (bitpos % 8 != 0) + return true; + + int bytepos = bitpos / 8; + if (bytepos % align != 0) + return true; + + if (amd64_has_unaligned_fields (subtype)) + return true; + } + } + + return false; +} + +/* Classify field I of TYPE starting at BITOFFSET according to the rules for + structures and union types, and store the result in THECLASS. */ + +static void +amd64_classify_aggregate_field (struct type *type, int i, + enum amd64_reg_class theclass[2], + unsigned int bitoffset) +{ + struct type *subtype = check_typedef (TYPE_FIELD_TYPE (type, i)); + int bitpos = bitoffset + TYPE_FIELD_BITPOS (type, i); + int pos = bitpos / 64; + enum amd64_reg_class subclass[2]; + int bitsize = TYPE_FIELD_BITSIZE (type, i); + int endpos; + + if (bitsize == 0) + bitsize = TYPE_LENGTH (subtype) * 8; + endpos = (bitpos + bitsize - 1) / 64; + + /* Ignore static fields, or empty fields, for example nested + empty structures.*/ + if (field_is_static (&TYPE_FIELD (type, i)) || bitsize == 0) + return; + + if (TYPE_CODE (subtype) == TYPE_CODE_STRUCT + || TYPE_CODE (subtype) == TYPE_CODE_UNION) + { + /* Each field of an object is classified recursively. */ + int j; + for (j = 0; j < TYPE_NFIELDS (subtype); j++) + amd64_classify_aggregate_field (subtype, j, theclass, bitpos); + return; + } + + gdb_assert (pos == 0 || pos == 1); + + amd64_classify (subtype, subclass); + theclass[pos] = amd64_merge_classes (theclass[pos], subclass[0]); + if (bitsize <= 64 && pos == 0 && endpos == 1) + /* This is a bit of an odd case: We have a field that would + normally fit in one of the two eightbytes, except that + it is placed in a way that this field straddles them. + This has been seen with a structure containing an array. + + The ABI is a bit unclear in this case, but we assume that + this field's class (stored in subclass[0]) must also be merged + into class[1]. In other words, our field has a piece stored + in the second eight-byte, and thus its class applies to + the second eight-byte as well. + + In the case where the field length exceeds 8 bytes, + it should not be necessary to merge the field class + into class[1]. As LEN > 8, subclass[1] is necessarily + different from AMD64_NO_CLASS. If subclass[1] is equal + to subclass[0], then the normal class[1]/subclass[1] + merging will take care of everything. For subclass[1] + to be different from subclass[0], I can only see the case + where we have a SSE/SSEUP or X87/X87UP pair, which both + use up all 16 bytes of the aggregate, and are already + handled just fine (because each portion sits on its own + 8-byte). */ + theclass[1] = amd64_merge_classes (theclass[1], subclass[0]); + if (pos == 0) + theclass[1] = amd64_merge_classes (theclass[1], subclass[1]); } /* Classify TYPE according to the rules for aggregate (structures and arrays) and union types, and store the result in CLASS. */ static void -amd64_classify_aggregate (struct type *type, enum amd64_reg_class class[2]) +amd64_classify_aggregate (struct type *type, enum amd64_reg_class theclass[2]) { - /* 1. If the size of an object is larger than two eightbytes, or in - C++, is a non-POD structure or union type, or contains + /* 1. If the size of an object is larger than two eightbytes, or it has unaligned fields, it has class memory. */ - if (TYPE_LENGTH (type) > 16 || amd64_non_pod_p (type)) + if (TYPE_LENGTH (type) > 16 || amd64_has_unaligned_fields (type)) { - class[0] = class[1] = AMD64_MEMORY; + theclass[0] = theclass[1] = AMD64_MEMORY; return; } /* 2. Both eightbytes get initialized to class NO_CLASS. */ - class[0] = class[1] = AMD64_NO_CLASS; + theclass[0] = theclass[1] = AMD64_NO_CLASS; /* 3. Each field of an object is classified recursively so that always two fields are considered. The resulting class is @@ -546,9 +672,9 @@ amd64_classify_aggregate (struct type *type, enum amd64_reg_class class[2]) struct type *subtype = check_typedef (TYPE_TARGET_TYPE (type)); /* All fields in an array have the same type. */ - amd64_classify (subtype, class); - if (TYPE_LENGTH (type) > 8 && class[1] == AMD64_NO_CLASS) - class[1] = class[0]; + amd64_classify (subtype, theclass); + if (TYPE_LENGTH (type) > 8 && theclass[1] == AMD64_NO_CLASS) + theclass[1] = theclass[0]; } else { @@ -559,78 +685,33 @@ amd64_classify_aggregate (struct type *type, enum amd64_reg_class class[2]) || TYPE_CODE (type) == TYPE_CODE_UNION); for (i = 0; i < TYPE_NFIELDS (type); i++) - { - struct type *subtype = check_typedef (TYPE_FIELD_TYPE (type, i)); - int pos = TYPE_FIELD_BITPOS (type, i) / 64; - enum amd64_reg_class subclass[2]; - int bitsize = TYPE_FIELD_BITSIZE (type, i); - int endpos; - - if (bitsize == 0) - bitsize = TYPE_LENGTH (subtype) * 8; - endpos = (TYPE_FIELD_BITPOS (type, i) + bitsize - 1) / 64; - - /* Ignore static fields. */ - if (field_is_static (&TYPE_FIELD (type, i))) - continue; - - gdb_assert (pos == 0 || pos == 1); - - amd64_classify (subtype, subclass); - class[pos] = amd64_merge_classes (class[pos], subclass[0]); - if (bitsize <= 64 && pos == 0 && endpos == 1) - /* This is a bit of an odd case: We have a field that would - normally fit in one of the two eightbytes, except that - it is placed in a way that this field straddles them. - This has been seen with a structure containing an array. - - The ABI is a bit unclear in this case, but we assume that - this field's class (stored in subclass[0]) must also be merged - into class[1]. In other words, our field has a piece stored - in the second eight-byte, and thus its class applies to - the second eight-byte as well. - - In the case where the field length exceeds 8 bytes, - it should not be necessary to merge the field class - into class[1]. As LEN > 8, subclass[1] is necessarily - different from AMD64_NO_CLASS. If subclass[1] is equal - to subclass[0], then the normal class[1]/subclass[1] - merging will take care of everything. For subclass[1] - to be different from subclass[0], I can only see the case - where we have a SSE/SSEUP or X87/X87UP pair, which both - use up all 16 bytes of the aggregate, and are already - handled just fine (because each portion sits on its own - 8-byte). */ - class[1] = amd64_merge_classes (class[1], subclass[0]); - if (pos == 0) - class[1] = amd64_merge_classes (class[1], subclass[1]); - } + amd64_classify_aggregate_field (type, i, theclass, 0); } /* 4. Then a post merger cleanup is done: */ /* Rule (a): If one of the classes is MEMORY, the whole argument is passed in memory. */ - if (class[0] == AMD64_MEMORY || class[1] == AMD64_MEMORY) - class[0] = class[1] = AMD64_MEMORY; + if (theclass[0] == AMD64_MEMORY || theclass[1] == AMD64_MEMORY) + theclass[0] = theclass[1] = AMD64_MEMORY; /* Rule (b): If SSEUP is not preceded by SSE, it is converted to SSE. */ - if (class[0] == AMD64_SSEUP) - class[0] = AMD64_SSE; - if (class[1] == AMD64_SSEUP && class[0] != AMD64_SSE) - class[1] = AMD64_SSE; + if (theclass[0] == AMD64_SSEUP) + theclass[0] = AMD64_SSE; + if (theclass[1] == AMD64_SSEUP && theclass[0] != AMD64_SSE) + theclass[1] = AMD64_SSE; } /* Classify TYPE, and store the result in CLASS. */ static void -amd64_classify (struct type *type, enum amd64_reg_class class[2]) +amd64_classify (struct type *type, enum amd64_reg_class theclass[2]) { enum type_code code = TYPE_CODE (type); int len = TYPE_LENGTH (type); - class[0] = class[1] = AMD64_NO_CLASS; + theclass[0] = theclass[1] = AMD64_NO_CLASS; /* Arguments of types (signed and unsigned) _Bool, char, short, int, long, long long, and pointers are in the INTEGER class. Similarly, @@ -639,30 +720,30 @@ amd64_classify (struct type *type, enum amd64_reg_class class[2]) if ((code == TYPE_CODE_INT || code == TYPE_CODE_ENUM || code == TYPE_CODE_BOOL || code == TYPE_CODE_RANGE || code == TYPE_CODE_CHAR - || code == TYPE_CODE_PTR || code == TYPE_CODE_REF) + || code == TYPE_CODE_PTR || TYPE_IS_REFERENCE (type)) && (len == 1 || len == 2 || len == 4 || len == 8)) - class[0] = AMD64_INTEGER; + theclass[0] = AMD64_INTEGER; /* Arguments of types float, double, _Decimal32, _Decimal64 and __m64 are in class SSE. */ else if ((code == TYPE_CODE_FLT || code == TYPE_CODE_DECFLOAT) && (len == 4 || len == 8)) /* FIXME: __m64 . */ - class[0] = AMD64_SSE; + theclass[0] = AMD64_SSE; /* Arguments of types __float128, _Decimal128 and __m128 are split into two halves. The least significant ones belong to class SSE, the most significant one to class SSEUP. */ else if (code == TYPE_CODE_DECFLOAT && len == 16) /* FIXME: __float128, __m128. */ - class[0] = AMD64_SSE, class[1] = AMD64_SSEUP; + theclass[0] = AMD64_SSE, theclass[1] = AMD64_SSEUP; /* The 64-bit mantissa of arguments of type long double belongs to class X87, the 16-bit exponent plus 6 bytes of padding belongs to class X87UP. */ else if (code == TYPE_CODE_FLT && len == 16) /* Class X87 and X87UP. */ - class[0] = AMD64_X87, class[1] = AMD64_X87UP; + theclass[0] = AMD64_X87, theclass[1] = AMD64_X87UP; /* Arguments of complex T where T is one of the types float or double get treated as if they are implemented as: @@ -670,21 +751,23 @@ amd64_classify (struct type *type, enum amd64_reg_class class[2]) struct complexT { T real; T imag; - }; */ + }; + + */ else if (code == TYPE_CODE_COMPLEX && len == 8) - class[0] = AMD64_SSE; + theclass[0] = AMD64_SSE; else if (code == TYPE_CODE_COMPLEX && len == 16) - class[0] = class[1] = AMD64_SSE; + theclass[0] = theclass[1] = AMD64_SSE; /* A variable of type complex long double is classified as type COMPLEX_X87. */ else if (code == TYPE_CODE_COMPLEX && len == 32) - class[0] = AMD64_COMPLEX_X87; + theclass[0] = AMD64_COMPLEX_X87; /* Aggregates. */ else if (code == TYPE_CODE_ARRAY || code == TYPE_CODE_STRUCT || code == TYPE_CODE_UNION) - amd64_classify_aggregate (type, class); + amd64_classify_aggregate (type, theclass); } static enum return_value_convention @@ -692,7 +775,7 @@ amd64_return_value (struct gdbarch *gdbarch, struct value *function, struct type *type, struct regcache *regcache, gdb_byte *readbuf, const gdb_byte *writebuf) { - enum amd64_reg_class class[2]; + enum amd64_reg_class theclass[2]; int len = TYPE_LENGTH (type); static int integer_regnum[] = { AMD64_RAX_REGNUM, AMD64_RDX_REGNUM }; static int sse_regnum[] = { AMD64_XMM0_REGNUM, AMD64_XMM1_REGNUM }; @@ -703,7 +786,7 @@ amd64_return_value (struct gdbarch *gdbarch, struct value *function, gdb_assert (!(readbuf && writebuf)); /* 1. Classify the return type with the classification algorithm. */ - amd64_classify (type, class); + amd64_classify (type, theclass); /* 2. If the type has class MEMORY, then the caller provides space for the return value and passes the address of this storage in @@ -712,7 +795,7 @@ amd64_return_value (struct gdbarch *gdbarch, struct value *function, On return %rax will contain the address that has been passed in by the caller in %rdi. */ - if (class[0] == AMD64_MEMORY) + if (theclass[0] == AMD64_MEMORY) { /* As indicated by the comment above, the ABI guarantees that we can always find the return value just after the function has @@ -731,19 +814,19 @@ amd64_return_value (struct gdbarch *gdbarch, struct value *function, /* 8. If the class is COMPLEX_X87, the real part of the value is returned in %st0 and the imaginary part in %st1. */ - if (class[0] == AMD64_COMPLEX_X87) + if (theclass[0] == AMD64_COMPLEX_X87) { if (readbuf) { - regcache_raw_read (regcache, AMD64_ST0_REGNUM, readbuf); - regcache_raw_read (regcache, AMD64_ST1_REGNUM, readbuf + 16); + regcache->raw_read (AMD64_ST0_REGNUM, readbuf); + regcache->raw_read (AMD64_ST1_REGNUM, readbuf + 16); } if (writebuf) { i387_return_value (gdbarch, regcache); - regcache_raw_write (regcache, AMD64_ST0_REGNUM, writebuf); - regcache_raw_write (regcache, AMD64_ST1_REGNUM, writebuf + 16); + regcache->raw_write (AMD64_ST0_REGNUM, writebuf); + regcache->raw_write (AMD64_ST1_REGNUM, writebuf + 16); /* Fix up the tag word such that both %st(0) and %st(1) are marked as valid. */ @@ -753,7 +836,7 @@ amd64_return_value (struct gdbarch *gdbarch, struct value *function, return RETURN_VALUE_REGISTER_CONVENTION; } - gdb_assert (class[1] != AMD64_MEMORY); + gdb_assert (theclass[1] != AMD64_MEMORY); gdb_assert (len <= 16); for (i = 0; len > 0; i++, len -= 8) @@ -761,7 +844,7 @@ amd64_return_value (struct gdbarch *gdbarch, struct value *function, int regnum = -1; int offset = 0; - switch (class[i]) + switch (theclass[i]) { case AMD64_INTEGER: /* 3. If the class is INTEGER, the next available register @@ -794,7 +877,7 @@ amd64_return_value (struct gdbarch *gdbarch, struct value *function, case AMD64_X87UP: /* 7. If the class is X87UP, the value is returned together with the previous X87 value in %st0. */ - gdb_assert (i > 0 && class[0] == AMD64_X87); + gdb_assert (i > 0 && theclass[0] == AMD64_X87); regnum = AMD64_ST0_REGNUM; offset = 8; len = 2; @@ -810,11 +893,11 @@ amd64_return_value (struct gdbarch *gdbarch, struct value *function, gdb_assert (regnum != -1); if (readbuf) - regcache_raw_read_part (regcache, regnum, offset, min (len, 8), - readbuf + i * 8); + regcache->raw_read_part (regnum, offset, std::min (len, 8), + readbuf + i * 8); if (writebuf) - regcache_raw_write_part (regcache, regnum, offset, min (len, 8), - writebuf + i * 8); + regcache->raw_write_part (regnum, offset, std::min (len, 8), + writebuf + i * 8); } return RETURN_VALUE_REGISTER_CONVENTION; @@ -822,8 +905,8 @@ amd64_return_value (struct gdbarch *gdbarch, struct value *function, static CORE_ADDR -amd64_push_arguments (struct regcache *regcache, int nargs, - struct value **args, CORE_ADDR sp, int struct_return) +amd64_push_arguments (struct regcache *regcache, int nargs, struct value **args, + CORE_ADDR sp, function_call_return_method return_method) { static int integer_regnum[] = { @@ -842,7 +925,7 @@ amd64_push_arguments (struct regcache *regcache, int nargs, AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5, AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7, }; - struct value **stack_args = alloca (nargs * sizeof (struct value *)); + struct value **stack_args = XALLOCAVEC (struct value *, nargs); int num_stack_args = 0; int num_elements = 0; int element = 0; @@ -851,28 +934,28 @@ amd64_push_arguments (struct regcache *regcache, int nargs, int i; /* Reserve a register for the "hidden" argument. */ - if (struct_return) +if (return_method == return_method_struct) integer_reg++; for (i = 0; i < nargs; i++) { struct type *type = value_type (args[i]); int len = TYPE_LENGTH (type); - enum amd64_reg_class class[2]; + enum amd64_reg_class theclass[2]; int needed_integer_regs = 0; int needed_sse_regs = 0; int j; /* Classify argument. */ - amd64_classify (type, class); + amd64_classify (type, theclass); /* Calculate the number of integer and SSE registers needed for this argument. */ for (j = 0; j < 2; j++) { - if (class[j] == AMD64_INTEGER) + if (theclass[j] == AMD64_INTEGER) needed_integer_regs++; - else if (class[j] == AMD64_SSE) + else if (theclass[j] == AMD64_SSE) needed_sse_regs++; } @@ -899,7 +982,7 @@ amd64_push_arguments (struct regcache *regcache, int nargs, int regnum = -1; int offset = 0; - switch (class[j]) + switch (theclass[j]) { case AMD64_INTEGER: regnum = integer_regnum[integer_reg++]; @@ -915,14 +998,17 @@ amd64_push_arguments (struct regcache *regcache, int nargs, offset = 8; break; + case AMD64_NO_CLASS: + continue; + default: gdb_assert (!"Unexpected register class."); } gdb_assert (regnum != -1); memset (buf, 0, sizeof buf); - memcpy (buf, valbuf + j * 8, min (len, 8)); - regcache_raw_write_part (regcache, regnum, offset, 8, buf); + memcpy (buf, valbuf + j * 8, std::min (len, 8)); + regcache->raw_write_part (regnum, offset, 8, buf); } } } @@ -957,19 +1043,27 @@ static CORE_ADDR amd64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, struct regcache *regcache, CORE_ADDR bp_addr, int nargs, struct value **args, CORE_ADDR sp, - int struct_return, CORE_ADDR struct_addr) + function_call_return_method return_method, + CORE_ADDR struct_addr) { enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); gdb_byte buf[8]; + /* BND registers can be in arbitrary values at the moment of the + inferior call. This can cause boundary violations that are not + due to a real bug or even desired by the user. The best to be done + is set the BND registers to allow access to the whole memory, INIT + state, before pushing the inferior call. */ + i387_reset_bnd_regs (gdbarch, regcache); + /* Pass arguments. */ - sp = amd64_push_arguments (regcache, nargs, args, sp, struct_return); + sp = amd64_push_arguments (regcache, nargs, args, sp, return_method); /* Pass "hidden" argument". */ - if (struct_return) + if (return_method == return_method_struct) { store_unsigned_integer (buf, 8, byte_order, struct_addr); - regcache_cooked_write (regcache, AMD64_RDI_REGNUM, buf); + regcache->cooked_write (AMD64_RDI_REGNUM, buf); } /* Store return address. */ @@ -979,10 +1073,10 @@ amd64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, /* Finally, update the stack pointer... */ store_unsigned_integer (buf, 8, byte_order, sp); - regcache_cooked_write (regcache, AMD64_RSP_REGNUM, buf); + regcache->cooked_write (AMD64_RSP_REGNUM, buf); /* ...and fake a frame pointer. */ - regcache_cooked_write (regcache, AMD64_RBP_REGNUM, buf); + regcache->cooked_write (AMD64_RBP_REGNUM, buf); return sp + 16; } @@ -996,8 +1090,9 @@ struct amd64_insn { /* The number of opcode bytes. */ int opcode_len; - /* The offset of the rex prefix or -1 if not present. */ - int rex_offset; + /* The offset of the REX/VEX instruction encoding prefix or -1 if + not present. */ + int enc_prefix_offset; /* The offset to the first opcode byte. */ int opcode_offset; /* The offset to the modrm byte or -1 if not present. */ @@ -1007,22 +1102,22 @@ struct amd64_insn gdb_byte *raw_insn; }; -struct displaced_step_closure +struct amd64_displaced_step_closure : public displaced_step_closure { + amd64_displaced_step_closure (int insn_buf_len) + : insn_buf (insn_buf_len, 0) + {} + /* For rip-relative insns, saved copy of the reg we use instead of %rip. */ - int tmp_used; + int tmp_used = 0; int tmp_regno; ULONGEST tmp_save; /* Details of the instruction. */ struct amd64_insn insn_details; - /* Amount of space allocated to insn_buf. */ - int max_len; - - /* The possibly modified insn. - This is a variable-length field. */ - gdb_byte insn_buf[1]; + /* The possibly modified insn. */ + gdb::byte_vector insn_buf; }; /* WARNING: Keep onebyte_has_modrm, twobyte_has_modrm in sync with @@ -1083,6 +1178,22 @@ rex_prefix_p (gdb_byte pfx) return REX_PREFIX_P (pfx); } +/* True if PFX is the start of the 2-byte VEX prefix. */ + +static bool +vex2_prefix_p (gdb_byte pfx) +{ + return pfx == 0xc5; +} + +/* True if PFX is the start of the 3-byte VEX prefix. */ + +static bool +vex3_prefix_p (gdb_byte pfx) +{ + return pfx == 0xc4; +} + /* Skip the legacy instruction prefixes in INSN. We assume INSN is properly sentineled so we don't have to worry about falling off the end of the buffer. */ @@ -1201,19 +1312,30 @@ amd64_get_insn_details (gdb_byte *insn, struct amd64_insn *details) details->raw_insn = insn; details->opcode_len = -1; - details->rex_offset = -1; + details->enc_prefix_offset = -1; details->opcode_offset = -1; details->modrm_offset = -1; /* Skip legacy instruction prefixes. */ insn = amd64_skip_prefixes (insn); - /* Skip REX instruction prefix. */ + /* Skip REX/VEX instruction encoding prefixes. */ if (rex_prefix_p (*insn)) { - details->rex_offset = insn - start; + details->enc_prefix_offset = insn - start; ++insn; } + else if (vex2_prefix_p (*insn)) + { + /* Don't record the offset in this case because this prefix has + no REX.B equivalent. */ + insn += 2; + } + else if (vex3_prefix_p (*insn)) + { + details->enc_prefix_offset = insn - start; + insn += 3; + } details->opcode_offset = insn - start; @@ -1263,15 +1385,13 @@ amd64_get_insn_details (gdb_byte *insn, struct amd64_insn *details) We set base = pc + insn_length so we can leave disp unchanged. */ static void -fixup_riprel (struct gdbarch *gdbarch, struct displaced_step_closure *dsc, +fixup_riprel (struct gdbarch *gdbarch, amd64_displaced_step_closure *dsc, CORE_ADDR from, CORE_ADDR to, struct regcache *regs) { - enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); const struct amd64_insn *insn_details = &dsc->insn_details; int modrm_offset = insn_details->modrm_offset; gdb_byte *insn = insn_details->raw_insn + modrm_offset; CORE_ADDR rip_base; - int32_t disp; int insn_length; int arch_tmp_regno, tmp_regno; ULONGEST orig_value; @@ -1280,9 +1400,8 @@ fixup_riprel (struct gdbarch *gdbarch, struct displaced_step_closure *dsc, ++insn; /* Compute the rip-relative address. */ - disp = extract_signed_integer (insn, sizeof (int32_t), byte_order); - insn_length = gdb_buffered_insn_length (gdbarch, dsc->insn_buf, - dsc->max_len, from); + insn_length = gdb_buffered_insn_length (gdbarch, dsc->insn_buf.data (), + dsc->insn_buf.size (), from); rip_base = from + insn_length; /* We need a register to hold the address. @@ -1291,10 +1410,22 @@ fixup_riprel (struct gdbarch *gdbarch, struct displaced_step_closure *dsc, arch_tmp_regno = amd64_get_unused_input_int_reg (insn_details); tmp_regno = amd64_arch_reg_to_regnum (arch_tmp_regno); - /* REX.B should be unset as we were using rip-relative addressing, - but ensure it's unset anyway, tmp_regno is not r8-r15. */ - if (insn_details->rex_offset != -1) - dsc->insn_buf[insn_details->rex_offset] &= ~REX_B; + /* Position of the not-B bit in the 3-byte VEX prefix (in byte 1). */ + static constexpr gdb_byte VEX3_NOT_B = 0x20; + + /* REX.B should be unset (VEX.!B set) as we were using rip-relative + addressing, but ensure it's unset (set for VEX) anyway, tmp_regno + is not r8-r15. */ + if (insn_details->enc_prefix_offset != -1) + { + gdb_byte *pfx = &dsc->insn_buf[insn_details->enc_prefix_offset]; + if (rex_prefix_p (pfx[0])) + pfx[0] &= ~REX_B; + else if (vex3_prefix_p (pfx[0])) + pfx[1] |= VEX3_NOT_B; + else + gdb_assert_not_reached ("unhandled prefix"); + } regcache_cooked_read_unsigned (regs, tmp_regno, &orig_value); dsc->tmp_regno = tmp_regno; @@ -1316,7 +1447,7 @@ fixup_riprel (struct gdbarch *gdbarch, struct displaced_step_closure *dsc, static void fixup_displaced_copy (struct gdbarch *gdbarch, - struct displaced_step_closure *dsc, + amd64_displaced_step_closure *dsc, CORE_ADDR from, CORE_ADDR to, struct regcache *regs) { const struct amd64_insn *details = &dsc->insn_details; @@ -1343,14 +1474,11 @@ amd64_displaced_step_copy_insn (struct gdbarch *gdbarch, /* Extra space for sentinels so fixup_{riprel,displaced_copy} don't have to continually watch for running off the end of the buffer. */ int fixup_sentinel_space = len; - struct displaced_step_closure *dsc = - xmalloc (sizeof (*dsc) + len + fixup_sentinel_space); + amd64_displaced_step_closure *dsc + = new amd64_displaced_step_closure (len + fixup_sentinel_space); gdb_byte *buf = &dsc->insn_buf[0]; struct amd64_insn *details = &dsc->insn_details; - dsc->tmp_used = 0; - dsc->max_len = len + fixup_sentinel_space; - read_memory (from, buf, len); /* Set up the sentinel space so we don't have to worry about running @@ -1506,7 +1634,7 @@ amd64_classify_insn_at (struct gdbarch *gdbarch, CORE_ADDR addr, int len, classification; len = gdbarch_max_insn_length (gdbarch); - buf = alloca (len); + buf = (gdb_byte *) alloca (len); read_code (addr, buf, len); amd64_get_insn_details (buf, &details); @@ -1545,14 +1673,15 @@ amd64_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr) void amd64_displaced_step_fixup (struct gdbarch *gdbarch, - struct displaced_step_closure *dsc, + struct displaced_step_closure *dsc_, CORE_ADDR from, CORE_ADDR to, struct regcache *regs) { + amd64_displaced_step_closure *dsc = (amd64_displaced_step_closure *) dsc_; enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); /* The offset we applied to the instruction's address. */ ULONGEST insn_offset = to - from; - gdb_byte *insn = dsc->insn_buf; + gdb_byte *insn = dsc->insn_buf.data (); const struct amd64_insn *insn_details = &dsc->insn_details; if (debug_displaced) @@ -1654,7 +1783,7 @@ amd64_displaced_step_fixup (struct gdbarch *gdbarch, regcache_cooked_read_unsigned (regs, AMD64_RSP_REGNUM, &rsp); retaddr = read_memory_unsigned_integer (rsp, retaddr_len, byte_order); - retaddr = (retaddr - insn_offset) & 0xffffffffUL; + retaddr = (retaddr - insn_offset) & 0xffffffffffffffffULL; write_memory_unsigned_integer (rsp, retaddr_len, byte_order, retaddr); if (debug_displaced) @@ -1703,7 +1832,7 @@ amd64_relocate_instruction (struct gdbarch *gdbarch, int len = gdbarch_max_insn_length (gdbarch); /* Extra space for sentinels. */ int fixup_sentinel_space = len; - gdb_byte *buf = xmalloc (len + fixup_sentinel_space); + gdb_byte *buf = (gdb_byte *) xmalloc (len + fixup_sentinel_space); struct amd64_insn insn_details; int offset = 0; LONGEST rel32, newrel; @@ -1730,15 +1859,47 @@ amd64_relocate_instruction (struct gdbarch *gdbarch, the user program would return to. */ if (insn[0] == 0xe8) { - gdb_byte push_buf[16]; - unsigned int ret_addr; + gdb_byte push_buf[32]; + CORE_ADDR ret_addr; + int i = 0; /* Where "ret" in the original code will return to. */ ret_addr = oldloc + insn_length; - push_buf[0] = 0x68; /* pushq $... */ - store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr); + + /* If pushing an address higher than or equal to 0x80000000, + avoid 'pushq', as that sign extends its 32-bit operand, which + would be incorrect. */ + if (ret_addr <= 0x7fffffff) + { + push_buf[0] = 0x68; /* pushq $... */ + store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr); + i = 5; + } + else + { + push_buf[i++] = 0x48; /* sub $0x8,%rsp */ + push_buf[i++] = 0x83; + push_buf[i++] = 0xec; + push_buf[i++] = 0x08; + + push_buf[i++] = 0xc7; /* movl $imm,(%rsp) */ + push_buf[i++] = 0x04; + push_buf[i++] = 0x24; + store_unsigned_integer (&push_buf[i], 4, byte_order, + ret_addr & 0xffffffff); + i += 4; + + push_buf[i++] = 0xc7; /* movl $imm,4(%rsp) */ + push_buf[i++] = 0x44; + push_buf[i++] = 0x24; + push_buf[i++] = 0x04; + store_unsigned_integer (&push_buf[i], 4, byte_order, + ret_addr >> 32); + i += 4; + } + gdb_assert (i <= sizeof (push_buf)); /* Push the push. */ - append_insns (to, 5, push_buf); + append_insns (to, i, push_buf); /* Convert the relative call to a relative jump. */ insn[0] = 0xe9; @@ -2001,7 +2162,7 @@ amd64_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, if (current_pc > pc + offset_and) cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg); - return min (pc + offset + 2, current_pc); + return std::min (pc + offset + 2, current_pc); } /* Similar to amd64_analyze_stack_align for x32. */ @@ -2183,7 +2344,7 @@ amd64_x32_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, if (current_pc > pc + offset_and) cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg); - return min (pc + offset + 2, current_pc); + return std::min (pc + offset + 2, current_pc); } /* Do a limited analysis of the prologue at PC and update CACHE @@ -2300,7 +2461,8 @@ amd64_skip_xmm_prologue (CORE_ADDR pc, CORE_ADDR start_pc) start_pc_sal = find_pc_sect_line (start_pc, NULL, 0); if (start_pc_sal.symtab == NULL - || producer_is_gcc_ge_4 (start_pc_sal.symtab->producer) < 6 + || producer_is_gcc_ge_4 (COMPUNIT_PRODUCER + (SYMTAB_COMPUNIT (start_pc_sal.symtab))) < 6 || start_pc_sal.pc != start_pc || pc >= start_pc_sal.end) return pc; @@ -2363,15 +2525,15 @@ amd64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) { CORE_ADDR post_prologue_pc = skip_prologue_using_sal (gdbarch, func_addr); - struct symtab *s = find_pc_symtab (func_addr); + struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr); /* Clang always emits a line note before the prologue and another one after. We trust clang to emit usable line notes. */ if (post_prologue_pc - && (s != NULL - && s->producer != NULL - && strncmp (s->producer, "clang ", sizeof ("clang ") - 1) == 0)) - return max (start_pc, post_prologue_pc); + && (cust != NULL + && COMPUNIT_PRODUCER (cust) != NULL + && startswith (COMPUNIT_PRODUCER (cust), "clang "))) + return std::max (start_pc, post_prologue_pc); } amd64_init_frame_cache (&cache); @@ -2458,21 +2620,23 @@ amd64_frame_cache_1 (struct frame_info *this_frame, static struct amd64_frame_cache * amd64_frame_cache (struct frame_info *this_frame, void **this_cache) { - volatile struct gdb_exception ex; struct amd64_frame_cache *cache; if (*this_cache) - return *this_cache; + return (struct amd64_frame_cache *) *this_cache; cache = amd64_alloc_frame_cache (); *this_cache = cache; - TRY_CATCH (ex, RETURN_MASK_ERROR) + try { amd64_frame_cache_1 (this_frame, cache); } - if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) - throw_exception (ex); + catch (const gdb_exception_error &ex) + { + if (ex.error != NOT_AVAILABLE_ERROR) + throw; + } return cache; } @@ -2571,18 +2735,17 @@ amd64_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache) struct gdbarch *gdbarch = get_frame_arch (this_frame); struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); - volatile struct gdb_exception ex; struct amd64_frame_cache *cache; CORE_ADDR addr; gdb_byte buf[8]; int i; if (*this_cache) - return *this_cache; + return (struct amd64_frame_cache *) *this_cache; cache = amd64_alloc_frame_cache (); - TRY_CATCH (ex, RETURN_MASK_ERROR) + try { get_frame_register (this_frame, AMD64_RSP_REGNUM, buf); cache->base = extract_unsigned_integer (buf, 8, byte_order) - 8; @@ -2596,8 +2759,11 @@ amd64_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache) cache->base_p = 1; } - if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) - throw_exception (ex); + catch (const gdb_exception_error &ex) + { + if (ex.error != NOT_AVAILABLE_ERROR) + throw; + } *this_cache = cache; return cache; @@ -2704,18 +2870,20 @@ static const struct frame_base amd64_frame_base = /* Normal frames, but in a function epilogue. */ -/* The epilogue is defined here as the 'ret' instruction, which will +/* Implement the stack_frame_destroyed_p gdbarch method. + + The epilogue is defined here as the 'ret' instruction, which will follow any instruction such as 'leave' or 'pop %ebp' that destroys the function's stack frame. */ static int -amd64_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) +amd64_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) { gdb_byte insn; - struct symtab *symtab; + struct compunit_symtab *cust; - symtab = find_pc_symtab (pc); - if (symtab && symtab->epilogue_unwind_valid) + cust = find_pc_compunit_symtab (pc); + if (cust != NULL && COMPUNIT_EPILOGUE_UNWIND_VALID (cust)) return 0; if (target_read_memory (pc, &insn, 1)) @@ -2733,8 +2901,8 @@ amd64_epilogue_frame_sniffer (const struct frame_unwind *self, void **this_prologue_cache) { if (frame_relative_level (this_frame) == 0) - return amd64_in_function_epilogue_p (get_frame_arch (this_frame), - get_frame_pc (this_frame)); + return amd64_stack_frame_destroyed_p (get_frame_arch (this_frame), + get_frame_pc (this_frame)); else return 0; } @@ -2744,17 +2912,16 @@ amd64_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache) { struct gdbarch *gdbarch = get_frame_arch (this_frame); enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); - volatile struct gdb_exception ex; struct amd64_frame_cache *cache; gdb_byte buf[8]; if (*this_cache) - return *this_cache; + return (struct amd64_frame_cache *) *this_cache; cache = amd64_alloc_frame_cache (); *this_cache = cache; - TRY_CATCH (ex, RETURN_MASK_ERROR) + try { /* Cache base will be %esp plus cache->sp_offset (-8). */ get_frame_register (this_frame, AMD64_RSP_REGNUM, buf); @@ -2772,8 +2939,11 @@ amd64_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache) cache->base_p = 1; } - if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) - throw_exception (ex); + catch (const gdb_exception_error &ex) + { + if (ex.error != NOT_AVAILABLE_ERROR) + throw; + } return cache; } @@ -2842,10 +3012,10 @@ static void amd64_supply_fpregset (const struct regset *regset, struct regcache *regcache, int regnum, const void *fpregs, size_t len) { - struct gdbarch *gdbarch = get_regcache_arch (regcache); + struct gdbarch *gdbarch = regcache->arch (); const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); - gdb_assert (len == tdep->sizeof_fpregset); + gdb_assert (len >= tdep->sizeof_fpregset); amd64_supply_fxsave (regcache, regnum, fpregs); } @@ -2859,60 +3029,17 @@ amd64_collect_fpregset (const struct regset *regset, const struct regcache *regcache, int regnum, void *fpregs, size_t len) { - struct gdbarch *gdbarch = get_regcache_arch (regcache); + struct gdbarch *gdbarch = regcache->arch (); const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); - gdb_assert (len == tdep->sizeof_fpregset); + gdb_assert (len >= tdep->sizeof_fpregset); amd64_collect_fxsave (regcache, regnum, fpregs); } -/* Similar to amd64_supply_fpregset, but use XSAVE extended state. */ - -static void -amd64_supply_xstateregset (const struct regset *regset, - struct regcache *regcache, int regnum, - const void *xstateregs, size_t len) -{ - amd64_supply_xsave (regcache, regnum, xstateregs); -} - -/* Similar to amd64_collect_fpregset, but use XSAVE extended state. */ - -static void -amd64_collect_xstateregset (const struct regset *regset, - const struct regcache *regcache, - int regnum, void *xstateregs, size_t len) -{ - amd64_collect_xsave (regcache, regnum, xstateregs, 1); -} - -static const struct regset amd64_fpregset = +const struct regset amd64_fpregset = { NULL, amd64_supply_fpregset, amd64_collect_fpregset }; - -static const struct regset amd64_xstateregset = - { - NULL, amd64_supply_xstateregset, amd64_collect_xstateregset - }; - -/* Return the appropriate register set for the core section identified - by SECT_NAME and SECT_SIZE. */ - -static const struct regset * -amd64_regset_from_core_section (struct gdbarch *gdbarch, - const char *sect_name, size_t sect_size) -{ - struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); - - if (strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset) - return &amd64_fpregset; - - if (strcmp (sect_name, ".reg-xstate") == 0) - return &amd64_xstateregset; - - return i386_regset_from_core_section (gdbarch, sect_name, sect_size); -} /* Figure out where the longjmp will land. Slurp the jmp_buf out of @@ -2956,8 +3083,19 @@ static const int amd64_record_regmap[] = AMD64_DS_REGNUM, AMD64_ES_REGNUM, AMD64_FS_REGNUM, AMD64_GS_REGNUM }; +/* Implement the "in_indirect_branch_thunk" gdbarch function. */ + +static bool +amd64_in_indirect_branch_thunk (struct gdbarch *gdbarch, CORE_ADDR pc) +{ + return x86_in_indirect_branch_thunk (pc, amd64_register_names, + AMD64_RAX_REGNUM, + AMD64_RIP_REGNUM); +} + void -amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) +amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch, + const target_desc *default_tdesc) { struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); const struct target_desc *tdesc = info.target_desc; @@ -2971,9 +3109,10 @@ amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) /* AMD64 generally uses `fxsave' instead of `fsave' for saving its floating-point registers. */ tdep->sizeof_fpregset = I387_SIZEOF_FXSAVE; + tdep->fpregset = &amd64_fpregset; if (! tdesc_has_registers (tdesc)) - tdesc = tdesc_amd64; + tdesc = default_tdesc; tdep->tdesc = tdesc; tdep->num_core_regs = AMD64_NUM_GREGS + I387_NUM_REGS; @@ -3010,6 +3149,18 @@ amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) tdep->bnd0r_regnum = AMD64_BND0R_REGNUM; } + if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.segments") != NULL) + { + tdep->fsbase_regnum = AMD64_FSBASE_REGNUM; + } + + if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.pkeys") != NULL) + { + tdep->pkeys_register_names = amd64_pkeys_names; + tdep->pkru_regnum = AMD64_PKRU_REGNUM; + tdep->num_pkeys_regs = 1; + } + tdep->num_byte_regs = 20; tdep->num_word_regs = 16; tdep->num_dword_regs = 16; @@ -3020,6 +3171,8 @@ amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) amd64_pseudo_register_read_value); set_gdbarch_pseudo_register_write (gdbarch, amd64_pseudo_register_write); + set_gdbarch_ax_pseudo_register_collect (gdbarch, + amd64_ax_pseudo_register_collect); set_tdesc_pseudo_register_name (gdbarch, amd64_pseudo_register_name); @@ -3084,11 +3237,6 @@ amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) frame_unwind_append_unwinder (gdbarch, &amd64_frame_unwind); frame_base_set_default (gdbarch, &amd64_frame_base); - /* If we have a register mapping, enable the generic core file support. */ - if (tdep->gregset_reg_offset) - set_gdbarch_regset_from_core_section (gdbarch, - amd64_regset_from_core_section); - set_gdbarch_get_longjmp_target (gdbarch, amd64_get_longjmp_target); set_gdbarch_relocate_instruction (gdbarch, amd64_relocate_instruction); @@ -3109,8 +3257,19 @@ amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) set_gdbarch_insn_is_call (gdbarch, amd64_insn_is_call); set_gdbarch_insn_is_ret (gdbarch, amd64_insn_is_ret); set_gdbarch_insn_is_jump (gdbarch, amd64_insn_is_jump); + + set_gdbarch_in_indirect_branch_thunk (gdbarch, + amd64_in_indirect_branch_thunk); +} + +/* Initialize ARCH for x86-64, no osabi. */ + +static void +amd64_none_init_abi (gdbarch_info info, gdbarch *arch) +{ + amd64_init_abi (info, arch, amd64_target_description (X86_XSTATE_SSE_MASK, + true)); } - static struct type * amd64_x32_pseudo_register_type (struct gdbarch *gdbarch, int regnum) @@ -3130,16 +3289,12 @@ amd64_x32_pseudo_register_type (struct gdbarch *gdbarch, int regnum) } void -amd64_x32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) +amd64_x32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch, + const target_desc *default_tdesc) { struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); - const struct target_desc *tdesc = info.target_desc; - amd64_init_abi (info, gdbarch); - - if (! tdesc_has_registers (tdesc)) - tdesc = tdesc_x32; - tdep->tdesc = tdesc; + amd64_init_abi (info, gdbarch, default_tdesc); tdep->num_dword_regs = 17; set_tdesc_pseudo_register_type (gdbarch, amd64_x32_pseudo_register_type); @@ -3148,20 +3303,44 @@ amd64_x32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) set_gdbarch_ptr_bit (gdbarch, 32); } -/* Provide a prototype to silence -Wmissing-prototypes. */ -void _initialize_amd64_tdep (void); +/* Initialize ARCH for x64-32, no osabi. */ + +static void +amd64_x32_none_init_abi (gdbarch_info info, gdbarch *arch) +{ + amd64_x32_init_abi (info, arch, + amd64_target_description (X86_XSTATE_SSE_MASK, true)); +} + +/* Return the target description for a specified XSAVE feature mask. */ + +const struct target_desc * +amd64_target_description (uint64_t xcr0, bool segments) +{ + static target_desc *amd64_tdescs \ + [2/*AVX*/][2/*MPX*/][2/*AVX512*/][2/*PKRU*/][2/*segments*/] = {}; + target_desc **tdesc; + + tdesc = &amd64_tdescs[(xcr0 & X86_XSTATE_AVX) ? 1 : 0] + [(xcr0 & X86_XSTATE_MPX) ? 1 : 0] + [(xcr0 & X86_XSTATE_AVX512) ? 1 : 0] + [(xcr0 & X86_XSTATE_PKRU) ? 1 : 0] + [segments ? 1 : 0]; + + if (*tdesc == NULL) + *tdesc = amd64_create_target_description (xcr0, false, false, + segments); + + return *tdesc; +} void _initialize_amd64_tdep (void) { - initialize_tdesc_amd64 (); - initialize_tdesc_amd64_avx (); - initialize_tdesc_amd64_mpx (); - initialize_tdesc_amd64_avx512 (); - - initialize_tdesc_x32 (); - initialize_tdesc_x32_avx (); - initialize_tdesc_x32_avx512 (); + gdbarch_register_osabi (bfd_arch_i386, bfd_mach_x86_64, GDB_OSABI_NONE, + amd64_none_init_abi); + gdbarch_register_osabi (bfd_arch_i386, bfd_mach_x64_32, GDB_OSABI_NONE, + amd64_x32_none_init_abi); } @@ -3181,7 +3360,7 @@ void amd64_supply_fxsave (struct regcache *regcache, int regnum, const void *fxsave) { - struct gdbarch *gdbarch = get_regcache_arch (regcache); + struct gdbarch *gdbarch = regcache->arch (); struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); i387_supply_fxsave (regcache, regnum, fxsave); @@ -3189,12 +3368,12 @@ amd64_supply_fxsave (struct regcache *regcache, int regnum, if (fxsave && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64) { - const gdb_byte *regs = fxsave; + const gdb_byte *regs = (const gdb_byte *) fxsave; if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep)) - regcache_raw_supply (regcache, I387_FISEG_REGNUM (tdep), regs + 12); + regcache->raw_supply (I387_FISEG_REGNUM (tdep), regs + 12); if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep)) - regcache_raw_supply (regcache, I387_FOSEG_REGNUM (tdep), regs + 20); + regcache->raw_supply (I387_FOSEG_REGNUM (tdep), regs + 20); } } @@ -3204,7 +3383,7 @@ void amd64_supply_xsave (struct regcache *regcache, int regnum, const void *xsave) { - struct gdbarch *gdbarch = get_regcache_arch (regcache); + struct gdbarch *gdbarch = regcache->arch (); struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); i387_supply_xsave (regcache, regnum, xsave); @@ -3212,14 +3391,21 @@ amd64_supply_xsave (struct regcache *regcache, int regnum, if (xsave && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64) { - const gdb_byte *regs = xsave; + const gdb_byte *regs = (const gdb_byte *) xsave; + ULONGEST clear_bv; - if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep)) - regcache_raw_supply (regcache, I387_FISEG_REGNUM (tdep), - regs + 12); - if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep)) - regcache_raw_supply (regcache, I387_FOSEG_REGNUM (tdep), - regs + 20); + clear_bv = i387_xsave_get_clear_bv (gdbarch, xsave); + + /* If the FISEG and FOSEG registers have not been initialised yet + (their CLEAR_BV bit is set) then their default values of zero will + have already been setup by I387_SUPPLY_XSAVE. */ + if (!(clear_bv & X86_XSTATE_X87)) + { + if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep)) + regcache->raw_supply (I387_FISEG_REGNUM (tdep), regs + 12); + if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep)) + regcache->raw_supply (I387_FOSEG_REGNUM (tdep), regs + 20); + } } } @@ -3232,18 +3418,18 @@ void amd64_collect_fxsave (const struct regcache *regcache, int regnum, void *fxsave) { - struct gdbarch *gdbarch = get_regcache_arch (regcache); + struct gdbarch *gdbarch = regcache->arch (); struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); - gdb_byte *regs = fxsave; + gdb_byte *regs = (gdb_byte *) fxsave; i387_collect_fxsave (regcache, regnum, fxsave); if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64) { if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep)) - regcache_raw_collect (regcache, I387_FISEG_REGNUM (tdep), regs + 12); + regcache->raw_collect (I387_FISEG_REGNUM (tdep), regs + 12); if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep)) - regcache_raw_collect (regcache, I387_FOSEG_REGNUM (tdep), regs + 20); + regcache->raw_collect (I387_FOSEG_REGNUM (tdep), regs + 20); } } @@ -3253,19 +3439,19 @@ void amd64_collect_xsave (const struct regcache *regcache, int regnum, void *xsave, int gcore) { - struct gdbarch *gdbarch = get_regcache_arch (regcache); + struct gdbarch *gdbarch = regcache->arch (); struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); - gdb_byte *regs = xsave; + gdb_byte *regs = (gdb_byte *) xsave; i387_collect_xsave (regcache, regnum, xsave, gcore); if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64) { if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep)) - regcache_raw_collect (regcache, I387_FISEG_REGNUM (tdep), + regcache->raw_collect (I387_FISEG_REGNUM (tdep), regs + 12); if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep)) - regcache_raw_collect (regcache, I387_FOSEG_REGNUM (tdep), + regcache->raw_collect (I387_FOSEG_REGNUM (tdep), regs + 20); } }